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1/*2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER20 * DEALINGS IN THE SOFTWARE.21 *22 */23 24#ifndef __NVKM_CLK_GK20A_H__25#define __NVKM_CLK_GK20A_H__26 27#define KHZ (1000)28#define MHZ (KHZ * 1000)29 30#define MASK(w) ((1 << (w)) - 1)31 32#define GK20A_CLK_GPC_MDIV 100033 34#define SYS_GPCPLL_CFG_BASE 0x0013700035#define GPCPLL_CFG (SYS_GPCPLL_CFG_BASE + 0)36#define GPCPLL_CFG_ENABLE BIT(0)37#define GPCPLL_CFG_IDDQ BIT(1)38#define GPCPLL_CFG_LOCK_DET_OFF BIT(4)39#define GPCPLL_CFG_LOCK BIT(17)40 41#define GPCPLL_CFG2 (SYS_GPCPLL_CFG_BASE + 0xc)42#define GPCPLL_CFG2_SETUP2_SHIFT 1643#define GPCPLL_CFG2_PLL_STEPA_SHIFT 2444 45#define GPCPLL_CFG3 (SYS_GPCPLL_CFG_BASE + 0x18)46#define GPCPLL_CFG3_VCO_CTRL_SHIFT 047#define GPCPLL_CFG3_VCO_CTRL_WIDTH 948#define GPCPLL_CFG3_VCO_CTRL_MASK \49 (MASK(GPCPLL_CFG3_VCO_CTRL_WIDTH) << GPCPLL_CFG3_VCO_CTRL_SHIFT)50#define GPCPLL_CFG3_PLL_STEPB_SHIFT 1651#define GPCPLL_CFG3_PLL_STEPB_WIDTH 852 53#define GPCPLL_COEFF (SYS_GPCPLL_CFG_BASE + 4)54#define GPCPLL_COEFF_M_SHIFT 055#define GPCPLL_COEFF_M_WIDTH 856#define GPCPLL_COEFF_N_SHIFT 857#define GPCPLL_COEFF_N_WIDTH 858#define GPCPLL_COEFF_N_MASK \59 (MASK(GPCPLL_COEFF_N_WIDTH) << GPCPLL_COEFF_N_SHIFT)60#define GPCPLL_COEFF_P_SHIFT 1661#define GPCPLL_COEFF_P_WIDTH 662 63#define GPCPLL_NDIV_SLOWDOWN (SYS_GPCPLL_CFG_BASE + 0x1c)64#define GPCPLL_NDIV_SLOWDOWN_NDIV_LO_SHIFT 065#define GPCPLL_NDIV_SLOWDOWN_NDIV_MID_SHIFT 866#define GPCPLL_NDIV_SLOWDOWN_STEP_SIZE_LO2MID_SHIFT 1667#define GPCPLL_NDIV_SLOWDOWN_SLOWDOWN_USING_PLL_SHIFT 2268#define GPCPLL_NDIV_SLOWDOWN_EN_DYNRAMP_SHIFT 3169 70#define GPC_BCAST_GPCPLL_CFG_BASE 0x0013280071#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG (GPC_BCAST_GPCPLL_CFG_BASE + 0xa0)72#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT 2473#define GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_MASK \74 (0x1 << GPC_BCAST_NDIV_SLOWDOWN_DEBUG_PLL_DYNRAMP_DONE_SYNCED_SHIFT)75 76#define SEL_VCO (SYS_GPCPLL_CFG_BASE + 0x100)77#define SEL_VCO_GPC2CLK_OUT_SHIFT 078 79#define GPC2CLK_OUT (SYS_GPCPLL_CFG_BASE + 0x250)80#define GPC2CLK_OUT_SDIV14_INDIV4_WIDTH 181#define GPC2CLK_OUT_SDIV14_INDIV4_SHIFT 3182#define GPC2CLK_OUT_SDIV14_INDIV4_MODE 183#define GPC2CLK_OUT_VCODIV_WIDTH 684#define GPC2CLK_OUT_VCODIV_SHIFT 885#define GPC2CLK_OUT_VCODIV1 086#define GPC2CLK_OUT_VCODIV2 287#define GPC2CLK_OUT_VCODIV_MASK (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << \88 GPC2CLK_OUT_VCODIV_SHIFT)89#define GPC2CLK_OUT_BYPDIV_WIDTH 690#define GPC2CLK_OUT_BYPDIV_SHIFT 091#define GPC2CLK_OUT_BYPDIV31 0x3c92#define GPC2CLK_OUT_INIT_MASK ((MASK(GPC2CLK_OUT_SDIV14_INDIV4_WIDTH) << \93 GPC2CLK_OUT_SDIV14_INDIV4_SHIFT)\94 | (MASK(GPC2CLK_OUT_VCODIV_WIDTH) << GPC2CLK_OUT_VCODIV_SHIFT)\95 | (MASK(GPC2CLK_OUT_BYPDIV_WIDTH) << GPC2CLK_OUT_BYPDIV_SHIFT))96#define GPC2CLK_OUT_INIT_VAL ((GPC2CLK_OUT_SDIV14_INDIV4_MODE << \97 GPC2CLK_OUT_SDIV14_INDIV4_SHIFT) \98 | (GPC2CLK_OUT_VCODIV1 << GPC2CLK_OUT_VCODIV_SHIFT) \99 | (GPC2CLK_OUT_BYPDIV31 << GPC2CLK_OUT_BYPDIV_SHIFT))100 101/* All frequencies in Khz */102struct gk20a_clk_pllg_params {103 u32 min_vco, max_vco;104 u32 min_u, max_u;105 u32 min_m, max_m;106 u32 min_n, max_n;107 u32 min_pl, max_pl;108};109 110struct gk20a_pll {111 u32 m;112 u32 n;113 u32 pl;114};115 116struct gk20a_clk {117 struct nvkm_clk base;118 const struct gk20a_clk_pllg_params *params;119 struct gk20a_pll pll;120 u32 parent_rate;121 122 u32 (*div_to_pl)(u32);123 u32 (*pl_to_div)(u32);124};125#define gk20a_clk(p) container_of((p), struct gk20a_clk, base)126 127u32 gk20a_pllg_calc_rate(struct gk20a_clk *, struct gk20a_pll *);128int gk20a_pllg_calc_mnp(struct gk20a_clk *, unsigned long, struct gk20a_pll *);129void gk20a_pllg_read_mnp(struct gk20a_clk *, struct gk20a_pll *);130void gk20a_pllg_write_mnp(struct gk20a_clk *, const struct gk20a_pll *);131 132static inline bool133gk20a_pllg_is_enabled(struct gk20a_clk *clk)134{135 struct nvkm_device *device = clk->base.subdev.device;136 u32 val;137 138 val = nvkm_rd32(device, GPCPLL_CFG);139 return val & GPCPLL_CFG_ENABLE;140}141 142static inline u32143gk20a_pllg_n_lo(struct gk20a_clk *clk, struct gk20a_pll *pll)144{145 return DIV_ROUND_UP(pll->m * clk->params->min_vco,146 clk->parent_rate / KHZ);147}148 149int gk20a_clk_ctor(struct nvkm_device *, enum nvkm_subdev_type, int, const struct nvkm_clk_func *,150 const struct gk20a_clk_pllg_params *, struct gk20a_clk *);151void gk20a_clk_fini(struct nvkm_clk *);152int gk20a_clk_read(struct nvkm_clk *, enum nv_clk_src);153int gk20a_clk_calc(struct nvkm_clk *, struct nvkm_cstate *);154int gk20a_clk_prog(struct nvkm_clk *);155void gk20a_clk_tidy(struct nvkm_clk *);156 157int gk20a_clk_setup_slide(struct gk20a_clk *);158 159#endif160