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1/*2 * Copyright (C) 2010 Francisco Jerez.3 * All Rights Reserved.4 *5 * Permission is hereby granted, free of charge, to any person obtaining6 * a copy of this software and associated documentation files (the7 * "Software"), to deal in the Software without restriction, including8 * without limitation the rights to use, copy, modify, merge, publish,9 * distribute, sublicense, and/or sell copies of the Software, and to10 * permit persons to whom the Software is furnished to do so, subject to11 * the following conditions:12 *13 * The above copyright notice and this permission notice (including the14 * next paragraph) shall be included in all copies or substantial15 * portions of the Software.16 *17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.24 *25 */26#include "nv04.h"27#include "fbmem.h"28 29#include <subdev/bios.h>30#include <subdev/bios/init.h>31#include <subdev/bios/pll.h>32#include <subdev/clk/pll.h>33#include <subdev/vga.h>34 35static void36nv04_devinit_meminit(struct nvkm_devinit *init)37{38 struct nvkm_subdev *subdev = &init->subdev;39 struct nvkm_device *device = subdev->device;40 u32 patt = 0xdeadbeef;41 struct io_mapping *fb;42 int i;43 44 /* Map the framebuffer aperture */45 fb = fbmem_init(device);46 if (!fb) {47 nvkm_error(subdev, "failed to map fb\n");48 return;49 }50 51 /* Sequencer and refresh off */52 nvkm_wrvgas(device, 0, 1, nvkm_rdvgas(device, 0, 1) | 0x20);53 nvkm_mask(device, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);54 55 nvkm_mask(device, NV04_PFB_BOOT_0, ~0,56 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |57 NV04_PFB_BOOT_0_RAM_WIDTH_128 |58 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);59 60 for (i = 0; i < 4; i++)61 fbmem_poke(fb, 4 * i, patt);62 63 fbmem_poke(fb, 0x400000, patt + 1);64 65 if (fbmem_peek(fb, 0) == patt + 1) {66 nvkm_mask(device, NV04_PFB_BOOT_0,67 NV04_PFB_BOOT_0_RAM_TYPE,68 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);69 nvkm_mask(device, NV04_PFB_DEBUG_0,70 NV04_PFB_DEBUG_0_REFRESH_OFF, 0);71 72 for (i = 0; i < 4; i++)73 fbmem_poke(fb, 4 * i, patt);74 75 if ((fbmem_peek(fb, 0xc) & 0xffff) != (patt & 0xffff))76 nvkm_mask(device, NV04_PFB_BOOT_0,77 NV04_PFB_BOOT_0_RAM_WIDTH_128 |78 NV04_PFB_BOOT_0_RAM_AMOUNT,79 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);80 } else81 if ((fbmem_peek(fb, 0xc) & 0xffff0000) != (patt & 0xffff0000)) {82 nvkm_mask(device, NV04_PFB_BOOT_0,83 NV04_PFB_BOOT_0_RAM_WIDTH_128 |84 NV04_PFB_BOOT_0_RAM_AMOUNT,85 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);86 } else87 if (fbmem_peek(fb, 0) != patt) {88 if (fbmem_readback(fb, 0x800000, patt))89 nvkm_mask(device, NV04_PFB_BOOT_0,90 NV04_PFB_BOOT_0_RAM_AMOUNT,91 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);92 else93 nvkm_mask(device, NV04_PFB_BOOT_0,94 NV04_PFB_BOOT_0_RAM_AMOUNT,95 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);96 97 nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,98 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);99 } else100 if (!fbmem_readback(fb, 0x800000, patt)) {101 nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,102 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);103 104 }105 106 /* Refresh on, sequencer on */107 nvkm_mask(device, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);108 nvkm_wrvgas(device, 0, 1, nvkm_rdvgas(device, 0, 1) & ~0x20);109 fbmem_fini(fb);110}111 112static int113powerctrl_1_shift(int chip_version, int reg)114{115 int shift = -4;116 117 if (chip_version < 0x17 || chip_version == 0x1a || chip_version == 0x20)118 return shift;119 120 switch (reg) {121 case 0x680520:122 shift += 4; fallthrough;123 case 0x680508:124 shift += 4; fallthrough;125 case 0x680504:126 shift += 4; fallthrough;127 case 0x680500:128 shift += 4;129 }130 131 /*132 * the shift for vpll regs is only used for nv3x chips with a single133 * stage pll134 */135 if (shift > 4 && (chip_version < 0x32 || chip_version == 0x35 ||136 chip_version == 0x36 || chip_version >= 0x40))137 shift = -4;138 139 return shift;140}141 142void143setPLL_single(struct nvkm_devinit *init, u32 reg,144 struct nvkm_pll_vals *pv)145{146 struct nvkm_device *device = init->subdev.device;147 int chip_version = device->bios->version.chip;148 uint32_t oldpll = nvkm_rd32(device, reg);149 int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff;150 uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1;151 uint32_t saved_powerctrl_1 = 0;152 int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg);153 154 if (oldpll == pll)155 return; /* already set */156 157 if (shift_powerctrl_1 >= 0) {158 saved_powerctrl_1 = nvkm_rd32(device, 0x001584);159 nvkm_wr32(device, 0x001584,160 (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |161 1 << shift_powerctrl_1);162 }163 164 if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1))165 /* upclock -- write new post divider first */166 nvkm_wr32(device, reg, pv->log2P << 16 | (oldpll & 0xffff));167 else168 /* downclock -- write new NM first */169 nvkm_wr32(device, reg, (oldpll & 0xffff0000) | pv->NM1);170 171 if ((chip_version < 0x17 || chip_version == 0x1a) &&172 chip_version != 0x11)173 /* wait a bit on older chips */174 msleep(64);175 nvkm_rd32(device, reg);176 177 /* then write the other half as well */178 nvkm_wr32(device, reg, pll);179 180 if (shift_powerctrl_1 >= 0)181 nvkm_wr32(device, 0x001584, saved_powerctrl_1);182}183 184static uint32_t185new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580)186{187 bool head_a = (reg1 == 0x680508);188 189 if (ss) /* single stage pll mode */190 ramdac580 |= head_a ? 0x00000100 : 0x10000000;191 else192 ramdac580 &= head_a ? 0xfffffeff : 0xefffffff;193 194 return ramdac580;195}196 197void198setPLL_double_highregs(struct nvkm_devinit *init, u32 reg1,199 struct nvkm_pll_vals *pv)200{201 struct nvkm_device *device = init->subdev.device;202 int chip_version = device->bios->version.chip;203 bool nv3035 = chip_version == 0x30 || chip_version == 0x35;204 uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70);205 uint32_t oldpll1 = nvkm_rd32(device, reg1);206 uint32_t oldpll2 = !nv3035 ? nvkm_rd32(device, reg2) : 0;207 uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1;208 uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2;209 uint32_t oldramdac580 = 0, ramdac580 = 0;210 bool single_stage = !pv->NM2 || pv->N2 == pv->M2; /* nv41+ only */211 uint32_t saved_powerctrl_1 = 0, savedc040 = 0;212 int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1);213 214 /* model specific additions to generic pll1 and pll2 set up above */215 if (nv3035) {216 pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 |217 (pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4;218 pll2 = 0;219 }220 if (chip_version > 0x40 && reg1 >= 0x680508) { /* !nv40 */221 oldramdac580 = nvkm_rd32(device, 0x680580);222 ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580);223 if (oldramdac580 != ramdac580)224 oldpll1 = ~0; /* force mismatch */225 if (single_stage)226 /* magic value used by nvidia in single stage mode */227 pll2 |= 0x011f;228 }229 if (chip_version > 0x70)230 /* magic bits set by the blob (but not the bios) on g71-73 */231 pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28;232 233 if (oldpll1 == pll1 && oldpll2 == pll2)234 return; /* already set */235 236 if (shift_powerctrl_1 >= 0) {237 saved_powerctrl_1 = nvkm_rd32(device, 0x001584);238 nvkm_wr32(device, 0x001584,239 (saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |240 1 << shift_powerctrl_1);241 }242 243 if (chip_version >= 0x40) {244 int shift_c040 = 14;245 246 switch (reg1) {247 case 0x680504:248 shift_c040 += 2; fallthrough;249 case 0x680500:250 shift_c040 += 2; fallthrough;251 case 0x680520:252 shift_c040 += 2; fallthrough;253 case 0x680508:254 shift_c040 += 2;255 }256 257 savedc040 = nvkm_rd32(device, 0xc040);258 if (shift_c040 != 14)259 nvkm_wr32(device, 0xc040, savedc040 & ~(3 << shift_c040));260 }261 262 if (oldramdac580 != ramdac580)263 nvkm_wr32(device, 0x680580, ramdac580);264 265 if (!nv3035)266 nvkm_wr32(device, reg2, pll2);267 nvkm_wr32(device, reg1, pll1);268 269 if (shift_powerctrl_1 >= 0)270 nvkm_wr32(device, 0x001584, saved_powerctrl_1);271 if (chip_version >= 0x40)272 nvkm_wr32(device, 0xc040, savedc040);273}274 275void276setPLL_double_lowregs(struct nvkm_devinit *init, u32 NMNMreg,277 struct nvkm_pll_vals *pv)278{279 /* When setting PLLs, there is a merry game of disabling and enabling280 * various bits of hardware during the process. This function is a281 * synthesis of six nv4x traces, nearly each card doing a subtly282 * different thing. With luck all the necessary bits for each card are283 * combined herein. Without luck it deviates from each card's formula284 * so as to not work on any :)285 */286 struct nvkm_device *device = init->subdev.device;287 uint32_t Preg = NMNMreg - 4;288 bool mpll = Preg == 0x4020;289 uint32_t oldPval = nvkm_rd32(device, Preg);290 uint32_t NMNM = pv->NM2 << 16 | pv->NM1;291 uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) |292 0xc << 28 | pv->log2P << 16;293 uint32_t saved4600 = 0;294 /* some cards have different maskc040s */295 uint32_t maskc040 = ~(3 << 14), savedc040;296 bool single_stage = !pv->NM2 || pv->N2 == pv->M2;297 298 if (nvkm_rd32(device, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval)299 return;300 301 if (Preg == 0x4000)302 maskc040 = ~0x333;303 if (Preg == 0x4058)304 maskc040 = ~(0xc << 24);305 306 if (mpll) {307 struct nvbios_pll info;308 uint8_t Pval2;309 310 if (nvbios_pll_parse(device->bios, Preg, &info))311 return;312 313 Pval2 = pv->log2P + info.bias_p;314 if (Pval2 > info.max_p)315 Pval2 = info.max_p;316 Pval |= 1 << 28 | Pval2 << 20;317 318 saved4600 = nvkm_rd32(device, 0x4600);319 nvkm_wr32(device, 0x4600, saved4600 | 8 << 28);320 }321 if (single_stage)322 Pval |= mpll ? 1 << 12 : 1 << 8;323 324 nvkm_wr32(device, Preg, oldPval | 1 << 28);325 nvkm_wr32(device, Preg, Pval & ~(4 << 28));326 if (mpll) {327 Pval |= 8 << 20;328 nvkm_wr32(device, 0x4020, Pval & ~(0xc << 28));329 nvkm_wr32(device, 0x4038, Pval & ~(0xc << 28));330 }331 332 savedc040 = nvkm_rd32(device, 0xc040);333 nvkm_wr32(device, 0xc040, savedc040 & maskc040);334 335 nvkm_wr32(device, NMNMreg, NMNM);336 if (NMNMreg == 0x4024)337 nvkm_wr32(device, 0x403c, NMNM);338 339 nvkm_wr32(device, Preg, Pval);340 if (mpll) {341 Pval &= ~(8 << 20);342 nvkm_wr32(device, 0x4020, Pval);343 nvkm_wr32(device, 0x4038, Pval);344 nvkm_wr32(device, 0x4600, saved4600);345 }346 347 nvkm_wr32(device, 0xc040, savedc040);348 349 if (mpll) {350 nvkm_wr32(device, 0x4020, Pval & ~(1 << 28));351 nvkm_wr32(device, 0x4038, Pval & ~(1 << 28));352 }353}354 355int356nv04_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)357{358 struct nvkm_subdev *subdev = &devinit->subdev;359 struct nvkm_bios *bios = subdev->device->bios;360 struct nvkm_pll_vals pv;361 struct nvbios_pll info;362 int cv = bios->version.chip;363 int N1, M1, N2, M2, P;364 int ret;365 366 ret = nvbios_pll_parse(bios, type > 0x405c ? type : type - 4, &info);367 if (ret)368 return ret;369 370 ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P);371 if (!ret)372 return -EINVAL;373 374 pv.refclk = info.refclk;375 pv.N1 = N1;376 pv.M1 = M1;377 pv.N2 = N2;378 pv.M2 = M2;379 pv.log2P = P;380 381 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||382 cv >= 0x40) {383 if (type > 0x405c)384 setPLL_double_highregs(devinit, type, &pv);385 else386 setPLL_double_lowregs(devinit, type, &pv);387 } else388 setPLL_single(devinit, type, &pv);389 390 return 0;391}392 393int394nv04_devinit_post(struct nvkm_devinit *init, bool execute)395{396 return nvbios_post(&init->subdev, execute);397}398 399void400nv04_devinit_preinit(struct nvkm_devinit *base)401{402 struct nv04_devinit *init = nv04_devinit(base);403 struct nvkm_subdev *subdev = &init->base.subdev;404 struct nvkm_device *device = subdev->device;405 406 /* make i2c busses accessible */407 nvkm_mask(device, 0x000200, 0x00000001, 0x00000001);408 409 /* unslave crtcs */410 if (init->owner < 0)411 init->owner = nvkm_rdvgaowner(device);412 nvkm_wrvgaowner(device, 0);413 414 if (!init->base.post) {415 u32 htotal = nvkm_rdvgac(device, 0, 0x06);416 htotal |= (nvkm_rdvgac(device, 0, 0x07) & 0x01) << 8;417 htotal |= (nvkm_rdvgac(device, 0, 0x07) & 0x20) << 4;418 htotal |= (nvkm_rdvgac(device, 0, 0x25) & 0x01) << 10;419 htotal |= (nvkm_rdvgac(device, 0, 0x41) & 0x01) << 11;420 if (!htotal) {421 nvkm_debug(subdev, "adaptor not initialised\n");422 init->base.post = true;423 }424 }425}426 427void *428nv04_devinit_dtor(struct nvkm_devinit *base)429{430 struct nv04_devinit *init = nv04_devinit(base);431 /* restore vga owner saved at first init */432 nvkm_wrvgaowner(init->base.subdev.device, init->owner);433 return init;434}435 436int437nv04_devinit_new_(const struct nvkm_devinit_func *func, struct nvkm_device *device,438 enum nvkm_subdev_type type, int inst, struct nvkm_devinit **pinit)439{440 struct nv04_devinit *init;441 442 if (!(init = kzalloc(sizeof(*init), GFP_KERNEL)))443 return -ENOMEM;444 *pinit = &init->base;445 446 nvkm_devinit_ctor(func, device, type, inst, &init->base);447 init->owner = -1;448 return 0;449}450 451static const struct nvkm_devinit_func452nv04_devinit = {453 .dtor = nv04_devinit_dtor,454 .preinit = nv04_devinit_preinit,455 .post = nv04_devinit_post,456 .meminit = nv04_devinit_meminit,457 .pll_set = nv04_devinit_pll_set,458};459 460int461nv04_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,462 struct nvkm_devinit **pinit)463{464 return nv04_devinit_new_(&nv04_devinit, device, type, inst, pinit);465}466