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1/*2 * Copyright 2013 Red Hat Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: Ben Skeggs <bskeggs@redhat.com>23 * Roy Spliet <rspliet@eclipso.eu>24 */25#include "ram.h"26 27struct ramxlat {28 int id;29 u8 enc;30};31 32static inline int33ramxlat(const struct ramxlat *xlat, int id)34{35 while (xlat->id >= 0) {36 if (xlat->id == id)37 return xlat->enc;38 xlat++;39 }40 return -EINVAL;41}42 43static const struct ramxlat44ramgddr3_cl_lo[] = {45 { 5, 5 }, { 7, 7 }, { 8, 0 }, { 9, 1 }, { 10, 2 }, { 11, 3 }, { 12, 8 },46 /* the below are mentioned in some, but not all, gddr3 docs */47 { 13, 9 }, { 14, 6 },48 /* XXX: Per Samsung docs, are these used? They overlap with Qimonda */49 /* { 4, 4 }, { 5, 5 }, { 6, 6 }, { 12, 8 }, { 13, 9 }, { 14, 10 },50 * { 15, 11 }, */51 { -1 }52};53 54static const struct ramxlat55ramgddr3_cl_hi[] = {56 { 10, 2 }, { 11, 3 }, { 12, 4 }, { 13, 5 }, { 14, 6 }, { 15, 7 },57 { 16, 0 }, { 17, 1 },58 { -1 }59};60 61static const struct ramxlat62ramgddr3_wr_lo[] = {63 { 5, 2 }, { 7, 4 }, { 8, 5 }, { 9, 6 }, { 10, 7 },64 { 11, 0 }, { 13 , 1 },65 /* the below are mentioned in some, but not all, gddr3 docs */66 { 4, 0 }, { 6, 3 }, { 12, 1 },67 { -1 }68};69 70int71nvkm_gddr3_calc(struct nvkm_ram *ram)72{73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi;74 75 switch (ram->next->bios.timing_ver) {76 case 0x10:77 CWL = ram->next->bios.timing_10_CWL;78 CL = ram->next->bios.timing_10_CL;79 WR = ram->next->bios.timing_10_WR;80 DLL = !ram->next->bios.ramcfg_DLLoff;81 ODT = ram->next->bios.timing_10_ODT;82 RON = ram->next->bios.ramcfg_RON;83 break;84 case 0x20:85 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;86 CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0;87 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;88 /* XXX: Get these values from the VBIOS instead */89 DLL = !(ram->mr[1] & 0x1);90 RON = !((ram->mr[1] & 0x300) >> 8);91 break;92 default:93 return -ENOSYS;94 }95 96 if (ram->next->bios.timing_ver == 0x20 ||97 ram->next->bios.ramcfg_timing == 0xff) {98 ODT = (ram->mr[1] & 0xc) >> 2;99 }100 101 hi = ram->mr[2] & 0x1;102 CL = ramxlat(hi ? ramgddr3_cl_hi : ramgddr3_cl_lo, CL);103 WR = ramxlat(ramgddr3_wr_lo, WR);104 if (CL < 0 || CWL < 1 || CWL > 7 || WR < 0)105 return -EINVAL;106 107 ram->mr[0] &= ~0xf74;108 ram->mr[0] |= (CWL & 0x07) << 9;109 ram->mr[0] |= (CL & 0x07) << 4;110 ram->mr[0] |= (CL & 0x08) >> 1;111 112 ram->mr[1] &= ~0x3fc;113 ram->mr[1] |= (ODT & 0x03) << 2;114 ram->mr[1] |= (RON & 0x03) << 8;115 ram->mr[1] |= (WR & 0x03) << 4;116 ram->mr[1] |= (WR & 0x04) << 5;117 ram->mr[1] |= !DLL << 6;118 return 0;119}120