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1/*2 * Copyright 2013 Red Hat Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: Ben Skeggs23 */24#define gf100_ram(p) container_of((p), struct gf100_ram, base)25#include "ram.h"26#include "ramfuc.h"27 28#include <core/option.h>29#include <subdev/bios.h>30#include <subdev/bios/pll.h>31#include <subdev/bios/rammap.h>32#include <subdev/bios/timing.h>33#include <subdev/clk.h>34#include <subdev/clk/pll.h>35 36struct gf100_ramfuc {37 struct ramfuc base;38 39 struct ramfuc_reg r_0x10fe20;40 struct ramfuc_reg r_0x10fe24;41 struct ramfuc_reg r_0x137320;42 struct ramfuc_reg r_0x137330;43 44 struct ramfuc_reg r_0x132000;45 struct ramfuc_reg r_0x132004;46 struct ramfuc_reg r_0x132100;47 48 struct ramfuc_reg r_0x137390;49 50 struct ramfuc_reg r_0x10f290;51 struct ramfuc_reg r_0x10f294;52 struct ramfuc_reg r_0x10f298;53 struct ramfuc_reg r_0x10f29c;54 struct ramfuc_reg r_0x10f2a0;55 56 struct ramfuc_reg r_0x10f300;57 struct ramfuc_reg r_0x10f338;58 struct ramfuc_reg r_0x10f340;59 struct ramfuc_reg r_0x10f344;60 struct ramfuc_reg r_0x10f348;61 62 struct ramfuc_reg r_0x10f910;63 struct ramfuc_reg r_0x10f914;64 65 struct ramfuc_reg r_0x100b0c;66 struct ramfuc_reg r_0x10f050;67 struct ramfuc_reg r_0x10f090;68 struct ramfuc_reg r_0x10f200;69 struct ramfuc_reg r_0x10f210;70 struct ramfuc_reg r_0x10f310;71 struct ramfuc_reg r_0x10f314;72 struct ramfuc_reg r_0x10f610;73 struct ramfuc_reg r_0x10f614;74 struct ramfuc_reg r_0x10f800;75 struct ramfuc_reg r_0x10f808;76 struct ramfuc_reg r_0x10f824;77 struct ramfuc_reg r_0x10f830;78 struct ramfuc_reg r_0x10f988;79 struct ramfuc_reg r_0x10f98c;80 struct ramfuc_reg r_0x10f990;81 struct ramfuc_reg r_0x10f998;82 struct ramfuc_reg r_0x10f9b0;83 struct ramfuc_reg r_0x10f9b4;84 struct ramfuc_reg r_0x10fb04;85 struct ramfuc_reg r_0x10fb08;86 struct ramfuc_reg r_0x137300;87 struct ramfuc_reg r_0x137310;88 struct ramfuc_reg r_0x137360;89 struct ramfuc_reg r_0x1373ec;90 struct ramfuc_reg r_0x1373f0;91 struct ramfuc_reg r_0x1373f8;92 93 struct ramfuc_reg r_0x61c140;94 struct ramfuc_reg r_0x611200;95 96 struct ramfuc_reg r_0x13d8f4;97};98 99struct gf100_ram {100 struct nvkm_ram base;101 struct gf100_ramfuc fuc;102 struct nvbios_pll refpll;103 struct nvbios_pll mempll;104};105 106static void107gf100_ram_train(struct gf100_ramfuc *fuc, u32 magic)108{109 struct gf100_ram *ram = container_of(fuc, typeof(*ram), fuc);110 struct nvkm_fb *fb = ram->base.fb;111 struct nvkm_device *device = fb->subdev.device;112 u32 part = nvkm_rd32(device, 0x022438), i;113 u32 mask = nvkm_rd32(device, 0x022554);114 u32 addr = 0x110974;115 116 ram_wr32(fuc, 0x10f910, magic);117 ram_wr32(fuc, 0x10f914, magic);118 119 for (i = 0; (magic & 0x80000000) && i < part; addr += 0x1000, i++) {120 if (mask & (1 << i))121 continue;122 ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000);123 }124}125 126int127gf100_ram_calc(struct nvkm_ram *base, u32 freq)128{129 struct gf100_ram *ram = gf100_ram(base);130 struct gf100_ramfuc *fuc = &ram->fuc;131 struct nvkm_subdev *subdev = &ram->base.fb->subdev;132 struct nvkm_device *device = subdev->device;133 struct nvkm_clk *clk = device->clk;134 struct nvkm_bios *bios = device->bios;135 struct nvbios_ramcfg cfg;136 u8 ver, cnt, len, strap;137 struct {138 u32 data;139 u8 size;140 } rammap, ramcfg, timing;141 int ref, div, out;142 int from, mode;143 int N1, M1, P;144 int ret;145 146 /* lookup memory config data relevant to the target frequency */147 rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size,148 &cnt, &ramcfg.size, &cfg);149 if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) {150 nvkm_error(subdev, "invalid/missing rammap entry\n");151 return -EINVAL;152 }153 154 /* locate specific data set for the attached memory */155 strap = nvbios_ramcfg_index(subdev);156 if (strap >= cnt) {157 nvkm_error(subdev, "invalid ramcfg strap\n");158 return -EINVAL;159 }160 161 ramcfg.data = rammap.data + rammap.size + (strap * ramcfg.size);162 if (!ramcfg.data || ver != 0x10 || ramcfg.size < 0x0e) {163 nvkm_error(subdev, "invalid/missing ramcfg entry\n");164 return -EINVAL;165 }166 167 /* lookup memory timings, if bios says they're present */168 strap = nvbios_rd08(bios, ramcfg.data + 0x01);169 if (strap != 0xff) {170 timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size,171 &cnt, &len);172 if (!timing.data || ver != 0x10 || timing.size < 0x19) {173 nvkm_error(subdev, "invalid/missing timing entry\n");174 return -EINVAL;175 }176 } else {177 timing.data = 0;178 }179 180 ret = ram_init(fuc, ram->base.fb);181 if (ret)182 return ret;183 184 /* determine current mclk configuration */185 from = !!(ram_rd32(fuc, 0x1373f0) & 0x00000002); /*XXX: ok? */186 187 /* determine target mclk configuration */188 if (!(ram_rd32(fuc, 0x137300) & 0x00000100))189 ref = nvkm_clk_read(clk, nv_clk_src_sppll0);190 else191 ref = nvkm_clk_read(clk, nv_clk_src_sppll1);192 div = max(min((ref * 2) / freq, (u32)65), (u32)2) - 2;193 out = (ref * 2) / (div + 2);194 mode = freq != out;195 196 ram_mask(fuc, 0x137360, 0x00000002, 0x00000000);197 198 if ((ram_rd32(fuc, 0x132000) & 0x00000002) || 0 /*XXX*/) {199 ram_nuke(fuc, 0x132000);200 ram_mask(fuc, 0x132000, 0x00000002, 0x00000002);201 ram_mask(fuc, 0x132000, 0x00000002, 0x00000000);202 }203 204 if (mode == 1) {205 ram_nuke(fuc, 0x10fe20);206 ram_mask(fuc, 0x10fe20, 0x00000002, 0x00000002);207 ram_mask(fuc, 0x10fe20, 0x00000002, 0x00000000);208 }209 210// 0x00020034 // 0x0000000a211 ram_wr32(fuc, 0x132100, 0x00000001);212 213 if (mode == 1 && from == 0) {214 /* calculate refpll */215 ret = gt215_pll_calc(subdev, &ram->refpll, ram->mempll.refclk,216 &N1, NULL, &M1, &P);217 if (ret <= 0) {218 nvkm_error(subdev, "unable to calc refpll\n");219 return ret ? ret : -ERANGE;220 }221 222 ram_wr32(fuc, 0x10fe20, 0x20010000);223 ram_wr32(fuc, 0x137320, 0x00000003);224 ram_wr32(fuc, 0x137330, 0x81200006);225 ram_wr32(fuc, 0x10fe24, (P << 16) | (N1 << 8) | M1);226 ram_wr32(fuc, 0x10fe20, 0x20010001);227 ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);228 229 /* calculate mempll */230 ret = gt215_pll_calc(subdev, &ram->mempll, freq,231 &N1, NULL, &M1, &P);232 if (ret <= 0) {233 nvkm_error(subdev, "unable to calc refpll\n");234 return ret ? ret : -ERANGE;235 }236 237 ram_wr32(fuc, 0x10fe20, 0x20010005);238 ram_wr32(fuc, 0x132004, (P << 16) | (N1 << 8) | M1);239 ram_wr32(fuc, 0x132000, 0x18010101);240 ram_wait(fuc, 0x137390, 0x00000002, 0x00000002, 64000);241 } else242 if (mode == 0) {243 ram_wr32(fuc, 0x137300, 0x00000003);244 }245 246 if (from == 0) {247 ram_nuke(fuc, 0x10fb04);248 ram_mask(fuc, 0x10fb04, 0x0000ffff, 0x00000000);249 ram_nuke(fuc, 0x10fb08);250 ram_mask(fuc, 0x10fb08, 0x0000ffff, 0x00000000);251 ram_wr32(fuc, 0x10f988, 0x2004ff00);252 ram_wr32(fuc, 0x10f98c, 0x003fc040);253 ram_wr32(fuc, 0x10f990, 0x20012001);254 ram_wr32(fuc, 0x10f998, 0x00011a00);255 ram_wr32(fuc, 0x13d8f4, 0x00000000);256 } else {257 ram_wr32(fuc, 0x10f988, 0x20010000);258 ram_wr32(fuc, 0x10f98c, 0x00000000);259 ram_wr32(fuc, 0x10f990, 0x20012001);260 ram_wr32(fuc, 0x10f998, 0x00010a00);261 }262 263 if (from == 0) {264// 0x00020039 // 0x000000ba265 }266 267// 0x0002003a // 0x00000002268 ram_wr32(fuc, 0x100b0c, 0x00080012);269// 0x00030014 // 0x00000000 // 0x02b5f070270// 0x00030014 // 0x00010000 // 0x02b5f070271 ram_wr32(fuc, 0x611200, 0x00003300);272// 0x00020034 // 0x0000000a273// 0x00030020 // 0x00000001 // 0x00000000274 275 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);276 ram_wr32(fuc, 0x10f210, 0x00000000);277 ram_nsec(fuc, 1000);278 if (mode == 0)279 gf100_ram_train(fuc, 0x000c1001);280 ram_wr32(fuc, 0x10f310, 0x00000001);281 ram_nsec(fuc, 1000);282 ram_wr32(fuc, 0x10f090, 0x00000061);283 ram_wr32(fuc, 0x10f090, 0xc000007f);284 ram_nsec(fuc, 1000);285 286 if (from == 0) {287 ram_wr32(fuc, 0x10f824, 0x00007fd4);288 } else {289 ram_wr32(fuc, 0x1373ec, 0x00020404);290 }291 292 if (mode == 0) {293 ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000);294 ram_mask(fuc, 0x10f200, 0x00008000, 0x00008000);295 ram_wr32(fuc, 0x10f830, 0x41500010);296 ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);297 ram_mask(fuc, 0x132100, 0x00000100, 0x00000100);298 ram_wr32(fuc, 0x10f050, 0xff000090);299 ram_wr32(fuc, 0x1373ec, 0x00020f0f);300 ram_wr32(fuc, 0x1373f0, 0x00000003);301 ram_wr32(fuc, 0x137310, 0x81201616);302 ram_wr32(fuc, 0x132100, 0x00000001);303// 0x00020039 // 0x000000ba304 ram_wr32(fuc, 0x10f830, 0x00300017);305 ram_wr32(fuc, 0x1373f0, 0x00000001);306 ram_wr32(fuc, 0x10f824, 0x00007e77);307 ram_wr32(fuc, 0x132000, 0x18030001);308 ram_wr32(fuc, 0x10f090, 0x4000007e);309 ram_nsec(fuc, 2000);310 ram_wr32(fuc, 0x10f314, 0x00000001);311 ram_wr32(fuc, 0x10f210, 0x80000000);312 ram_wr32(fuc, 0x10f338, 0x00300220);313 ram_wr32(fuc, 0x10f300, 0x0000011d);314 ram_nsec(fuc, 1000);315 ram_wr32(fuc, 0x10f290, 0x02060505);316 ram_wr32(fuc, 0x10f294, 0x34208288);317 ram_wr32(fuc, 0x10f298, 0x44050411);318 ram_wr32(fuc, 0x10f29c, 0x0000114c);319 ram_wr32(fuc, 0x10f2a0, 0x42e10069);320 ram_wr32(fuc, 0x10f614, 0x40044f77);321 ram_wr32(fuc, 0x10f610, 0x40044f77);322 ram_wr32(fuc, 0x10f344, 0x00600009);323 ram_nsec(fuc, 1000);324 ram_wr32(fuc, 0x10f348, 0x00700008);325 ram_wr32(fuc, 0x61c140, 0x19240000);326 ram_wr32(fuc, 0x10f830, 0x00300017);327 gf100_ram_train(fuc, 0x80021001);328 gf100_ram_train(fuc, 0x80081001);329 ram_wr32(fuc, 0x10f340, 0x00500004);330 ram_nsec(fuc, 1000);331 ram_wr32(fuc, 0x10f830, 0x01300017);332 ram_wr32(fuc, 0x10f830, 0x00300017);333// 0x00030020 // 0x00000000 // 0x00000000334// 0x00020034 // 0x0000000b335 ram_wr32(fuc, 0x100b0c, 0x00080028);336 ram_wr32(fuc, 0x611200, 0x00003330);337 } else {338 ram_wr32(fuc, 0x10f800, 0x00001800);339 ram_wr32(fuc, 0x13d8f4, 0x00000000);340 ram_wr32(fuc, 0x1373ec, 0x00020404);341 ram_wr32(fuc, 0x1373f0, 0x00000003);342 ram_wr32(fuc, 0x10f830, 0x40700010);343 ram_wr32(fuc, 0x10f830, 0x40500010);344 ram_wr32(fuc, 0x13d8f4, 0x00000000);345 ram_wr32(fuc, 0x1373f8, 0x00000000);346 ram_wr32(fuc, 0x132100, 0x00000101);347 ram_wr32(fuc, 0x137310, 0x89201616);348 ram_wr32(fuc, 0x10f050, 0xff000090);349 ram_wr32(fuc, 0x1373ec, 0x00030404);350 ram_wr32(fuc, 0x1373f0, 0x00000002);351 // 0x00020039 // 0x00000011352 ram_wr32(fuc, 0x132100, 0x00000001);353 ram_wr32(fuc, 0x1373f8, 0x00002000);354 ram_nsec(fuc, 2000);355 ram_wr32(fuc, 0x10f808, 0x7aaa0050);356 ram_wr32(fuc, 0x10f830, 0x00500010);357 ram_wr32(fuc, 0x10f200, 0x00ce1000);358 ram_wr32(fuc, 0x10f090, 0x4000007e);359 ram_nsec(fuc, 2000);360 ram_wr32(fuc, 0x10f314, 0x00000001);361 ram_wr32(fuc, 0x10f210, 0x80000000);362 ram_wr32(fuc, 0x10f338, 0x00300200);363 ram_wr32(fuc, 0x10f300, 0x0000084d);364 ram_nsec(fuc, 1000);365 ram_wr32(fuc, 0x10f290, 0x0b343825);366 ram_wr32(fuc, 0x10f294, 0x3483028e);367 ram_wr32(fuc, 0x10f298, 0x440c0600);368 ram_wr32(fuc, 0x10f29c, 0x0000214c);369 ram_wr32(fuc, 0x10f2a0, 0x42e20069);370 ram_wr32(fuc, 0x10f200, 0x00ce0000);371 ram_wr32(fuc, 0x10f614, 0x60044e77);372 ram_wr32(fuc, 0x10f610, 0x60044e77);373 ram_wr32(fuc, 0x10f340, 0x00500000);374 ram_nsec(fuc, 1000);375 ram_wr32(fuc, 0x10f344, 0x00600228);376 ram_nsec(fuc, 1000);377 ram_wr32(fuc, 0x10f348, 0x00700000);378 ram_wr32(fuc, 0x13d8f4, 0x00000000);379 ram_wr32(fuc, 0x61c140, 0x09a40000);380 381 gf100_ram_train(fuc, 0x800e1008);382 383 ram_nsec(fuc, 1000);384 ram_wr32(fuc, 0x10f800, 0x00001804);385 // 0x00030020 // 0x00000000 // 0x00000000386 // 0x00020034 // 0x0000000b387 ram_wr32(fuc, 0x13d8f4, 0x00000000);388 ram_wr32(fuc, 0x100b0c, 0x00080028);389 ram_wr32(fuc, 0x611200, 0x00003330);390 ram_nsec(fuc, 100000);391 ram_wr32(fuc, 0x10f9b0, 0x05313f41);392 ram_wr32(fuc, 0x10f9b4, 0x00002f50);393 394 gf100_ram_train(fuc, 0x010c1001);395 }396 397 ram_mask(fuc, 0x10f200, 0x00000800, 0x00000800);398// 0x00020016 // 0x00000000399 400 if (mode == 0)401 ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);402 403 return 0;404}405 406int407gf100_ram_prog(struct nvkm_ram *base)408{409 struct gf100_ram *ram = gf100_ram(base);410 struct nvkm_device *device = ram->base.fb->subdev.device;411 ram_exec(&ram->fuc, nvkm_boolopt(device->cfgopt, "NvMemExec", true));412 return 0;413}414 415void416gf100_ram_tidy(struct nvkm_ram *base)417{418 struct gf100_ram *ram = gf100_ram(base);419 ram_exec(&ram->fuc, false);420}421 422int423gf100_ram_init(struct nvkm_ram *base)424{425 static const u8 train0[] = {426 0x00, 0xff, 0x55, 0xaa, 0x33, 0xcc,427 0x00, 0xff, 0xff, 0x00, 0xff, 0x00,428 };429 static const u32 train1[] = {430 0x00000000, 0xffffffff,431 0x55555555, 0xaaaaaaaa,432 0x33333333, 0xcccccccc,433 0xf0f0f0f0, 0x0f0f0f0f,434 0x00ff00ff, 0xff00ff00,435 0x0000ffff, 0xffff0000,436 };437 struct gf100_ram *ram = gf100_ram(base);438 struct nvkm_device *device = ram->base.fb->subdev.device;439 int i;440 441 switch (ram->base.type) {442 case NVKM_RAM_TYPE_GDDR5:443 break;444 default:445 return 0;446 }447 448 /* prepare for ddr link training, and load training patterns */449 for (i = 0; i < 0x30; i++) {450 nvkm_wr32(device, 0x10f968, 0x00000000 | (i << 8));451 nvkm_wr32(device, 0x10f96c, 0x00000000 | (i << 8));452 nvkm_wr32(device, 0x10f920, 0x00000100 | train0[i % 12]);453 nvkm_wr32(device, 0x10f924, 0x00000100 | train0[i % 12]);454 nvkm_wr32(device, 0x10f918, train1[i % 12]);455 nvkm_wr32(device, 0x10f91c, train1[i % 12]);456 nvkm_wr32(device, 0x10f920, 0x00000000 | train0[i % 12]);457 nvkm_wr32(device, 0x10f924, 0x00000000 | train0[i % 12]);458 nvkm_wr32(device, 0x10f918, train1[i % 12]);459 nvkm_wr32(device, 0x10f91c, train1[i % 12]);460 }461 462 return 0;463}464 465u32466gf100_ram_probe_fbpa_amount(struct nvkm_device *device, int fbpa)467{468 return nvkm_rd32(device, 0x11020c + (fbpa * 0x1000));469}470 471u32472gf100_ram_probe_fbp_amount(const struct nvkm_ram_func *func, u32 fbpao,473 struct nvkm_device *device, int fbp, int *pltcs)474{475 if (!(fbpao & BIT(fbp))) {476 *pltcs = 1;477 return func->probe_fbpa_amount(device, fbp);478 }479 return 0;480}481 482u32483gf100_ram_probe_fbp(const struct nvkm_ram_func *func,484 struct nvkm_device *device, int fbp, int *pltcs)485{486 u32 fbpao = nvkm_rd32(device, 0x022554);487 return func->probe_fbp_amount(func, fbpao, device, fbp, pltcs);488}489 490int491gf100_ram_ctor(const struct nvkm_ram_func *func, struct nvkm_fb *fb,492 struct nvkm_ram *ram)493{494 struct nvkm_subdev *subdev = &fb->subdev;495 struct nvkm_device *device = subdev->device;496 struct nvkm_bios *bios = device->bios;497 const u32 rsvd_head = ( 256 * 1024); /* vga memory */498 const u32 rsvd_tail = (1024 * 1024); /* vbios etc */499 enum nvkm_ram_type type = nvkm_fb_bios_memtype(bios);500 u32 fbps = nvkm_rd32(device, 0x022438);501 u64 total = 0, lcomm = ~0, lower, ubase, usize;502 int ret, fbp, ltcs, ltcn = 0;503 504 nvkm_debug(subdev, "%d FBP(s)\n", fbps);505 for (fbp = 0; fbp < fbps; fbp++) {506 u32 size = func->probe_fbp(func, device, fbp, <cs);507 if (size) {508 nvkm_debug(subdev, "FBP %d: %4d MiB, %d LTC(s)\n",509 fbp, size, ltcs);510 lcomm = min(lcomm, (u64)(size / ltcs) << 20);511 total += (u64) size << 20;512 ltcn += ltcs;513 } else {514 nvkm_debug(subdev, "FBP %d: disabled\n", fbp);515 }516 }517 518 lower = lcomm * ltcn;519 ubase = lcomm + func->upper;520 usize = total - lower;521 522 nvkm_debug(subdev, "Lower: %4lld MiB @ %010llx\n", lower >> 20, 0ULL);523 nvkm_debug(subdev, "Upper: %4lld MiB @ %010llx\n", usize >> 20, ubase);524 nvkm_debug(subdev, "Total: %4lld MiB\n", total >> 20);525 526 ret = nvkm_ram_ctor(func, fb, type, total, ram);527 if (ret)528 return ret;529 530 nvkm_mm_fini(&ram->vram);531 532 /* Some GPUs are in what's known as a "mixed memory" configuration.533 *534 * This is either where some FBPs have more memory than the others,535 * or where LTCs have been disabled on a FBP.536 */537 if (lower != total) {538 /* The common memory amount is addressed normally. */539 ret = nvkm_mm_init(&ram->vram, NVKM_RAM_MM_NORMAL,540 rsvd_head >> NVKM_RAM_MM_SHIFT,541 (lower - rsvd_head) >> NVKM_RAM_MM_SHIFT, 1);542 if (ret)543 return ret;544 545 /* And the rest is much higher in the physical address546 * space, and may not be usable for certain operations.547 */548 ret = nvkm_mm_init(&ram->vram, NVKM_RAM_MM_MIXED,549 ubase >> NVKM_RAM_MM_SHIFT,550 (usize - rsvd_tail) >> NVKM_RAM_MM_SHIFT, 1);551 if (ret)552 return ret;553 } else {554 /* GPUs without mixed-memory are a lot nicer... */555 ret = nvkm_mm_init(&ram->vram, NVKM_RAM_MM_NORMAL,556 rsvd_head >> NVKM_RAM_MM_SHIFT,557 (total - rsvd_head - rsvd_tail) >>558 NVKM_RAM_MM_SHIFT, 1);559 if (ret)560 return ret;561 }562 563 return 0;564}565 566int567gf100_ram_new_(const struct nvkm_ram_func *func,568 struct nvkm_fb *fb, struct nvkm_ram **pram)569{570 struct nvkm_subdev *subdev = &fb->subdev;571 struct nvkm_bios *bios = subdev->device->bios;572 struct gf100_ram *ram;573 int ret;574 575 if (!(ram = kzalloc(sizeof(*ram), GFP_KERNEL)))576 return -ENOMEM;577 *pram = &ram->base;578 579 ret = gf100_ram_ctor(func, fb, &ram->base);580 if (ret)581 return ret;582 583 ret = nvbios_pll_parse(bios, 0x0c, &ram->refpll);584 if (ret) {585 nvkm_error(subdev, "mclk refpll data not found\n");586 return ret;587 }588 589 ret = nvbios_pll_parse(bios, 0x04, &ram->mempll);590 if (ret) {591 nvkm_error(subdev, "mclk pll data not found\n");592 return ret;593 }594 595 ram->fuc.r_0x10fe20 = ramfuc_reg(0x10fe20);596 ram->fuc.r_0x10fe24 = ramfuc_reg(0x10fe24);597 ram->fuc.r_0x137320 = ramfuc_reg(0x137320);598 ram->fuc.r_0x137330 = ramfuc_reg(0x137330);599 600 ram->fuc.r_0x132000 = ramfuc_reg(0x132000);601 ram->fuc.r_0x132004 = ramfuc_reg(0x132004);602 ram->fuc.r_0x132100 = ramfuc_reg(0x132100);603 604 ram->fuc.r_0x137390 = ramfuc_reg(0x137390);605 606 ram->fuc.r_0x10f290 = ramfuc_reg(0x10f290);607 ram->fuc.r_0x10f294 = ramfuc_reg(0x10f294);608 ram->fuc.r_0x10f298 = ramfuc_reg(0x10f298);609 ram->fuc.r_0x10f29c = ramfuc_reg(0x10f29c);610 ram->fuc.r_0x10f2a0 = ramfuc_reg(0x10f2a0);611 612 ram->fuc.r_0x10f300 = ramfuc_reg(0x10f300);613 ram->fuc.r_0x10f338 = ramfuc_reg(0x10f338);614 ram->fuc.r_0x10f340 = ramfuc_reg(0x10f340);615 ram->fuc.r_0x10f344 = ramfuc_reg(0x10f344);616 ram->fuc.r_0x10f348 = ramfuc_reg(0x10f348);617 618 ram->fuc.r_0x10f910 = ramfuc_reg(0x10f910);619 ram->fuc.r_0x10f914 = ramfuc_reg(0x10f914);620 621 ram->fuc.r_0x100b0c = ramfuc_reg(0x100b0c);622 ram->fuc.r_0x10f050 = ramfuc_reg(0x10f050);623 ram->fuc.r_0x10f090 = ramfuc_reg(0x10f090);624 ram->fuc.r_0x10f200 = ramfuc_reg(0x10f200);625 ram->fuc.r_0x10f210 = ramfuc_reg(0x10f210);626 ram->fuc.r_0x10f310 = ramfuc_reg(0x10f310);627 ram->fuc.r_0x10f314 = ramfuc_reg(0x10f314);628 ram->fuc.r_0x10f610 = ramfuc_reg(0x10f610);629 ram->fuc.r_0x10f614 = ramfuc_reg(0x10f614);630 ram->fuc.r_0x10f800 = ramfuc_reg(0x10f800);631 ram->fuc.r_0x10f808 = ramfuc_reg(0x10f808);632 ram->fuc.r_0x10f824 = ramfuc_reg(0x10f824);633 ram->fuc.r_0x10f830 = ramfuc_reg(0x10f830);634 ram->fuc.r_0x10f988 = ramfuc_reg(0x10f988);635 ram->fuc.r_0x10f98c = ramfuc_reg(0x10f98c);636 ram->fuc.r_0x10f990 = ramfuc_reg(0x10f990);637 ram->fuc.r_0x10f998 = ramfuc_reg(0x10f998);638 ram->fuc.r_0x10f9b0 = ramfuc_reg(0x10f9b0);639 ram->fuc.r_0x10f9b4 = ramfuc_reg(0x10f9b4);640 ram->fuc.r_0x10fb04 = ramfuc_reg(0x10fb04);641 ram->fuc.r_0x10fb08 = ramfuc_reg(0x10fb08);642 ram->fuc.r_0x137310 = ramfuc_reg(0x137300);643 ram->fuc.r_0x137310 = ramfuc_reg(0x137310);644 ram->fuc.r_0x137360 = ramfuc_reg(0x137360);645 ram->fuc.r_0x1373ec = ramfuc_reg(0x1373ec);646 ram->fuc.r_0x1373f0 = ramfuc_reg(0x1373f0);647 ram->fuc.r_0x1373f8 = ramfuc_reg(0x1373f8);648 649 ram->fuc.r_0x61c140 = ramfuc_reg(0x61c140);650 ram->fuc.r_0x611200 = ramfuc_reg(0x611200);651 652 ram->fuc.r_0x13d8f4 = ramfuc_reg(0x13d8f4);653 return 0;654}655 656static const struct nvkm_ram_func657gf100_ram = {658 .upper = 0x0200000000ULL,659 .probe_fbp = gf100_ram_probe_fbp,660 .probe_fbp_amount = gf100_ram_probe_fbp_amount,661 .probe_fbpa_amount = gf100_ram_probe_fbpa_amount,662 .init = gf100_ram_init,663 .calc = gf100_ram_calc,664 .prog = gf100_ram_prog,665 .tidy = gf100_ram_tidy,666};667 668int669gf100_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram)670{671 return gf100_ram_new_(&gf100_ram, fb, pram);672}673