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1/*2 * Copyright 2013 Red Hat Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: Ben Skeggs <bskeggs@redhat.com>23 * Roy Spliet <rspliet@eclipso.eu>24 */25#include "priv.h"26#include "ram.h"27 28struct ramxlat {29 int id;30 u8 enc;31};32 33static inline int34ramxlat(const struct ramxlat *xlat, int id)35{36 while (xlat->id >= 0) {37 if (xlat->id == id)38 return xlat->enc;39 xlat++;40 }41 return -EINVAL;42}43 44static const struct ramxlat45ramddr3_cl[] = {46 { 5, 2 }, { 6, 4 }, { 7, 6 }, { 8, 8 }, { 9, 10 }, { 10, 12 },47 { 11, 14 },48 /* the below are mentioned in some, but not all, ddr3 docs */49 { 12, 1 }, { 13, 3 }, { 14, 5 },50 { -1 }51};52 53static const struct ramxlat54ramddr3_wr[] = {55 { 5, 1 }, { 6, 2 }, { 7, 3 }, { 8, 4 }, { 10, 5 }, { 12, 6 },56 /* the below are mentioned in some, but not all, ddr3 docs */57 { 14, 7 }, { 15, 7 }, { 16, 0 },58 { -1 }59};60 61static const struct ramxlat62ramddr3_cwl[] = {63 { 5, 0 }, { 6, 1 }, { 7, 2 }, { 8, 3 },64 /* the below are mentioned in some, but not all, ddr3 docs */65 { 9, 4 }, { 10, 5 },66 { -1 }67};68 69int70nvkm_sddr3_calc(struct nvkm_ram *ram)71{72 int CWL, CL, WR, DLL = 0, ODT = 0;73 74 DLL = !ram->next->bios.ramcfg_DLLoff;75 76 switch (ram->next->bios.timing_ver) {77 case 0x10:78 if (ram->next->bios.timing_hdr < 0x17) {79 /* XXX: NV50: Get CWL from the timing register */80 return -ENOSYS;81 }82 CWL = ram->next->bios.timing_10_CWL;83 CL = ram->next->bios.timing_10_CL;84 WR = ram->next->bios.timing_10_WR;85 ODT = ram->next->bios.timing_10_ODT;86 break;87 case 0x20:88 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;89 CL = (ram->next->bios.timing[1] & 0x0000001f) >> 0;90 WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;91 /* XXX: Get these values from the VBIOS instead */92 ODT = (ram->mr[1] & 0x004) >> 2 |93 (ram->mr[1] & 0x040) >> 5 |94 (ram->mr[1] & 0x200) >> 7;95 break;96 default:97 return -ENOSYS;98 }99 100 CWL = ramxlat(ramddr3_cwl, CWL);101 CL = ramxlat(ramddr3_cl, CL);102 WR = ramxlat(ramddr3_wr, WR);103 if (CL < 0 || CWL < 0 || WR < 0)104 return -EINVAL;105 106 ram->mr[0] &= ~0xf74;107 ram->mr[0] |= (WR & 0x07) << 9;108 ram->mr[0] |= (CL & 0x0e) << 3;109 ram->mr[0] |= (CL & 0x01) << 2;110 111 ram->mr[1] &= ~0x245;112 ram->mr[1] |= (ODT & 0x1) << 2;113 ram->mr[1] |= (ODT & 0x2) << 5;114 ram->mr[1] |= (ODT & 0x4) << 7;115 ram->mr[1] |= !DLL;116 117 ram->mr[2] &= ~0x038;118 ram->mr[2] |= (CWL & 0x07) << 3;119 return 0;120}121