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1/*2 * Copyright 2022 Red Hat Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 */22#include "priv.h"23 24#include <subdev/fb.h>25 26#include <nvfw/flcn.h>27#include <nvfw/fw.h>28#include <nvfw/hs.h>29 30int31tu102_gsp_booter_ctor(struct nvkm_gsp *gsp, const char *name, const struct firmware *blob,32 struct nvkm_falcon *falcon, struct nvkm_falcon_fw *fw)33{34 struct nvkm_subdev *subdev = &gsp->subdev;35 const struct nvkm_falcon_fw_func *func = &gm200_flcn_fw;36 const struct nvfw_bin_hdr *hdr;37 const struct nvfw_hs_header_v2 *hshdr;38 const struct nvfw_hs_load_header_v2 *lhdr;39 u32 loc, sig, cnt;40 int ret;41 42 hdr = nvfw_bin_hdr(subdev, blob->data);43 hshdr = nvfw_hs_header_v2(subdev, blob->data + hdr->header_offset);44 loc = *(u32 *)(blob->data + hshdr->patch_loc);45 sig = *(u32 *)(blob->data + hshdr->patch_sig);46 cnt = *(u32 *)(blob->data + hshdr->num_sig);47 48 ret = nvkm_falcon_fw_ctor(func, name, subdev->device, true,49 blob->data + hdr->data_offset, hdr->data_size, falcon, fw);50 if (ret)51 goto done;52 53 ret = nvkm_falcon_fw_sign(fw, loc, hshdr->sig_prod_size / cnt, blob->data,54 cnt, hshdr->sig_prod_offset + sig, 0, 0);55 if (ret)56 goto done;57 58 lhdr = nvfw_hs_load_header_v2(subdev, blob->data + hshdr->header_offset);59 60 fw->nmem_base_img = 0;61 fw->nmem_base = lhdr->os_code_offset;62 fw->nmem_size = lhdr->os_code_size;63 fw->imem_base_img = fw->nmem_size;64 fw->imem_base = lhdr->app[0].offset;65 fw->imem_size = lhdr->app[0].size;66 fw->dmem_base_img = lhdr->os_data_offset;67 fw->dmem_base = 0;68 fw->dmem_size = lhdr->os_data_size;69 fw->dmem_sign = loc - fw->dmem_base_img;70 fw->boot_addr = lhdr->os_code_offset;71 72done:73 if (ret)74 nvkm_falcon_fw_dtor(fw);75 76 return ret;77}78 79static int80tu102_gsp_fwsec_load_bld(struct nvkm_falcon_fw *fw)81{82 struct flcn_bl_dmem_desc_v2 desc = {83 .ctx_dma = FALCON_DMAIDX_PHYS_SYS_NCOH,84 .code_dma_base = fw->fw.phys,85 .non_sec_code_off = fw->nmem_base,86 .non_sec_code_size = fw->nmem_size,87 .sec_code_off = fw->imem_base,88 .sec_code_size = fw->imem_size,89 .code_entry_point = 0,90 .data_dma_base = fw->fw.phys + fw->dmem_base_img,91 .data_size = fw->dmem_size,92 .argc = 0,93 .argv = 0,94 };95 96 flcn_bl_dmem_desc_v2_dump(fw->falcon->user, &desc);97 98 nvkm_falcon_mask(fw->falcon, 0x600 + desc.ctx_dma * 4, 0x00000007, 0x00000005);99 100 return nvkm_falcon_pio_wr(fw->falcon, (u8 *)&desc, 0, 0, DMEM, 0, sizeof(desc), 0, 0);101}102 103const struct nvkm_falcon_fw_func104tu102_gsp_fwsec = {105 .reset = gm200_flcn_fw_reset,106 .load = gm200_flcn_fw_load,107 .load_bld = tu102_gsp_fwsec_load_bld,108 .boot = gm200_flcn_fw_boot,109};110 111int112tu102_gsp_reset(struct nvkm_gsp *gsp)113{114 return gsp->falcon.func->reset_eng(&gsp->falcon);115}116 117static u64118tu102_gsp_vga_workspace_addr(struct nvkm_gsp *gsp, u64 fb_size)119{120 struct nvkm_device *device = gsp->subdev.device;121 const u64 base = fb_size - 0x100000;122 u64 addr = 0;123 124 if (device->disp)125 addr = nvkm_rd32(gsp->subdev.device, 0x625f04);126 if (!(addr & 0x00000008))127 return base;128 129 addr = (addr & 0xffffff00) << 8;130 if (addr < base)131 return fb_size - 0x20000;132 133 return addr;134}135 136int137tu102_gsp_oneinit(struct nvkm_gsp *gsp)138{139 gsp->fb.size = nvkm_fb_vidmem_size(gsp->subdev.device);140 141 gsp->fb.bios.vga_workspace.addr = tu102_gsp_vga_workspace_addr(gsp, gsp->fb.size);142 gsp->fb.bios.vga_workspace.size = gsp->fb.size - gsp->fb.bios.vga_workspace.addr;143 gsp->fb.bios.addr = gsp->fb.bios.vga_workspace.addr;144 gsp->fb.bios.size = gsp->fb.bios.vga_workspace.size;145 146 return r535_gsp_oneinit(gsp);147}148 149const struct nvkm_falcon_func150tu102_gsp_flcn = {151 .disable = gm200_flcn_disable,152 .enable = gm200_flcn_enable,153 .addr2 = 0x1000,154 .riscv_irqmask = 0x2b4,155 .reset_eng = gp102_flcn_reset_eng,156 .reset_wait_mem_scrubbing = gm200_flcn_reset_wait_mem_scrubbing,157 .bind_inst = gm200_flcn_bind_inst,158 .bind_stat = gm200_flcn_bind_stat,159 .bind_intr = true,160 .imem_pio = &gm200_flcn_imem_pio,161 .dmem_pio = &gm200_flcn_dmem_pio,162 .riscv_active = tu102_flcn_riscv_active,163};164 165static const struct nvkm_gsp_func166tu102_gsp_r535_113_01 = {167 .flcn = &tu102_gsp_flcn,168 .fwsec = &tu102_gsp_fwsec,169 170 .sig_section = ".fwsignature_tu10x",171 172 .wpr_heap.base_size = 8 << 20,173 .wpr_heap.min_size = 64 << 20,174 175 .booter.ctor = tu102_gsp_booter_ctor,176 177 .dtor = r535_gsp_dtor,178 .oneinit = tu102_gsp_oneinit,179 .init = r535_gsp_init,180 .fini = r535_gsp_fini,181 .reset = tu102_gsp_reset,182 183 .rm = &r535_gsp_rm,184};185 186static struct nvkm_gsp_fwif187tu102_gsps[] = {188 { 0, r535_gsp_load, &tu102_gsp_r535_113_01, "535.113.01" },189 { -1, gv100_gsp_nofw, &gv100_gsp },190 {}191};192 193int194tu102_gsp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,195 struct nvkm_gsp **pgsp)196{197 return nvkm_gsp_new_(tu102_gsps, device, type, inst, pgsp);198}199