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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * HDMI driver definition for TI OMAP4 Processor.4 *5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/6 */7 8#ifndef _HDMI_H9#define _HDMI_H10 11#include <linux/delay.h>12#include <linux/io.h>13#include <linux/platform_device.h>14#include <linux/hdmi.h>15#include <sound/omap-hdmi-audio.h>16#include <media/cec.h>17#include <drm/drm_bridge.h>18 19#include "omapdss.h"20#include "dss.h"21 22struct dss_device;23 24/* HDMI Wrapper */25 26#define HDMI_WP_REVISION 0x027#define HDMI_WP_SYSCONFIG 0x1028#define HDMI_WP_IRQSTATUS_RAW 0x2429#define HDMI_WP_IRQSTATUS 0x2830#define HDMI_WP_IRQENABLE_SET 0x2C31#define HDMI_WP_IRQENABLE_CLR 0x3032#define HDMI_WP_IRQWAKEEN 0x3433#define HDMI_WP_PWR_CTRL 0x4034#define HDMI_WP_DEBOUNCE 0x4435#define HDMI_WP_VIDEO_CFG 0x5036#define HDMI_WP_VIDEO_SIZE 0x6037#define HDMI_WP_VIDEO_TIMING_H 0x6838#define HDMI_WP_VIDEO_TIMING_V 0x6C39#define HDMI_WP_CLK 0x7040#define HDMI_WP_AUDIO_CFG 0x8041#define HDMI_WP_AUDIO_CFG2 0x8442#define HDMI_WP_AUDIO_CTRL 0x8843#define HDMI_WP_AUDIO_DATA 0x8C44 45/* HDMI WP IRQ flags */46#define HDMI_IRQ_CORE (1 << 0)47#define HDMI_IRQ_OCP_TIMEOUT (1 << 4)48#define HDMI_IRQ_AUDIO_FIFO_UNDERFLOW (1 << 8)49#define HDMI_IRQ_AUDIO_FIFO_OVERFLOW (1 << 9)50#define HDMI_IRQ_AUDIO_FIFO_SAMPLE_REQ (1 << 10)51#define HDMI_IRQ_VIDEO_VSYNC (1 << 16)52#define HDMI_IRQ_VIDEO_FRAME_DONE (1 << 17)53#define HDMI_IRQ_PHY_LINE5V_ASSERT (1 << 24)54#define HDMI_IRQ_LINK_CONNECT (1 << 25)55#define HDMI_IRQ_LINK_DISCONNECT (1 << 26)56#define HDMI_IRQ_PLL_LOCK (1 << 29)57#define HDMI_IRQ_PLL_UNLOCK (1 << 30)58#define HDMI_IRQ_PLL_RECAL (1 << 31)59 60/* HDMI PLL */61 62#define PLLCTRL_PLL_CONTROL 0x063#define PLLCTRL_PLL_STATUS 0x464#define PLLCTRL_PLL_GO 0x865#define PLLCTRL_CFG1 0xC66#define PLLCTRL_CFG2 0x1067#define PLLCTRL_CFG3 0x1468#define PLLCTRL_SSC_CFG1 0x1869#define PLLCTRL_SSC_CFG2 0x1C70#define PLLCTRL_CFG4 0x2071 72/* HDMI PHY */73 74#define HDMI_TXPHY_TX_CTRL 0x075#define HDMI_TXPHY_DIGITAL_CTRL 0x476#define HDMI_TXPHY_POWER_CTRL 0x877#define HDMI_TXPHY_PAD_CFG_CTRL 0xC78#define HDMI_TXPHY_BIST_CONTROL 0x1C79 80enum hdmi_pll_pwr {81 HDMI_PLLPWRCMD_ALLOFF = 0,82 HDMI_PLLPWRCMD_PLLONLY = 1,83 HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,84 HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 385};86 87enum hdmi_phy_pwr {88 HDMI_PHYPWRCMD_OFF = 0,89 HDMI_PHYPWRCMD_LDOON = 1,90 HDMI_PHYPWRCMD_TXON = 291};92 93enum hdmi_core_hdmi_dvi {94 HDMI_DVI = 0,95 HDMI_HDMI = 196};97 98enum hdmi_packing_mode {99 HDMI_PACK_10b_RGB_YUV444 = 0,100 HDMI_PACK_24b_RGB_YUV444_YUV422 = 1,101 HDMI_PACK_20b_YUV422 = 2,102 HDMI_PACK_ALREADYPACKED = 7103};104 105enum hdmi_stereo_channels {106 HDMI_AUDIO_STEREO_NOCHANNELS = 0,107 HDMI_AUDIO_STEREO_ONECHANNEL = 1,108 HDMI_AUDIO_STEREO_TWOCHANNELS = 2,109 HDMI_AUDIO_STEREO_THREECHANNELS = 3,110 HDMI_AUDIO_STEREO_FOURCHANNELS = 4111};112 113enum hdmi_audio_type {114 HDMI_AUDIO_TYPE_LPCM = 0,115 HDMI_AUDIO_TYPE_IEC = 1116};117 118enum hdmi_audio_justify {119 HDMI_AUDIO_JUSTIFY_LEFT = 0,120 HDMI_AUDIO_JUSTIFY_RIGHT = 1121};122 123enum hdmi_audio_sample_order {124 HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,125 HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1126};127 128enum hdmi_audio_samples_perword {129 HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,130 HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1131};132 133enum hdmi_audio_sample_size_omap {134 HDMI_AUDIO_SAMPLE_16BITS = 0,135 HDMI_AUDIO_SAMPLE_24BITS = 1136};137 138enum hdmi_audio_transf_mode {139 HDMI_AUDIO_TRANSF_DMA = 0,140 HDMI_AUDIO_TRANSF_IRQ = 1141};142 143enum hdmi_audio_blk_strt_end_sig {144 HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,145 HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1146};147 148enum hdmi_core_audio_layout {149 HDMI_AUDIO_LAYOUT_2CH = 0,150 HDMI_AUDIO_LAYOUT_8CH = 1,151 HDMI_AUDIO_LAYOUT_6CH = 2152};153 154enum hdmi_core_cts_mode {155 HDMI_AUDIO_CTS_MODE_HW = 0,156 HDMI_AUDIO_CTS_MODE_SW = 1157};158 159enum hdmi_audio_mclk_mode {160 HDMI_AUDIO_MCLK_128FS = 0,161 HDMI_AUDIO_MCLK_256FS = 1,162 HDMI_AUDIO_MCLK_384FS = 2,163 HDMI_AUDIO_MCLK_512FS = 3,164 HDMI_AUDIO_MCLK_768FS = 4,165 HDMI_AUDIO_MCLK_1024FS = 5,166 HDMI_AUDIO_MCLK_1152FS = 6,167 HDMI_AUDIO_MCLK_192FS = 7168};169 170struct hdmi_video_format {171 enum hdmi_packing_mode packing_mode;172 u32 y_res; /* Line per panel */173 u32 x_res; /* pixel per line */174};175 176struct hdmi_config {177 struct videomode vm;178 struct hdmi_avi_infoframe infoframe;179 enum hdmi_core_hdmi_dvi hdmi_dvi_mode;180};181 182struct hdmi_audio_format {183 enum hdmi_stereo_channels stereo_channels;184 u8 active_chnnls_msk;185 enum hdmi_audio_type type;186 enum hdmi_audio_justify justification;187 enum hdmi_audio_sample_order sample_order;188 enum hdmi_audio_samples_perword samples_per_word;189 enum hdmi_audio_sample_size_omap sample_size;190 enum hdmi_audio_blk_strt_end_sig en_sig_blk_strt_end;191};192 193struct hdmi_audio_dma {194 u8 transfer_size;195 u8 block_size;196 enum hdmi_audio_transf_mode mode;197 u16 fifo_threshold;198};199 200struct hdmi_core_audio_i2s_config {201 u8 in_length_bits;202 u8 justification;203 u8 sck_edge_mode;204 u8 vbit;205 u8 direction;206 u8 shift;207 u8 active_sds;208};209 210struct hdmi_core_audio_config {211 struct hdmi_core_audio_i2s_config i2s_cfg;212 struct snd_aes_iec958 *iec60958_cfg;213 bool fs_override;214 u32 n;215 u32 cts;216 u32 aud_par_busclk;217 enum hdmi_core_audio_layout layout;218 enum hdmi_core_cts_mode cts_mode;219 bool use_mclk;220 enum hdmi_audio_mclk_mode mclk_mode;221 bool en_acr_pkt;222 bool en_dsd_audio;223 bool en_parallel_aud_input;224 bool en_spdif;225};226 227struct hdmi_wp_data {228 void __iomem *base;229 phys_addr_t phys_base;230 unsigned int version;231};232 233struct hdmi_pll_data {234 struct dss_pll pll;235 236 void __iomem *base;237 238 struct platform_device *pdev;239 struct hdmi_wp_data *wp;240};241 242struct hdmi_phy_features {243 bool bist_ctrl;244 bool ldo_voltage;245 unsigned long max_phy;246};247 248struct hdmi_phy_data {249 void __iomem *base;250 251 const struct hdmi_phy_features *features;252 u8 lane_function[4];253 u8 lane_polarity[4];254};255 256struct hdmi_core_data {257 void __iomem *base;258 bool cts_swmode;259 bool audio_use_mclk;260 261 struct hdmi_wp_data *wp;262 unsigned int core_pwr_cnt;263 struct cec_adapter *adap;264};265 266static inline void hdmi_write_reg(void __iomem *base_addr, const u32 idx,267 u32 val)268{269 __raw_writel(val, base_addr + idx);270}271 272static inline u32 hdmi_read_reg(void __iomem *base_addr, const u32 idx)273{274 return __raw_readl(base_addr + idx);275}276 277#define REG_FLD_MOD(base, idx, val, start, end) \278 hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\279 val, start, end))280#define REG_GET(base, idx, start, end) \281 FLD_GET(hdmi_read_reg(base, idx), start, end)282 283static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,284 const u32 idx, int b2, int b1, u32 val)285{286 u32 t = 0, v;287 while (val != (v = REG_GET(base_addr, idx, b2, b1))) {288 if (t++ > 10000)289 return v;290 udelay(1);291 }292 return v;293}294 295/* HDMI wrapper funcs */296int hdmi_wp_video_start(struct hdmi_wp_data *wp);297void hdmi_wp_video_stop(struct hdmi_wp_data *wp);298void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);299u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);300void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);301void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);302void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);303int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);304int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);305void hdmi_wp_video_config_format(struct hdmi_wp_data *wp,306 const struct hdmi_video_format *video_fmt);307void hdmi_wp_video_config_interface(struct hdmi_wp_data *wp,308 const struct videomode *vm);309void hdmi_wp_video_config_timing(struct hdmi_wp_data *wp,310 const struct videomode *vm);311void hdmi_wp_init_vid_fmt_timings(struct hdmi_video_format *video_fmt,312 struct videomode *vm, const struct hdmi_config *param);313int hdmi_wp_init(struct platform_device *pdev, struct hdmi_wp_data *wp,314 unsigned int version);315phys_addr_t hdmi_wp_get_audio_dma_addr(struct hdmi_wp_data *wp);316 317/* HDMI PLL funcs */318void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s);319int hdmi_pll_init(struct dss_device *dss, struct platform_device *pdev,320 struct hdmi_pll_data *pll, struct hdmi_wp_data *wp);321void hdmi_pll_uninit(struct hdmi_pll_data *hpll);322 323/* HDMI PHY funcs */324int hdmi_phy_configure(struct hdmi_phy_data *phy, unsigned long hfbitclk,325 unsigned long lfbitclk);326void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s);327int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy,328 unsigned int version);329int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes);330 331/* HDMI common funcs */332int hdmi_parse_lanes_of(struct platform_device *pdev, struct device_node *ep,333 struct hdmi_phy_data *phy);334 335/* Audio funcs */336int hdmi_compute_acr(u32 pclk, u32 sample_freq, u32 *n, u32 *cts);337int hdmi_wp_audio_enable(struct hdmi_wp_data *wp, bool enable);338int hdmi_wp_audio_core_req_enable(struct hdmi_wp_data *wp, bool enable);339void hdmi_wp_audio_config_format(struct hdmi_wp_data *wp,340 struct hdmi_audio_format *aud_fmt);341void hdmi_wp_audio_config_dma(struct hdmi_wp_data *wp,342 struct hdmi_audio_dma *aud_dma);343static inline bool hdmi_mode_has_audio(struct hdmi_config *cfg)344{345 return cfg->hdmi_dvi_mode == HDMI_HDMI ? true : false;346}347 348/* HDMI DRV data */349struct omap_hdmi {350 struct mutex lock;351 struct platform_device *pdev;352 struct dss_device *dss;353 354 struct dss_debugfs_entry *debugfs;355 356 struct hdmi_wp_data wp;357 struct hdmi_pll_data pll;358 struct hdmi_phy_data phy;359 struct hdmi_core_data core;360 361 struct hdmi_config cfg;362 363 struct regulator *vdda_reg;364 365 bool core_enabled;366 367 struct omap_dss_device output;368 struct drm_bridge bridge;369 370 struct platform_device *audio_pdev;371 void (*audio_abort_cb)(struct device *dev);372 int wp_idlemode;373 374 bool audio_configured;375 struct omap_dss_audio audio_config;376 377 /* This lock should be taken when booleans below are touched. */378 spinlock_t audio_playing_lock;379 bool audio_playing;380 bool display_enabled;381};382 383#define drm_bridge_to_hdmi(b) container_of(b, struct omap_hdmi, bridge)384 385#endif386