269 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * HDMI header definition for OMAP4 HDMI core IP4 *5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com/6 */7 8#ifndef _HDMI4_CORE_H_9#define _HDMI4_CORE_H_10 11#include "hdmi.h"12 13/* OMAP4 HDMI IP Core System */14 15#define HDMI_CORE_SYS_VND_IDL 0x016#define HDMI_CORE_SYS_DEV_IDL 0x817#define HDMI_CORE_SYS_DEV_IDH 0xC18#define HDMI_CORE_SYS_DEV_REV 0x1019#define HDMI_CORE_SYS_SRST 0x1420#define HDMI_CORE_SYS_SYS_CTRL1 0x2021#define HDMI_CORE_SYS_SYS_STAT 0x2422#define HDMI_CORE_SYS_SYS_CTRL3 0x2823#define HDMI_CORE_SYS_DCTL 0x3424#define HDMI_CORE_SYS_DE_DLY 0xC825#define HDMI_CORE_SYS_DE_CTRL 0xCC26#define HDMI_CORE_SYS_DE_TOP 0xD027#define HDMI_CORE_SYS_DE_CNTL 0xD828#define HDMI_CORE_SYS_DE_CNTH 0xDC29#define HDMI_CORE_SYS_DE_LINL 0xE030#define HDMI_CORE_SYS_DE_LINH_1 0xE431#define HDMI_CORE_SYS_HRES_L 0xE832#define HDMI_CORE_SYS_HRES_H 0xEC33#define HDMI_CORE_SYS_VRES_L 0xF034#define HDMI_CORE_SYS_VRES_H 0xF435#define HDMI_CORE_SYS_IADJUST 0xF836#define HDMI_CORE_SYS_POLDETECT 0xFC37#define HDMI_CORE_SYS_HWIDTH1 0x11038#define HDMI_CORE_SYS_HWIDTH2 0x11439#define HDMI_CORE_SYS_VWIDTH 0x11C40#define HDMI_CORE_SYS_VID_CTRL 0x12041#define HDMI_CORE_SYS_VID_ACEN 0x12442#define HDMI_CORE_SYS_VID_MODE 0x12843#define HDMI_CORE_SYS_VID_BLANK1 0x12C44#define HDMI_CORE_SYS_VID_BLANK2 0x13045#define HDMI_CORE_SYS_VID_BLANK3 0x13446#define HDMI_CORE_SYS_DC_HEADER 0x13847#define HDMI_CORE_SYS_VID_DITHER 0x13C48#define HDMI_CORE_SYS_RGB2XVYCC_CT 0x14049#define HDMI_CORE_SYS_R2Y_COEFF_LOW 0x14450#define HDMI_CORE_SYS_R2Y_COEFF_UP 0x14851#define HDMI_CORE_SYS_G2Y_COEFF_LOW 0x14C52#define HDMI_CORE_SYS_G2Y_COEFF_UP 0x15053#define HDMI_CORE_SYS_B2Y_COEFF_LOW 0x15454#define HDMI_CORE_SYS_B2Y_COEFF_UP 0x15855#define HDMI_CORE_SYS_R2CB_COEFF_LOW 0x15C56#define HDMI_CORE_SYS_R2CB_COEFF_UP 0x16057#define HDMI_CORE_SYS_G2CB_COEFF_LOW 0x16458#define HDMI_CORE_SYS_G2CB_COEFF_UP 0x16859#define HDMI_CORE_SYS_B2CB_COEFF_LOW 0x16C60#define HDMI_CORE_SYS_B2CB_COEFF_UP 0x17061#define HDMI_CORE_SYS_R2CR_COEFF_LOW 0x17462#define HDMI_CORE_SYS_R2CR_COEFF_UP 0x17863#define HDMI_CORE_SYS_G2CR_COEFF_LOW 0x17C64#define HDMI_CORE_SYS_G2CR_COEFF_UP 0x18065#define HDMI_CORE_SYS_B2CR_COEFF_LOW 0x18466#define HDMI_CORE_SYS_B2CR_COEFF_UP 0x18867#define HDMI_CORE_SYS_RGB_OFFSET_LOW 0x18C68#define HDMI_CORE_SYS_RGB_OFFSET_UP 0x19069#define HDMI_CORE_SYS_Y_OFFSET_LOW 0x19470#define HDMI_CORE_SYS_Y_OFFSET_UP 0x19871#define HDMI_CORE_SYS_CBCR_OFFSET_LOW 0x19C72#define HDMI_CORE_SYS_CBCR_OFFSET_UP 0x1A073#define HDMI_CORE_SYS_INTR_STATE 0x1C074#define HDMI_CORE_SYS_INTR1 0x1C475#define HDMI_CORE_SYS_INTR2 0x1C876#define HDMI_CORE_SYS_INTR3 0x1CC77#define HDMI_CORE_SYS_INTR4 0x1D078#define HDMI_CORE_SYS_INTR_UNMASK1 0x1D479#define HDMI_CORE_SYS_INTR_UNMASK2 0x1D880#define HDMI_CORE_SYS_INTR_UNMASK3 0x1DC81#define HDMI_CORE_SYS_INTR_UNMASK4 0x1E082#define HDMI_CORE_SYS_INTR_CTRL 0x1E483#define HDMI_CORE_SYS_TMDS_CTRL 0x20884 85/* value definitions for HDMI_CORE_SYS_SYS_CTRL1 fields */86#define HDMI_CORE_SYS_SYS_CTRL1_VEN_FOLLOWVSYNC 0x187#define HDMI_CORE_SYS_SYS_CTRL1_HEN_FOLLOWHSYNC 0x188#define HDMI_CORE_SYS_SYS_CTRL1_BSEL_24BITBUS 0x189#define HDMI_CORE_SYS_SYS_CTRL1_EDGE_RISINGEDGE 0x190 91/* HDMI DDC E-DID */92#define HDMI_CORE_DDC_ADDR 0x3B493#define HDMI_CORE_DDC_SEGM 0x3B894#define HDMI_CORE_DDC_OFFSET 0x3BC95#define HDMI_CORE_DDC_COUNT1 0x3C096#define HDMI_CORE_DDC_COUNT2 0x3C497#define HDMI_CORE_DDC_STATUS 0x3C898#define HDMI_CORE_DDC_CMD 0x3CC99#define HDMI_CORE_DDC_DATA 0x3D0100 101/* HDMI IP Core Audio Video */102 103#define HDMI_CORE_AV_ACR_CTRL 0x4104#define HDMI_CORE_AV_FREQ_SVAL 0x8105#define HDMI_CORE_AV_N_SVAL1 0xC106#define HDMI_CORE_AV_N_SVAL2 0x10107#define HDMI_CORE_AV_N_SVAL3 0x14108#define HDMI_CORE_AV_CTS_SVAL1 0x18109#define HDMI_CORE_AV_CTS_SVAL2 0x1C110#define HDMI_CORE_AV_CTS_SVAL3 0x20111#define HDMI_CORE_AV_CTS_HVAL1 0x24112#define HDMI_CORE_AV_CTS_HVAL2 0x28113#define HDMI_CORE_AV_CTS_HVAL3 0x2C114#define HDMI_CORE_AV_AUD_MODE 0x50115#define HDMI_CORE_AV_SPDIF_CTRL 0x54116#define HDMI_CORE_AV_HW_SPDIF_FS 0x60117#define HDMI_CORE_AV_SWAP_I2S 0x64118#define HDMI_CORE_AV_SPDIF_ERTH 0x6C119#define HDMI_CORE_AV_I2S_IN_MAP 0x70120#define HDMI_CORE_AV_I2S_IN_CTRL 0x74121#define HDMI_CORE_AV_I2S_CHST0 0x78122#define HDMI_CORE_AV_I2S_CHST1 0x7C123#define HDMI_CORE_AV_I2S_CHST2 0x80124#define HDMI_CORE_AV_I2S_CHST4 0x84125#define HDMI_CORE_AV_I2S_CHST5 0x88126#define HDMI_CORE_AV_ASRC 0x8C127#define HDMI_CORE_AV_I2S_IN_LEN 0x90128#define HDMI_CORE_AV_HDMI_CTRL 0xBC129#define HDMI_CORE_AV_AUDO_TXSTAT 0xC0130#define HDMI_CORE_AV_AUD_PAR_BUSCLK_1 0xCC131#define HDMI_CORE_AV_AUD_PAR_BUSCLK_2 0xD0132#define HDMI_CORE_AV_AUD_PAR_BUSCLK_3 0xD4133#define HDMI_CORE_AV_TEST_TXCTRL 0xF0134#define HDMI_CORE_AV_DPD 0xF4135#define HDMI_CORE_AV_PB_CTRL1 0xF8136#define HDMI_CORE_AV_PB_CTRL2 0xFC137#define HDMI_CORE_AV_AVI_BASE 0x100138#define HDMI_CORE_AV_AVI_TYPE 0x100139#define HDMI_CORE_AV_AVI_VERS 0x104140#define HDMI_CORE_AV_AVI_LEN 0x108141#define HDMI_CORE_AV_AVI_CHSUM 0x10C142#define HDMI_CORE_AV_AVI_DBYTE(n) (n * 4 + 0x110)143#define HDMI_CORE_AV_SPD_TYPE 0x180144#define HDMI_CORE_AV_SPD_VERS 0x184145#define HDMI_CORE_AV_SPD_LEN 0x188146#define HDMI_CORE_AV_SPD_CHSUM 0x18C147#define HDMI_CORE_AV_SPD_DBYTE(n) (n * 4 + 0x190)148#define HDMI_CORE_AV_AUDIO_TYPE 0x200149#define HDMI_CORE_AV_AUDIO_VERS 0x204150#define HDMI_CORE_AV_AUDIO_LEN 0x208151#define HDMI_CORE_AV_AUDIO_CHSUM 0x20C152#define HDMI_CORE_AV_AUD_DBYTE(n) (n * 4 + 0x210)153#define HDMI_CORE_AV_MPEG_TYPE 0x280154#define HDMI_CORE_AV_MPEG_VERS 0x284155#define HDMI_CORE_AV_MPEG_LEN 0x288156#define HDMI_CORE_AV_MPEG_CHSUM 0x28C157#define HDMI_CORE_AV_MPEG_DBYTE(n) (n * 4 + 0x290)158#define HDMI_CORE_AV_GEN_DBYTE(n) (n * 4 + 0x300)159#define HDMI_CORE_AV_CP_BYTE1 0x37C160#define HDMI_CORE_AV_GEN2_DBYTE(n) (n * 4 + 0x380)161#define HDMI_CORE_AV_CEC_ADDR_ID 0x3FC162 163#define HDMI_CORE_AV_SPD_DBYTE_ELSIZE 0x4164#define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE 0x4165#define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE 0x4166#define HDMI_CORE_AV_GEN_DBYTE_ELSIZE 0x4167 168#define HDMI_CORE_AV_AVI_DBYTE_NELEMS 15169#define HDMI_CORE_AV_SPD_DBYTE_NELEMS 27170#define HDMI_CORE_AV_AUD_DBYTE_NELEMS 10171#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS 27172#define HDMI_CORE_AV_GEN_DBYTE_NELEMS 31173#define HDMI_CORE_AV_GEN2_DBYTE_NELEMS 31174 175enum hdmi_core_inputbus_width {176 HDMI_INPUT_8BIT = 0,177 HDMI_INPUT_10BIT = 1,178 HDMI_INPUT_12BIT = 2179};180 181enum hdmi_core_dither_trunc {182 HDMI_OUTPUTTRUNCATION_8BIT = 0,183 HDMI_OUTPUTTRUNCATION_10BIT = 1,184 HDMI_OUTPUTTRUNCATION_12BIT = 2,185 HDMI_OUTPUTDITHER_8BIT = 3,186 HDMI_OUTPUTDITHER_10BIT = 4,187 HDMI_OUTPUTDITHER_12BIT = 5188};189 190enum hdmi_core_deepcolor_ed {191 HDMI_DEEPCOLORPACKECTDISABLE = 0,192 HDMI_DEEPCOLORPACKECTENABLE = 1193};194 195enum hdmi_core_packet_mode {196 HDMI_PACKETMODERESERVEDVALUE = 0,197 HDMI_PACKETMODE24BITPERPIXEL = 4,198 HDMI_PACKETMODE30BITPERPIXEL = 5,199 HDMI_PACKETMODE36BITPERPIXEL = 6,200 HDMI_PACKETMODE48BITPERPIXEL = 7201};202 203enum hdmi_core_tclkselclkmult {204 HDMI_FPLL05IDCK = 0,205 HDMI_FPLL10IDCK = 1,206 HDMI_FPLL20IDCK = 2,207 HDMI_FPLL40IDCK = 3208};209 210enum hdmi_core_packet_ctrl {211 HDMI_PACKETENABLE = 1,212 HDMI_PACKETDISABLE = 0,213 HDMI_PACKETREPEATON = 1,214 HDMI_PACKETREPEATOFF = 0215};216 217enum hdmi_audio_i2s_config {218 HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST = 0,219 HDMI_AUDIO_I2S_LSB_SHIFTED_FIRST = 1,220 HDMI_AUDIO_I2S_SCK_EDGE_FALLING = 0,221 HDMI_AUDIO_I2S_SCK_EDGE_RISING = 1,222 HDMI_AUDIO_I2S_VBIT_FOR_PCM = 0,223 HDMI_AUDIO_I2S_VBIT_FOR_COMPRESSED = 1,224 HDMI_AUDIO_I2S_FIRST_BIT_SHIFT = 0,225 HDMI_AUDIO_I2S_FIRST_BIT_NO_SHIFT = 1,226 HDMI_AUDIO_I2S_SD0_EN = 1,227 HDMI_AUDIO_I2S_SD1_EN = 1 << 1,228 HDMI_AUDIO_I2S_SD2_EN = 1 << 2,229 HDMI_AUDIO_I2S_SD3_EN = 1 << 3,230};231 232struct hdmi_core_video_config {233 enum hdmi_core_inputbus_width ip_bus_width;234 enum hdmi_core_dither_trunc op_dither_truc;235 enum hdmi_core_deepcolor_ed deep_color_pkt;236 enum hdmi_core_packet_mode pkt_mode;237 enum hdmi_core_hdmi_dvi hdmi_dvi;238 enum hdmi_core_tclkselclkmult tclk_sel_clkmult;239};240 241struct hdmi_core_packet_enable_repeat {242 u32 audio_pkt;243 u32 audio_pkt_repeat;244 u32 avi_infoframe;245 u32 avi_infoframe_repeat;246 u32 gen_cntrl_pkt;247 u32 gen_cntrl_pkt_repeat;248 u32 generic_pkt;249 u32 generic_pkt_repeat;250};251 252int hdmi4_core_ddc_init(struct hdmi_core_data *core);253int hdmi4_core_ddc_read(void *data, u8 *buf, unsigned int block, size_t len);254 255void hdmi4_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,256 struct hdmi_config *cfg);257void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s);258int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core);259 260int hdmi4_core_enable(struct hdmi_core_data *core);261void hdmi4_core_disable(struct hdmi_core_data *core);262void hdmi4_core_powerdown_disable(struct hdmi_core_data *core);263 264int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp);265void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp);266int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,267 struct omap_dss_audio *audio, u32 pclk);268#endif269