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1// SPDX-License-Identifier: GPL-2.02/*3 * Copyright (C) STMicroelectronics SA 20174 *5 * Authors: Philippe Cornu <philippe.cornu@st.com>6 * Yannick Fertre <yannick.fertre@st.com>7 */8 9#include <linux/backlight.h>10#include <linux/delay.h>11#include <linux/gpio/consumer.h>12#include <linux/module.h>13#include <linux/regulator/consumer.h>14 15#include <video/mipi_display.h>16 17#include <drm/drm_mipi_dsi.h>18#include <drm/drm_modes.h>19#include <drm/drm_panel.h>20 21#define OTM8009A_BACKLIGHT_DEFAULT 24022#define OTM8009A_BACKLIGHT_MAX 25523 24/* Manufacturer Command Set */25#define MCS_ADRSFT 0x0000 /* Address Shift Function */26#define MCS_PANSET 0xB3A6 /* Panel Type Setting */27#define MCS_SD_CTRL 0xC0A2 /* Source Driver Timing Setting */28#define MCS_P_DRV_M 0xC0B4 /* Panel Driving Mode */29#define MCS_OSC_ADJ 0xC181 /* Oscillator Adjustment for Idle/Normal mode */30#define MCS_RGB_VID_SET 0xC1A1 /* RGB Video Mode Setting */31#define MCS_SD_PCH_CTRL 0xC480 /* Source Driver Precharge Control */32#define MCS_NO_DOC1 0xC48A /* Command not documented */33#define MCS_PWR_CTRL1 0xC580 /* Power Control Setting 1 */34#define MCS_PWR_CTRL2 0xC590 /* Power Control Setting 2 for Normal Mode */35#define MCS_PWR_CTRL4 0xC5B0 /* Power Control Setting 4 for DC Voltage */36#define MCS_PANCTRLSET1 0xCB80 /* Panel Control Setting 1 */37#define MCS_PANCTRLSET2 0xCB90 /* Panel Control Setting 2 */38#define MCS_PANCTRLSET3 0xCBA0 /* Panel Control Setting 3 */39#define MCS_PANCTRLSET4 0xCBB0 /* Panel Control Setting 4 */40#define MCS_PANCTRLSET5 0xCBC0 /* Panel Control Setting 5 */41#define MCS_PANCTRLSET6 0xCBD0 /* Panel Control Setting 6 */42#define MCS_PANCTRLSET7 0xCBE0 /* Panel Control Setting 7 */43#define MCS_PANCTRLSET8 0xCBF0 /* Panel Control Setting 8 */44#define MCS_PANU2D1 0xCC80 /* Panel U2D Setting 1 */45#define MCS_PANU2D2 0xCC90 /* Panel U2D Setting 2 */46#define MCS_PANU2D3 0xCCA0 /* Panel U2D Setting 3 */47#define MCS_PAND2U1 0xCCB0 /* Panel D2U Setting 1 */48#define MCS_PAND2U2 0xCCC0 /* Panel D2U Setting 2 */49#define MCS_PAND2U3 0xCCD0 /* Panel D2U Setting 3 */50#define MCS_GOAVST 0xCE80 /* GOA VST Setting */51#define MCS_GOACLKA1 0xCEA0 /* GOA CLKA1 Setting */52#define MCS_GOACLKA3 0xCEB0 /* GOA CLKA3 Setting */53#define MCS_GOAECLK 0xCFC0 /* GOA ECLK Setting */54#define MCS_NO_DOC2 0xCFD0 /* Command not documented */55#define MCS_GVDDSET 0xD800 /* GVDD/NGVDD */56#define MCS_VCOMDC 0xD900 /* VCOM Voltage Setting */57#define MCS_GMCT2_2P 0xE100 /* Gamma Correction 2.2+ Setting */58#define MCS_GMCT2_2N 0xE200 /* Gamma Correction 2.2- Setting */59#define MCS_NO_DOC3 0xF5B6 /* Command not documented */60#define MCS_CMD2_ENA1 0xFF00 /* Enable Access Command2 "CMD2" */61#define MCS_CMD2_ENA2 0xFF80 /* Enable Access Orise Command2 */62 63#define OTM8009A_HDISPLAY 48064#define OTM8009A_VDISPLAY 80065 66struct otm8009a {67 struct device *dev;68 struct drm_panel panel;69 struct backlight_device *bl_dev;70 struct gpio_desc *reset_gpio;71 struct regulator *supply;72 bool prepared;73};74 75static const struct drm_display_mode modes[] = {76 { /* 50 Hz, preferred */77 .clock = 29700,78 .hdisplay = 480,79 .hsync_start = 480 + 98,80 .hsync_end = 480 + 98 + 32,81 .htotal = 480 + 98 + 32 + 98,82 .vdisplay = 800,83 .vsync_start = 800 + 15,84 .vsync_end = 800 + 15 + 10,85 .vtotal = 800 + 15 + 10 + 14,86 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,87 .width_mm = 52,88 .height_mm = 86,89 },90 { /* 60 Hz */91 .clock = 33000,92 .hdisplay = 480,93 .hsync_start = 480 + 70,94 .hsync_end = 480 + 70 + 32,95 .htotal = 480 + 70 + 32 + 72,96 .vdisplay = 800,97 .vsync_start = 800 + 15,98 .vsync_end = 800 + 15 + 10,99 .vtotal = 800 + 15 + 10 + 16,100 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,101 .width_mm = 52,102 .height_mm = 86,103 },104};105 106static inline struct otm8009a *panel_to_otm8009a(struct drm_panel *panel)107{108 return container_of(panel, struct otm8009a, panel);109}110 111static void otm8009a_dcs_write_buf(struct otm8009a *ctx, const void *data,112 size_t len)113{114 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);115 116 if (mipi_dsi_dcs_write_buffer(dsi, data, len) < 0)117 dev_warn(ctx->dev, "mipi dsi dcs write buffer failed\n");118}119 120#define dcs_write_seq(ctx, seq...) \121({ \122 static const u8 d[] = { seq }; \123 otm8009a_dcs_write_buf(ctx, d, ARRAY_SIZE(d)); \124})125 126#define dcs_write_cmd_at(ctx, cmd, seq...) \127({ \128 dcs_write_seq(ctx, MCS_ADRSFT, (cmd) & 0xFF); \129 dcs_write_seq(ctx, (cmd) >> 8, seq); \130})131 132static int otm8009a_init_sequence(struct otm8009a *ctx)133{134 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);135 int ret;136 137 /* Enter CMD2 */138 dcs_write_cmd_at(ctx, MCS_CMD2_ENA1, 0x80, 0x09, 0x01);139 140 /* Enter Orise Command2 */141 dcs_write_cmd_at(ctx, MCS_CMD2_ENA2, 0x80, 0x09);142 143 dcs_write_cmd_at(ctx, MCS_SD_PCH_CTRL, 0x30);144 mdelay(10);145 146 dcs_write_cmd_at(ctx, MCS_NO_DOC1, 0x40);147 mdelay(10);148 149 dcs_write_cmd_at(ctx, MCS_PWR_CTRL4 + 1, 0xA9);150 dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 1, 0x34);151 dcs_write_cmd_at(ctx, MCS_P_DRV_M, 0x50);152 dcs_write_cmd_at(ctx, MCS_VCOMDC, 0x4E);153 dcs_write_cmd_at(ctx, MCS_OSC_ADJ, 0x66); /* 65Hz */154 dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 2, 0x01);155 dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 5, 0x34);156 dcs_write_cmd_at(ctx, MCS_PWR_CTRL2 + 4, 0x33);157 dcs_write_cmd_at(ctx, MCS_GVDDSET, 0x79, 0x79);158 dcs_write_cmd_at(ctx, MCS_SD_CTRL + 1, 0x1B);159 dcs_write_cmd_at(ctx, MCS_PWR_CTRL1 + 2, 0x83);160 dcs_write_cmd_at(ctx, MCS_SD_PCH_CTRL + 1, 0x83);161 dcs_write_cmd_at(ctx, MCS_RGB_VID_SET, 0x0E);162 dcs_write_cmd_at(ctx, MCS_PANSET, 0x00, 0x01);163 164 dcs_write_cmd_at(ctx, MCS_GOAVST, 0x85, 0x01, 0x00, 0x84, 0x01, 0x00);165 dcs_write_cmd_at(ctx, MCS_GOACLKA1, 0x18, 0x04, 0x03, 0x39, 0x00, 0x00,166 0x00, 0x18, 0x03, 0x03, 0x3A, 0x00, 0x00, 0x00);167 dcs_write_cmd_at(ctx, MCS_GOACLKA3, 0x18, 0x02, 0x03, 0x3B, 0x00, 0x00,168 0x00, 0x18, 0x01, 0x03, 0x3C, 0x00, 0x00, 0x00);169 dcs_write_cmd_at(ctx, MCS_GOAECLK, 0x01, 0x01, 0x20, 0x20, 0x00, 0x00,170 0x01, 0x02, 0x00, 0x00);171 172 dcs_write_cmd_at(ctx, MCS_NO_DOC2, 0x00);173 174 dcs_write_cmd_at(ctx, MCS_PANCTRLSET1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);175 dcs_write_cmd_at(ctx, MCS_PANCTRLSET2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,176 0, 0, 0, 0, 0);177 dcs_write_cmd_at(ctx, MCS_PANCTRLSET3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,178 0, 0, 0, 0, 0);179 dcs_write_cmd_at(ctx, MCS_PANCTRLSET4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);180 dcs_write_cmd_at(ctx, MCS_PANCTRLSET5, 0, 4, 4, 4, 4, 4, 0, 0, 0, 0,181 0, 0, 0, 0, 0);182 dcs_write_cmd_at(ctx, MCS_PANCTRLSET6, 0, 0, 0, 0, 0, 0, 4, 4, 4, 4,183 4, 0, 0, 0, 0);184 dcs_write_cmd_at(ctx, MCS_PANCTRLSET7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);185 dcs_write_cmd_at(ctx, MCS_PANCTRLSET8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,186 0xFF, 0xFF, 0xFF, 0xFF, 0xFF);187 188 dcs_write_cmd_at(ctx, MCS_PANU2D1, 0x00, 0x26, 0x09, 0x0B, 0x01, 0x25,189 0x00, 0x00, 0x00, 0x00);190 dcs_write_cmd_at(ctx, MCS_PANU2D2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,191 0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x0A, 0x0C, 0x02);192 dcs_write_cmd_at(ctx, MCS_PANU2D3, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00,193 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);194 dcs_write_cmd_at(ctx, MCS_PAND2U1, 0x00, 0x25, 0x0C, 0x0A, 0x02, 0x26,195 0x00, 0x00, 0x00, 0x00);196 dcs_write_cmd_at(ctx, MCS_PAND2U2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,197 0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x0B, 0x09, 0x01);198 dcs_write_cmd_at(ctx, MCS_PAND2U3, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00,199 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);200 201 dcs_write_cmd_at(ctx, MCS_PWR_CTRL1 + 1, 0x66);202 203 dcs_write_cmd_at(ctx, MCS_NO_DOC3, 0x06);204 205 dcs_write_cmd_at(ctx, MCS_GMCT2_2P, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10,206 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A,207 0x01);208 dcs_write_cmd_at(ctx, MCS_GMCT2_2N, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10,209 0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A,210 0x01);211 212 /* Exit CMD2 */213 dcs_write_cmd_at(ctx, MCS_CMD2_ENA1, 0xFF, 0xFF, 0xFF);214 215 ret = mipi_dsi_dcs_nop(dsi);216 if (ret)217 return ret;218 219 ret = mipi_dsi_dcs_exit_sleep_mode(dsi);220 if (ret)221 return ret;222 223 /* Wait for sleep out exit */224 mdelay(120);225 226 /* Default portrait 480x800 rgb24 */227 dcs_write_seq(ctx, MIPI_DCS_SET_ADDRESS_MODE, 0x00);228 229 ret = mipi_dsi_dcs_set_column_address(dsi, 0, OTM8009A_HDISPLAY - 1);230 if (ret)231 return ret;232 233 ret = mipi_dsi_dcs_set_page_address(dsi, 0, OTM8009A_VDISPLAY - 1);234 if (ret)235 return ret;236 237 /* See otm8009a driver documentation for pixel format descriptions */238 ret = mipi_dsi_dcs_set_pixel_format(dsi, MIPI_DCS_PIXEL_FMT_24BIT |239 MIPI_DCS_PIXEL_FMT_24BIT << 4);240 if (ret)241 return ret;242 243 /* Disable CABC feature */244 dcs_write_seq(ctx, MIPI_DCS_WRITE_POWER_SAVE, 0x00);245 246 ret = mipi_dsi_dcs_set_display_on(dsi);247 if (ret)248 return ret;249 250 ret = mipi_dsi_dcs_nop(dsi);251 if (ret)252 return ret;253 254 /* Send Command GRAM memory write (no parameters) */255 dcs_write_seq(ctx, MIPI_DCS_WRITE_MEMORY_START);256 257 /* Wait a short while to let the panel be ready before the 1st frame */258 mdelay(10);259 260 return 0;261}262 263static int otm8009a_disable(struct drm_panel *panel)264{265 struct otm8009a *ctx = panel_to_otm8009a(panel);266 struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);267 int ret;268 269 backlight_disable(ctx->bl_dev);270 271 ret = mipi_dsi_dcs_set_display_off(dsi);272 if (ret)273 return ret;274 275 ret = mipi_dsi_dcs_enter_sleep_mode(dsi);276 if (ret)277 return ret;278 279 msleep(120);280 281 return 0;282}283 284static int otm8009a_unprepare(struct drm_panel *panel)285{286 struct otm8009a *ctx = panel_to_otm8009a(panel);287 288 if (ctx->reset_gpio) {289 gpiod_set_value_cansleep(ctx->reset_gpio, 1);290 msleep(20);291 }292 293 regulator_disable(ctx->supply);294 295 ctx->prepared = false;296 297 return 0;298}299 300static int otm8009a_prepare(struct drm_panel *panel)301{302 struct otm8009a *ctx = panel_to_otm8009a(panel);303 int ret;304 305 ret = regulator_enable(ctx->supply);306 if (ret < 0) {307 dev_err(panel->dev, "failed to enable supply: %d\n", ret);308 return ret;309 }310 311 if (ctx->reset_gpio) {312 gpiod_set_value_cansleep(ctx->reset_gpio, 0);313 gpiod_set_value_cansleep(ctx->reset_gpio, 1);314 msleep(20);315 gpiod_set_value_cansleep(ctx->reset_gpio, 0);316 msleep(100);317 }318 319 ret = otm8009a_init_sequence(ctx);320 if (ret)321 return ret;322 323 ctx->prepared = true;324 325 return 0;326}327 328static int otm8009a_enable(struct drm_panel *panel)329{330 struct otm8009a *ctx = panel_to_otm8009a(panel);331 332 backlight_enable(ctx->bl_dev);333 334 return 0;335}336 337static int otm8009a_get_modes(struct drm_panel *panel,338 struct drm_connector *connector)339{340 struct drm_display_mode *mode;341 unsigned int num_modes = ARRAY_SIZE(modes);342 unsigned int i;343 344 for (i = 0; i < num_modes; i++) {345 mode = drm_mode_duplicate(connector->dev, &modes[i]);346 if (!mode) {347 dev_err(panel->dev, "failed to add mode %ux%u@%u\n",348 modes[i].hdisplay,349 modes[i].vdisplay,350 drm_mode_vrefresh(&modes[i]));351 return -ENOMEM;352 }353 354 mode->type = DRM_MODE_TYPE_DRIVER;355 356 /* Setting first mode as preferred */357 if (!i)358 mode->type |= DRM_MODE_TYPE_PREFERRED;359 360 drm_mode_set_name(mode);361 drm_mode_probed_add(connector, mode);362 }363 364 connector->display_info.width_mm = mode->width_mm;365 connector->display_info.height_mm = mode->height_mm;366 367 return num_modes;368}369 370static const struct drm_panel_funcs otm8009a_drm_funcs = {371 .disable = otm8009a_disable,372 .unprepare = otm8009a_unprepare,373 .prepare = otm8009a_prepare,374 .enable = otm8009a_enable,375 .get_modes = otm8009a_get_modes,376};377 378/*379 * DSI-BASED BACKLIGHT380 */381 382static int otm8009a_backlight_update_status(struct backlight_device *bd)383{384 struct otm8009a *ctx = bl_get_data(bd);385 u8 data[2];386 387 if (!ctx->prepared) {388 dev_dbg(&bd->dev, "lcd not ready yet for setting its backlight!\n");389 return -ENXIO;390 }391 392 if (bd->props.power <= BACKLIGHT_POWER_REDUCED) {393 /* Power on the backlight with the requested brightness394 * Note We can not use mipi_dsi_dcs_set_display_brightness()395 * as otm8009a driver support only 8-bit brightness (1 param).396 */397 data[0] = MIPI_DCS_SET_DISPLAY_BRIGHTNESS;398 data[1] = bd->props.brightness;399 otm8009a_dcs_write_buf(ctx, data, ARRAY_SIZE(data));400 401 /* set Brightness Control & Backlight on */402 data[1] = 0x24;403 404 } else {405 /* Power off the backlight: set Brightness Control & Bl off */406 data[1] = 0;407 }408 409 /* Update Brightness Control & Backlight */410 data[0] = MIPI_DCS_WRITE_CONTROL_DISPLAY;411 otm8009a_dcs_write_buf(ctx, data, ARRAY_SIZE(data));412 413 return 0;414}415 416static const struct backlight_ops otm8009a_backlight_ops = {417 .update_status = otm8009a_backlight_update_status,418};419 420static int otm8009a_probe(struct mipi_dsi_device *dsi)421{422 struct device *dev = &dsi->dev;423 struct otm8009a *ctx;424 int ret;425 426 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);427 if (!ctx)428 return -ENOMEM;429 430 ctx->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);431 if (IS_ERR(ctx->reset_gpio)) {432 dev_err(dev, "cannot get reset-gpio\n");433 return PTR_ERR(ctx->reset_gpio);434 }435 436 ctx->supply = devm_regulator_get(dev, "power");437 if (IS_ERR(ctx->supply)) {438 ret = PTR_ERR(ctx->supply);439 if (ret != -EPROBE_DEFER)440 dev_err(dev, "failed to request regulator: %d\n", ret);441 return ret;442 }443 444 mipi_dsi_set_drvdata(dsi, ctx);445 446 ctx->dev = dev;447 448 dsi->lanes = 2;449 dsi->format = MIPI_DSI_FMT_RGB888;450 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |451 MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS;452 453 drm_panel_init(&ctx->panel, dev, &otm8009a_drm_funcs,454 DRM_MODE_CONNECTOR_DSI);455 456 ctx->bl_dev = devm_backlight_device_register(dev, dev_name(dev),457 dev, ctx,458 &otm8009a_backlight_ops,459 NULL);460 if (IS_ERR(ctx->bl_dev)) {461 ret = PTR_ERR(ctx->bl_dev);462 dev_err(dev, "failed to register backlight: %d\n", ret);463 return ret;464 }465 466 ctx->bl_dev->props.max_brightness = OTM8009A_BACKLIGHT_MAX;467 ctx->bl_dev->props.brightness = OTM8009A_BACKLIGHT_DEFAULT;468 ctx->bl_dev->props.power = BACKLIGHT_POWER_OFF;469 ctx->bl_dev->props.type = BACKLIGHT_RAW;470 471 drm_panel_add(&ctx->panel);472 473 ret = mipi_dsi_attach(dsi);474 if (ret < 0) {475 dev_err(dev, "mipi_dsi_attach failed. Is host ready?\n");476 drm_panel_remove(&ctx->panel);477 return ret;478 }479 480 return 0;481}482 483static void otm8009a_remove(struct mipi_dsi_device *dsi)484{485 struct otm8009a *ctx = mipi_dsi_get_drvdata(dsi);486 487 mipi_dsi_detach(dsi);488 drm_panel_remove(&ctx->panel);489}490 491static const struct of_device_id orisetech_otm8009a_of_match[] = {492 { .compatible = "orisetech,otm8009a" },493 { }494};495MODULE_DEVICE_TABLE(of, orisetech_otm8009a_of_match);496 497static struct mipi_dsi_driver orisetech_otm8009a_driver = {498 .probe = otm8009a_probe,499 .remove = otm8009a_remove,500 .driver = {501 .name = "panel-orisetech-otm8009a",502 .of_match_table = orisetech_otm8009a_of_match,503 },504};505module_mipi_dsi_driver(orisetech_otm8009a_driver);506 507MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");508MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");509MODULE_DESCRIPTION("DRM driver for Orise Tech OTM8009A MIPI DSI panel");510MODULE_LICENSE("GPL v2");511