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1/* SPDX-License-Identifier: GPL-2.0 */2/* (C) COPYRIGHT 2014-2018 ARM Limited. All rights reserved. */3/* Copyright 2019 Linaro, Ltd., Rob Herring <robh@kernel.org> */4#ifndef __PANFROST_ISSUES_H__5#define __PANFROST_ISSUES_H__6 7#include <linux/bitops.h>8 9#include "panfrost_device.h"10 11/*12 * This is not a complete list of issues, but only the ones the driver needs13 * to care about.14 */15enum panfrost_hw_issue {16 /* Need way to guarantee that all previously-translated memory accesses17 * are committed */18 HW_ISSUE_6367,19 20 /* On job complete with non-done the cache is not flushed */21 HW_ISSUE_6787,22 23 /* Write of PRFCNT_CONFIG_MODE_MANUAL to PRFCNT_CONFIG causes a24 * instrumentation dump if PRFCNT_TILER_EN is enabled */25 HW_ISSUE_8186,26 27 /* TIB: Reports faults from a vtile which has not yet been allocated */28 HW_ISSUE_8245,29 30 /* uTLB deadlock could occur when writing to an invalid page at the31 * same time as access to a valid page in the same uTLB cache line ( ==32 * 4 PTEs == 16K block of mapping) */33 HW_ISSUE_8316,34 35 /* HT: TERMINATE for RUN command ignored if previous LOAD_DESCRIPTOR is36 * still executing */37 HW_ISSUE_8394,38 39 /* CSE: Sends a TERMINATED response for a task that should not be40 * terminated */41 HW_ISSUE_8401,42 43 /* Repeatedly Soft-stopping a job chain consisting of (Vertex Shader,44 * Cache Flush, Tiler) jobs causes DATA_INVALID_FAULT on tiler job. */45 HW_ISSUE_8408,46 47 /* Disable the Pause Buffer in the LS pipe. */48 HW_ISSUE_8443,49 50 /* Change in RMUs in use causes problems related with the core's SDC */51 HW_ISSUE_8987,52 53 /* Compute endpoint has a 4-deep queue of tasks, meaning a soft stop54 * won't complete until all 4 tasks have completed */55 HW_ISSUE_9435,56 57 /* HT: Tiler returns TERMINATED for non-terminated command */58 HW_ISSUE_9510,59 60 /* Occasionally the GPU will issue multiple page faults for the same61 * address before the MMU page table has been read by the GPU */62 HW_ISSUE_9630,63 64 /* RA DCD load request to SDC returns invalid load ignore causing65 * colour buffer mismatch */66 HW_ISSUE_10327,67 68 /* MMU TLB invalidation hazards */69 HW_ISSUE_10649,70 71 /* Missing cache flush in multi core-group configuration */72 HW_ISSUE_10676,73 74 /* Chicken bit on T72X for a hardware workaround in compiler */75 HW_ISSUE_10797,76 77 /* Soft-stopping fragment jobs might fail with TILE_RANGE_FAULT */78 HW_ISSUE_10817,79 80 /* Intermittent missing interrupt on job completion */81 HW_ISSUE_10883,82 83 /* Soft-stopping fragment jobs might fail with TILE_RANGE_ERROR84 * (similar to issue 10817) and can use #10817 workaround */85 HW_ISSUE_10959,86 87 /* Soft-stopped fragment shader job can restart with out-of-bound88 * restart index */89 HW_ISSUE_10969,90 91 /* Race condition can cause tile list corruption */92 HW_ISSUE_11020,93 94 /* Write buffer can cause tile list corruption */95 HW_ISSUE_11024,96 97 /* Pause buffer can cause a fragment job hang */98 HW_ISSUE_11035,99 100 /* Dynamic Core Scaling not supported due to errata */101 HW_ISSUE_11056,102 103 /* Clear encoder state for a hard stopped fragment job which is AFBC104 * encoded by soft resetting the GPU. Only for T76X r0p0, r0p1 and105 * r0p1_50rel0 */106 HW_ISSUE_T76X_3542,107 108 /* Keep tiler module clock on to prevent GPU stall */109 HW_ISSUE_T76X_3953,110 111 /* Must ensure L2 is not transitioning when we reset. Workaround with a112 * busy wait until L2 completes transition; ensure there is a maximum113 * loop count as she may never complete her transition. (On chips114 * without this errata, it's totally okay if L2 transitions.) */115 HW_ISSUE_TMIX_8463,116 117 /* Don't set SC_LS_ATTR_CHECK_DISABLE/SC_LS_ALLOW_ATTR_TYPES */118 GPUCORE_1619,119 120 /* When a hard-stop follows close after a soft-stop, the completion121 * code for the terminated job may be incorrectly set to STOPPED */122 HW_ISSUE_TMIX_8438,123 124 /* "Protected mode" is buggy on Mali-G31 some Bifrost chips, so the125 * kernel must fiddle with L2 caches to prevent data leakage */126 HW_ISSUE_TGOX_R1_1234,127 128 /* Must set SC_VAR_ALGORITHM */129 HW_ISSUE_TTRX_2968_TTRX_3162,130 131 /* Bus fault from occlusion query write may cause future fragment jobs132 * to hang */133 HW_ISSUE_TTRX_3076,134 135 /* Must issue a dummy job before starting real work to prevent hangs */136 HW_ISSUE_TTRX_3485,137 138 HW_ISSUE_END139};140 141#define hw_issues_all (\142 BIT_ULL(HW_ISSUE_9435))143 144#define hw_issues_t600 (\145 BIT_ULL(HW_ISSUE_6367) | \146 BIT_ULL(HW_ISSUE_6787) | \147 BIT_ULL(HW_ISSUE_8408) | \148 BIT_ULL(HW_ISSUE_9510) | \149 BIT_ULL(HW_ISSUE_10649) | \150 BIT_ULL(HW_ISSUE_10676) | \151 BIT_ULL(HW_ISSUE_10883) | \152 BIT_ULL(HW_ISSUE_11020) | \153 BIT_ULL(HW_ISSUE_11035) | \154 BIT_ULL(HW_ISSUE_11056) | \155 BIT_ULL(HW_ISSUE_TMIX_8438))156 157#define hw_issues_t600_r0p0_15dev0 (\158 BIT_ULL(HW_ISSUE_8186) | \159 BIT_ULL(HW_ISSUE_8245) | \160 BIT_ULL(HW_ISSUE_8316) | \161 BIT_ULL(HW_ISSUE_8394) | \162 BIT_ULL(HW_ISSUE_8401) | \163 BIT_ULL(HW_ISSUE_8443) | \164 BIT_ULL(HW_ISSUE_8987) | \165 BIT_ULL(HW_ISSUE_9630) | \166 BIT_ULL(HW_ISSUE_10969) | \167 BIT_ULL(GPUCORE_1619))168 169#define hw_issues_t620 (\170 BIT_ULL(HW_ISSUE_10649) | \171 BIT_ULL(HW_ISSUE_10883) | \172 BIT_ULL(HW_ISSUE_10959) | \173 BIT_ULL(HW_ISSUE_11056) | \174 BIT_ULL(HW_ISSUE_TMIX_8438))175 176#define hw_issues_t620_r0p1 (\177 BIT_ULL(HW_ISSUE_10327) | \178 BIT_ULL(HW_ISSUE_10676) | \179 BIT_ULL(HW_ISSUE_10817) | \180 BIT_ULL(HW_ISSUE_11020) | \181 BIT_ULL(HW_ISSUE_11024) | \182 BIT_ULL(HW_ISSUE_11035))183 184#define hw_issues_t620_r1p0 (\185 BIT_ULL(HW_ISSUE_11020) | \186 BIT_ULL(HW_ISSUE_11024))187 188#define hw_issues_t720 (\189 BIT_ULL(HW_ISSUE_10649) | \190 BIT_ULL(HW_ISSUE_10797) | \191 BIT_ULL(HW_ISSUE_10883) | \192 BIT_ULL(HW_ISSUE_11056) | \193 BIT_ULL(HW_ISSUE_TMIX_8438))194 195#define hw_issues_t760 (\196 BIT_ULL(HW_ISSUE_10883) | \197 BIT_ULL(HW_ISSUE_T76X_3953) | \198 BIT_ULL(HW_ISSUE_TMIX_8438))199 200#define hw_issues_t760_r0p0 (\201 BIT_ULL(HW_ISSUE_11020) | \202 BIT_ULL(HW_ISSUE_11024) | \203 BIT_ULL(HW_ISSUE_T76X_3542))204 205#define hw_issues_t760_r0p1 (\206 BIT_ULL(HW_ISSUE_11020) | \207 BIT_ULL(HW_ISSUE_11024) | \208 BIT_ULL(HW_ISSUE_T76X_3542))209 210#define hw_issues_t760_r0p1_50rel0 (\211 BIT_ULL(HW_ISSUE_T76X_3542))212 213#define hw_issues_t760_r0p2 (\214 BIT_ULL(HW_ISSUE_11020) | \215 BIT_ULL(HW_ISSUE_11024) | \216 BIT_ULL(HW_ISSUE_T76X_3542))217 218#define hw_issues_t760_r0p3 (\219 BIT_ULL(HW_ISSUE_T76X_3542))220 221#define hw_issues_t820 (\222 BIT_ULL(HW_ISSUE_10883) | \223 BIT_ULL(HW_ISSUE_T76X_3953) | \224 BIT_ULL(HW_ISSUE_TMIX_8438))225 226#define hw_issues_t830 (\227 BIT_ULL(HW_ISSUE_10883) | \228 BIT_ULL(HW_ISSUE_T76X_3953) | \229 BIT_ULL(HW_ISSUE_TMIX_8438))230 231#define hw_issues_t860 (\232 BIT_ULL(HW_ISSUE_10883) | \233 BIT_ULL(HW_ISSUE_T76X_3953) | \234 BIT_ULL(HW_ISSUE_TMIX_8438))235 236#define hw_issues_t880 (\237 BIT_ULL(HW_ISSUE_10883) | \238 BIT_ULL(HW_ISSUE_T76X_3953) | \239 BIT_ULL(HW_ISSUE_TMIX_8438))240 241#define hw_issues_g31 0242 243#define hw_issues_g31_r1p0 (\244 BIT_ULL(HW_ISSUE_TGOX_R1_1234))245 246#define hw_issues_g51 0247 248#define hw_issues_g52 0249 250#define hw_issues_g71 (\251 BIT_ULL(HW_ISSUE_TMIX_8463) | \252 BIT_ULL(HW_ISSUE_TMIX_8438))253 254#define hw_issues_g71_r0p0_05dev0 (\255 BIT_ULL(HW_ISSUE_T76X_3953))256 257#define hw_issues_g72 0258 259#define hw_issues_g76 0260 261#define hw_issues_g57 (\262 BIT_ULL(HW_ISSUE_TTRX_2968_TTRX_3162) | \263 BIT_ULL(HW_ISSUE_TTRX_3076))264 265#define hw_issues_g57_r0p0 (\266 BIT_ULL(HW_ISSUE_TTRX_3485))267 268static inline bool panfrost_has_hw_issue(const struct panfrost_device *pfdev,269 enum panfrost_hw_issue issue)270{271 return test_bit(issue, pfdev->features.hw_issues);272}273 274#endif /* __PANFROST_ISSUES_H__ */275