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1/*2 * Copyright 2011 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23#ifndef __BTC_DPM_H__24#define __BTC_DPM_H__25 26#include "radeon.h"27#include "rv770_dpm.h"28 29#define BTC_RLP_UVD_DFLT 2030#define BTC_RMP_UVD_DFLT 5031#define BTC_LHP_UVD_DFLT 5032#define BTC_LMP_UVD_DFLT 2033#define BARTS_MGCGCGTSSMCTRL_DFLT 0x8194400034#define TURKS_MGCGCGTSSMCTRL_DFLT 0x6e94400035#define CAICOS_MGCGCGTSSMCTRL_DFLT 0x4694404036#define BTC_CGULVPARAMETER_DFLT 0x0004003537#define BTC_CGULVCONTROL_DFLT 0x0000145038 39extern u32 btc_valid_sclk[40];40 41void btc_read_arb_registers(struct radeon_device *rdev);42void btc_program_mgcg_hw_sequence(struct radeon_device *rdev,43 const u32 *sequence, u32 count);44void btc_skip_blacklist_clocks(struct radeon_device *rdev,45 const u32 max_sclk, const u32 max_mclk,46 u32 *sclk, u32 *mclk);47void btc_adjust_clock_combinations(struct radeon_device *rdev,48 const struct radeon_clock_and_voltage_limits *max_limits,49 struct rv7xx_pl *pl);50void btc_apply_voltage_dependency_rules(struct radeon_clock_voltage_dependency_table *table,51 u32 clock, u16 max_voltage, u16 *voltage);52void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,53 u32 *max_clock);54void btc_apply_voltage_delta_rules(struct radeon_device *rdev,55 u16 max_vddc, u16 max_vddci,56 u16 *vddc, u16 *vddci);57bool btc_dpm_enabled(struct radeon_device *rdev);58int btc_reset_to_default(struct radeon_device *rdev);59void btc_notify_uvd_to_smc(struct radeon_device *rdev,60 struct radeon_ps *radeon_new_state);61 62#endif63