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1/*2 * Copyright 2013 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23#ifndef __CI_DPM_H__24#define __CI_DPM_H__25 26#include "ppsmc.h"27#include "radeon.h"28 29#define SMU__NUM_SCLK_DPM_STATE 830#define SMU__NUM_MCLK_DPM_LEVELS 631#define SMU__NUM_LCLK_DPM_LEVELS 832#define SMU__NUM_PCIE_DPM_LEVELS 833#include "smu7_discrete.h"34 35#define CISLANDS_MAX_HARDWARE_POWERLEVELS 236 37#define CISLANDS_UNUSED_GPIO_PIN 0x7F38 39struct ci_pl {40 u32 mclk;41 u32 sclk;42 enum radeon_pcie_gen pcie_gen;43 u16 pcie_lane;44};45 46struct ci_ps {47 u16 performance_level_count;48 bool dc_compatible;49 u32 sclk_t;50 struct ci_pl performance_levels[CISLANDS_MAX_HARDWARE_POWERLEVELS];51};52 53struct ci_dpm_level {54 bool enabled;55 u32 value;56 u32 param1;57};58 59#define CISLAND_MAX_DEEPSLEEP_DIVIDER_ID 560#define MAX_REGULAR_DPM_NUMBER 861#define CISLAND_MINIMUM_ENGINE_CLOCK 80062 63struct ci_single_dpm_table {64 u32 count;65 struct ci_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];66};67 68struct ci_dpm_table {69 struct ci_single_dpm_table sclk_table;70 struct ci_single_dpm_table mclk_table;71 struct ci_single_dpm_table pcie_speed_table;72 struct ci_single_dpm_table vddc_table;73 struct ci_single_dpm_table vddci_table;74 struct ci_single_dpm_table mvdd_table;75};76 77struct ci_mc_reg_entry {78 u32 mclk_max;79 u32 mc_data[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];80};81 82struct ci_mc_reg_table {83 u8 last;84 u8 num_entries;85 u16 valid_flag;86 struct ci_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];87 SMU7_Discrete_MCRegisterAddress mc_reg_address[SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE];88};89 90struct ci_ulv_parm {91 bool supported;92 u32 cg_ulv_parameter;93 u32 volt_change_delay;94 struct ci_pl pl;95};96 97#define CISLANDS_MAX_LEAKAGE_COUNT 898 99struct ci_leakage_voltage {100 u16 count;101 u16 leakage_id[CISLANDS_MAX_LEAKAGE_COUNT];102 u16 actual_voltage[CISLANDS_MAX_LEAKAGE_COUNT];103};104 105struct ci_dpm_level_enable_mask {106 u32 uvd_dpm_enable_mask;107 u32 vce_dpm_enable_mask;108 u32 acp_dpm_enable_mask;109 u32 samu_dpm_enable_mask;110 u32 sclk_dpm_enable_mask;111 u32 mclk_dpm_enable_mask;112 u32 pcie_dpm_enable_mask;113};114 115struct ci_vbios_boot_state {116 u16 mvdd_bootup_value;117 u16 vddc_bootup_value;118 u16 vddci_bootup_value;119 u32 sclk_bootup_value;120 u32 mclk_bootup_value;121 u16 pcie_gen_bootup_value;122 u16 pcie_lane_bootup_value;123};124 125struct ci_clock_registers {126 u32 cg_spll_func_cntl;127 u32 cg_spll_func_cntl_2;128 u32 cg_spll_func_cntl_3;129 u32 cg_spll_func_cntl_4;130 u32 cg_spll_spread_spectrum;131 u32 cg_spll_spread_spectrum_2;132 u32 dll_cntl;133 u32 mclk_pwrmgt_cntl;134 u32 mpll_ad_func_cntl;135 u32 mpll_dq_func_cntl;136 u32 mpll_func_cntl;137 u32 mpll_func_cntl_1;138 u32 mpll_func_cntl_2;139 u32 mpll_ss1;140 u32 mpll_ss2;141};142 143struct ci_thermal_temperature_setting {144 s32 temperature_low;145 s32 temperature_high;146 s32 temperature_shutdown;147};148 149struct ci_pcie_perf_range {150 u16 max;151 u16 min;152};153 154enum ci_pt_config_reg_type {155 CISLANDS_CONFIGREG_MMR = 0,156 CISLANDS_CONFIGREG_SMC_IND,157 CISLANDS_CONFIGREG_DIDT_IND,158 CISLANDS_CONFIGREG_CACHE,159 CISLANDS_CONFIGREG_MAX160};161 162#define POWERCONTAINMENT_FEATURE_BAPM 0x00000001163#define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002164#define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004165 166struct ci_pt_config_reg {167 u32 offset;168 u32 mask;169 u32 shift;170 u32 value;171 enum ci_pt_config_reg_type type;172};173 174struct ci_pt_defaults {175 u8 svi_load_line_en;176 u8 svi_load_line_vddc;177 u8 tdc_vddc_throttle_release_limit_perc;178 u8 tdc_mawt;179 u8 tdc_waterfall_ctl;180 u8 dte_ambient_temp_base;181 u32 display_cac;182 u32 bapm_temp_gradient;183 u16 bapmti_r[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];184 u16 bapmti_rc[SMU7_DTE_ITERATIONS * SMU7_DTE_SOURCES * SMU7_DTE_SINKS];185};186 187#define DPMTABLE_OD_UPDATE_SCLK 0x00000001188#define DPMTABLE_OD_UPDATE_MCLK 0x00000002189#define DPMTABLE_UPDATE_SCLK 0x00000004190#define DPMTABLE_UPDATE_MCLK 0x00000008191 192struct ci_power_info {193 struct ci_dpm_table dpm_table;194 u32 voltage_control;195 u32 mvdd_control;196 u32 vddci_control;197 u32 active_auto_throttle_sources;198 struct ci_clock_registers clock_registers;199 u16 acpi_vddc;200 u16 acpi_vddci;201 enum radeon_pcie_gen force_pcie_gen;202 enum radeon_pcie_gen acpi_pcie_gen;203 struct ci_leakage_voltage vddc_leakage;204 struct ci_leakage_voltage vddci_leakage;205 u16 max_vddc_in_pp_table;206 u16 min_vddc_in_pp_table;207 u16 max_vddci_in_pp_table;208 u16 min_vddci_in_pp_table;209 u32 mclk_strobe_mode_threshold;210 u32 mclk_stutter_mode_threshold;211 u32 mclk_edc_enable_threshold;212 u32 mclk_edc_wr_enable_threshold;213 struct ci_vbios_boot_state vbios_boot_state;214 /* smc offsets */215 u32 sram_end;216 u32 dpm_table_start;217 u32 soft_regs_start;218 u32 mc_reg_table_start;219 u32 fan_table_start;220 u32 arb_table_start;221 /* smc tables */222 SMU7_Discrete_DpmTable smc_state_table;223 SMU7_Discrete_MCRegisters smc_mc_reg_table;224 SMU7_Discrete_PmFuses smc_powertune_table;225 /* other stuff */226 struct ci_mc_reg_table mc_reg_table;227 struct atom_voltage_table vddc_voltage_table;228 struct atom_voltage_table vddci_voltage_table;229 struct atom_voltage_table mvdd_voltage_table;230 struct ci_ulv_parm ulv;231 u32 power_containment_features;232 const struct ci_pt_defaults *powertune_defaults;233 u32 dte_tj_offset;234 bool vddc_phase_shed_control;235 struct ci_thermal_temperature_setting thermal_temp_setting;236 struct ci_dpm_level_enable_mask dpm_level_enable_mask;237 u32 need_update_smu7_dpm_table;238 u32 sclk_dpm_key_disabled;239 u32 mclk_dpm_key_disabled;240 u32 pcie_dpm_key_disabled;241 u32 thermal_sclk_dpm_enabled;242 struct ci_pcie_perf_range pcie_gen_performance;243 struct ci_pcie_perf_range pcie_lane_performance;244 struct ci_pcie_perf_range pcie_gen_powersaving;245 struct ci_pcie_perf_range pcie_lane_powersaving;246 u32 activity_target[SMU7_MAX_LEVELS_GRAPHICS];247 u32 mclk_activity_target;248 u32 low_sclk_interrupt_t;249 u32 last_mclk_dpm_enable_mask;250 u32 sys_pcie_mask;251 /* caps */252 bool caps_power_containment;253 bool caps_cac;254 bool caps_sq_ramping;255 bool caps_db_ramping;256 bool caps_td_ramping;257 bool caps_tcp_ramping;258 bool caps_fps;259 bool caps_sclk_ds;260 bool caps_sclk_ss_support;261 bool caps_mclk_ss_support;262 bool caps_uvd_dpm;263 bool caps_vce_dpm;264 bool caps_samu_dpm;265 bool caps_acp_dpm;266 bool caps_automatic_dc_transition;267 bool caps_sclk_throttle_low_notification;268 bool caps_dynamic_ac_timing;269 bool caps_od_fuzzy_fan_control_support;270 /* flags */271 bool thermal_protection;272 bool pcie_performance_request;273 bool dynamic_ss;274 bool dll_default_on;275 bool cac_enabled;276 bool uvd_enabled;277 bool battery_state;278 bool pspp_notify_required;279 bool mem_gddr5;280 bool enable_bapm_feature;281 bool enable_tdc_limit_feature;282 bool enable_pkg_pwr_tracking_feature;283 bool use_pcie_performance_levels;284 bool use_pcie_powersaving_levels;285 bool uvd_power_gated;286 /* driver states */287 struct radeon_ps current_rps;288 struct ci_ps current_ps;289 struct radeon_ps requested_rps;290 struct ci_ps requested_ps;291 /* fan control */292 bool fan_ctrl_is_in_default_mode;293 bool fan_is_controlled_by_smc;294 u32 t_min;295 u32 fan_ctrl_default_mode;296};297 298#define CISLANDS_VOLTAGE_CONTROL_NONE 0x0299#define CISLANDS_VOLTAGE_CONTROL_BY_GPIO 0x1300#define CISLANDS_VOLTAGE_CONTROL_BY_SVID2 0x2301 302#define CISLANDS_Q88_FORMAT_CONVERSION_UNIT 256303 304#define CISLANDS_VRC_DFLT0 0x3FFFC000305#define CISLANDS_VRC_DFLT1 0x000400306#define CISLANDS_VRC_DFLT2 0xC00080307#define CISLANDS_VRC_DFLT3 0xC00200308#define CISLANDS_VRC_DFLT4 0xC01680309#define CISLANDS_VRC_DFLT5 0xC00033310#define CISLANDS_VRC_DFLT6 0xC00033311#define CISLANDS_VRC_DFLT7 0x3FFFC000312 313#define CISLANDS_CGULVPARAMETER_DFLT 0x00040035314#define CISLAND_TARGETACTIVITY_DFLT 30315#define CISLAND_MCLK_TARGETACTIVITY_DFLT 10316 317#define PCIE_PERF_REQ_REMOVE_REGISTRY 0318#define PCIE_PERF_REQ_FORCE_LOWPOWER 1319#define PCIE_PERF_REQ_PECI_GEN1 2320#define PCIE_PERF_REQ_PECI_GEN2 3321#define PCIE_PERF_REQ_PECI_GEN3 4322 323int ci_copy_bytes_to_smc(struct radeon_device *rdev,324 u32 smc_start_address,325 const u8 *src, u32 byte_count, u32 limit);326void ci_start_smc(struct radeon_device *rdev);327void ci_reset_smc(struct radeon_device *rdev);328int ci_program_jump_on_start(struct radeon_device *rdev);329void ci_stop_smc_clock(struct radeon_device *rdev);330void ci_start_smc_clock(struct radeon_device *rdev);331bool ci_is_smc_running(struct radeon_device *rdev);332PPSMC_Result ci_wait_for_smc_inactive(struct radeon_device *rdev);333int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit);334int ci_read_smc_sram_dword(struct radeon_device *rdev,335 u32 smc_address, u32 *value, u32 limit);336int ci_write_smc_sram_dword(struct radeon_device *rdev,337 u32 smc_address, u32 value, u32 limit);338 339#endif340