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1/*2 * Copyright 2012 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: Alex Deucher23 */24#ifndef __CIK_REG_H__25#define __CIK_REG_H__26 27#define CIK_DIDT_IND_INDEX 0xca0028#define CIK_DIDT_IND_DATA 0xca0429 30#define CIK_DC_GPIO_HPD_MASK 0x65b031#define CIK_DC_GPIO_HPD_A 0x65b432#define CIK_DC_GPIO_HPD_EN 0x65b833#define CIK_DC_GPIO_HPD_Y 0x65bc34 35#define CIK_GRPH_CONTROL 0x680436# define CIK_GRPH_DEPTH(x) (((x) & 0x3) << 0)37# define CIK_GRPH_DEPTH_8BPP 038# define CIK_GRPH_DEPTH_16BPP 139# define CIK_GRPH_DEPTH_32BPP 240# define CIK_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2)41# define CIK_ADDR_SURF_2_BANK 042# define CIK_ADDR_SURF_4_BANK 143# define CIK_ADDR_SURF_8_BANK 244# define CIK_ADDR_SURF_16_BANK 345# define CIK_GRPH_Z(x) (((x) & 0x3) << 4)46# define CIK_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)47# define CIK_ADDR_SURF_BANK_WIDTH_1 048# define CIK_ADDR_SURF_BANK_WIDTH_2 149# define CIK_ADDR_SURF_BANK_WIDTH_4 250# define CIK_ADDR_SURF_BANK_WIDTH_8 351# define CIK_GRPH_FORMAT(x) (((x) & 0x7) << 8)52/* 8 BPP */53# define CIK_GRPH_FORMAT_INDEXED 054/* 16 BPP */55# define CIK_GRPH_FORMAT_ARGB1555 056# define CIK_GRPH_FORMAT_ARGB565 157# define CIK_GRPH_FORMAT_ARGB4444 258# define CIK_GRPH_FORMAT_AI88 359# define CIK_GRPH_FORMAT_MONO16 460# define CIK_GRPH_FORMAT_BGRA5551 561/* 32 BPP */62# define CIK_GRPH_FORMAT_ARGB8888 063# define CIK_GRPH_FORMAT_ARGB2101010 164# define CIK_GRPH_FORMAT_32BPP_DIG 265# define CIK_GRPH_FORMAT_8B_ARGB2101010 366# define CIK_GRPH_FORMAT_BGRA1010102 467# define CIK_GRPH_FORMAT_8B_BGRA1010102 568# define CIK_GRPH_FORMAT_RGB111110 669# define CIK_GRPH_FORMAT_BGR101111 770# define CIK_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11)71# define CIK_ADDR_SURF_BANK_HEIGHT_1 072# define CIK_ADDR_SURF_BANK_HEIGHT_2 173# define CIK_ADDR_SURF_BANK_HEIGHT_4 274# define CIK_ADDR_SURF_BANK_HEIGHT_8 375# define CIK_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13)76# define CIK_ADDR_SURF_TILE_SPLIT_64B 077# define CIK_ADDR_SURF_TILE_SPLIT_128B 178# define CIK_ADDR_SURF_TILE_SPLIT_256B 279# define CIK_ADDR_SURF_TILE_SPLIT_512B 380# define CIK_ADDR_SURF_TILE_SPLIT_1KB 481# define CIK_ADDR_SURF_TILE_SPLIT_2KB 582# define CIK_ADDR_SURF_TILE_SPLIT_4KB 683# define CIK_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18)84# define CIK_ADDR_SURF_MACRO_TILE_ASPECT_1 085# define CIK_ADDR_SURF_MACRO_TILE_ASPECT_2 186# define CIK_ADDR_SURF_MACRO_TILE_ASPECT_4 287# define CIK_ADDR_SURF_MACRO_TILE_ASPECT_8 388# define CIK_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)89# define CIK_GRPH_ARRAY_LINEAR_GENERAL 090# define CIK_GRPH_ARRAY_LINEAR_ALIGNED 191# define CIK_GRPH_ARRAY_1D_TILED_THIN1 292# define CIK_GRPH_ARRAY_2D_TILED_THIN1 493# define CIK_GRPH_PIPE_CONFIG(x) (((x) & 0x1f) << 24)94# define CIK_ADDR_SURF_P2 095# define CIK_ADDR_SURF_P4_8x16 496# define CIK_ADDR_SURF_P4_16x16 597# define CIK_ADDR_SURF_P4_16x32 698# define CIK_ADDR_SURF_P4_32x32 799# define CIK_ADDR_SURF_P8_16x16_8x16 8100# define CIK_ADDR_SURF_P8_16x32_8x16 9101# define CIK_ADDR_SURF_P8_32x32_8x16 10102# define CIK_ADDR_SURF_P8_16x32_16x16 11103# define CIK_ADDR_SURF_P8_32x32_16x16 12104# define CIK_ADDR_SURF_P8_32x32_16x32 13105# define CIK_ADDR_SURF_P8_32x64_32x32 14106# define CIK_GRPH_MICRO_TILE_MODE(x) (((x) & 0x7) << 29)107# define CIK_DISPLAY_MICRO_TILING 0108# define CIK_THIN_MICRO_TILING 1109# define CIK_DEPTH_MICRO_TILING 2110# define CIK_ROTATED_MICRO_TILING 4111 112/* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */113#define CIK_CUR_CONTROL 0x6998114# define CIK_CURSOR_EN (1 << 0)115# define CIK_CURSOR_MODE(x) (((x) & 0x3) << 8)116# define CIK_CURSOR_MONO 0117# define CIK_CURSOR_24_1 1118# define CIK_CURSOR_24_8_PRE_MULT 2119# define CIK_CURSOR_24_8_UNPRE_MULT 3120# define CIK_CURSOR_2X_MAGNIFY (1 << 16)121# define CIK_CURSOR_FORCE_MC_ON (1 << 20)122# define CIK_CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24)123# define CIK_CURSOR_URGENT_ALWAYS 0124# define CIK_CURSOR_URGENT_1_8 1125# define CIK_CURSOR_URGENT_1_4 2126# define CIK_CURSOR_URGENT_3_8 3127# define CIK_CURSOR_URGENT_1_2 4128#define CIK_CUR_SURFACE_ADDRESS 0x699c129# define CIK_CUR_SURFACE_ADDRESS_MASK 0xfffff000130#define CIK_CUR_SIZE 0x69a0131#define CIK_CUR_SURFACE_ADDRESS_HIGH 0x69a4132#define CIK_CUR_POSITION 0x69a8133#define CIK_CUR_HOT_SPOT 0x69ac134#define CIK_CUR_COLOR1 0x69b0135#define CIK_CUR_COLOR2 0x69b4136#define CIK_CUR_UPDATE 0x69b8137# define CIK_CURSOR_UPDATE_PENDING (1 << 0)138# define CIK_CURSOR_UPDATE_TAKEN (1 << 1)139# define CIK_CURSOR_UPDATE_LOCK (1 << 16)140# define CIK_CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)141 142#define CIK_ALPHA_CONTROL 0x6af0143# define CIK_CURSOR_ALPHA_BLND_ENA (1 << 1)144 145#define CIK_LB_DATA_FORMAT 0x6b00146# define CIK_INTERLEAVE_EN (1 << 3)147 148#define CIK_LB_DESKTOP_HEIGHT 0x6b0c149 150#define SQ_IND_INDEX 0x8DE0151#define SQ_CMD 0x8DEC152#define SQ_IND_DATA 0x8DE4153 154/*155 * The TCP_WATCHx_xxxx addresses that are shown here are in dwords,156 * and that's why they are multiplied by 4157 */158#define TCP_WATCH0_ADDR_H (0x32A0*4)159#define TCP_WATCH1_ADDR_H (0x32A3*4)160#define TCP_WATCH2_ADDR_H (0x32A6*4)161#define TCP_WATCH3_ADDR_H (0x32A9*4)162#define TCP_WATCH0_ADDR_L (0x32A1*4)163#define TCP_WATCH1_ADDR_L (0x32A4*4)164#define TCP_WATCH2_ADDR_L (0x32A7*4)165#define TCP_WATCH3_ADDR_L (0x32AA*4)166#define TCP_WATCH0_CNTL (0x32A2*4)167#define TCP_WATCH1_CNTL (0x32A5*4)168#define TCP_WATCH2_CNTL (0x32A8*4)169#define TCP_WATCH3_CNTL (0x32AB*4)170 171#define CPC_INT_CNTL 0xC2D0172 173#define CP_HQD_IQ_RPTR 0xC970u174#define SDMA0_RLC0_RB_CNTL 0xD400u175#define SDMA_RB_VMID(x) (x << 24)176#define SDMA0_RLC0_RB_BASE 0xD404u177#define SDMA0_RLC0_RB_BASE_HI 0xD408u178#define SDMA0_RLC0_RB_RPTR 0xD40Cu179#define SDMA0_RLC0_RB_WPTR 0xD410u180#define SDMA0_RLC0_RB_WPTR_POLL_CNTL 0xD414u181#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_HI 0xD418u182#define SDMA0_RLC0_RB_WPTR_POLL_ADDR_LO 0xD41Cu183#define SDMA0_RLC0_RB_RPTR_ADDR_HI 0xD420u184#define SDMA0_RLC0_RB_RPTR_ADDR_LO 0xD424u185#define SDMA0_RLC0_IB_CNTL 0xD428u186#define SDMA0_RLC0_IB_RPTR 0xD42Cu187#define SDMA0_RLC0_IB_OFFSET 0xD430u188#define SDMA0_RLC0_IB_BASE_LO 0xD434u189#define SDMA0_RLC0_IB_BASE_HI 0xD438u190#define SDMA0_RLC0_IB_SIZE 0xD43Cu191#define SDMA0_RLC0_SKIP_CNTL 0xD440u192#define SDMA0_RLC0_CONTEXT_STATUS 0xD444u193#define SDMA_RLC_IDLE (1 << 2)194#define SDMA0_RLC0_DOORBELL 0xD448u195#define SDMA_OFFSET(x) (x << 0)196#define SDMA_DB_ENABLE (1 << 28)197#define SDMA0_RLC0_VIRTUAL_ADDR 0xD49Cu198#define SDMA_ATC (1 << 0)199#define SDMA_VA_PTR32 (1 << 4)200#define SDMA_VA_SHARED_BASE(x) (x << 8)201#define SDMA0_RLC0_APE1_CNTL 0xD4A0u202#define SDMA0_RLC0_DOORBELL_LOG 0xD4A4u203#define SDMA0_RLC0_WATERMARK 0xD4A8u204#define SDMA0_CNTL 0xD010205#define SDMA1_CNTL 0xD810206 207enum {208 MAX_TRAPID = 8, /* 3 bits in the bitfield. */209 MAX_WATCH_ADDRESSES = 4210};211 212enum {213 ADDRESS_WATCH_REG_ADDR_HI = 0,214 ADDRESS_WATCH_REG_ADDR_LO,215 ADDRESS_WATCH_REG_CNTL,216 ADDRESS_WATCH_REG_MAX217};218 219enum { /* not defined in the CI/KV reg file */220 ADDRESS_WATCH_REG_CNTL_ATC_BIT = 0x10000000UL,221 ADDRESS_WATCH_REG_CNTL_DEFAULT_MASK = 0x00FFFFFF,222 ADDRESS_WATCH_REG_ADDLOW_MASK_EXTENSION = 0x03000000,223 /* extend the mask to 26 bits in order to match the low address field */224 ADDRESS_WATCH_REG_ADDLOW_SHIFT = 6,225 ADDRESS_WATCH_REG_ADDHIGH_MASK = 0xFFFF226};227 228union TCP_WATCH_CNTL_BITS {229 struct {230 uint32_t mask:24;231 uint32_t vmid:4;232 uint32_t atc:1;233 uint32_t mode:2;234 uint32_t valid:1;235 } bitfields, bits;236 uint32_t u32All;237 signed int i32All;238 float f32All;239};240 241#endif242