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1/*2 * Copyright 2013 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: Alex Deucher23 */24#include <linux/firmware.h>25 26#include "radeon.h"27#include "radeon_ucode.h"28#include "radeon_asic.h"29#include "radeon_trace.h"30#include "cik.h"31#include "cikd.h"32 33/* sdma */34#define CIK_SDMA_UCODE_SIZE 105035#define CIK_SDMA_UCODE_VERSION 6436 37/*38 * sDMA - System DMA39 * Starting with CIK, the GPU has new asynchronous40 * DMA engines. These engines are used for compute41 * and gfx. There are two DMA engines (SDMA0, SDMA1)42 * and each one supports 1 ring buffer used for gfx43 * and 2 queues used for compute.44 *45 * The programming model is very similar to the CP46 * (ring buffer, IBs, etc.), but sDMA has it's own47 * packet format that is different from the PM4 format48 * used by the CP. sDMA supports copying data, writing49 * embedded data, solid fills, and a number of other50 * things. It also has support for tiling/detiling of51 * buffers.52 */53 54/**55 * cik_sdma_get_rptr - get the current read pointer56 *57 * @rdev: radeon_device pointer58 * @ring: radeon ring pointer59 *60 * Get the current rptr from the hardware (CIK+).61 */62uint32_t cik_sdma_get_rptr(struct radeon_device *rdev,63 struct radeon_ring *ring)64{65 u32 rptr, reg;66 67 if (rdev->wb.enabled) {68 rptr = rdev->wb.wb[ring->rptr_offs/4];69 } else {70 if (ring->idx == R600_RING_TYPE_DMA_INDEX)71 reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET;72 else73 reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET;74 75 rptr = RREG32(reg);76 }77 78 return (rptr & 0x3fffc) >> 2;79}80 81/**82 * cik_sdma_get_wptr - get the current write pointer83 *84 * @rdev: radeon_device pointer85 * @ring: radeon ring pointer86 *87 * Get the current wptr from the hardware (CIK+).88 */89uint32_t cik_sdma_get_wptr(struct radeon_device *rdev,90 struct radeon_ring *ring)91{92 u32 reg;93 94 if (ring->idx == R600_RING_TYPE_DMA_INDEX)95 reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;96 else97 reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;98 99 return (RREG32(reg) & 0x3fffc) >> 2;100}101 102/**103 * cik_sdma_set_wptr - commit the write pointer104 *105 * @rdev: radeon_device pointer106 * @ring: radeon ring pointer107 *108 * Write the wptr back to the hardware (CIK+).109 */110void cik_sdma_set_wptr(struct radeon_device *rdev,111 struct radeon_ring *ring)112{113 u32 reg;114 115 if (ring->idx == R600_RING_TYPE_DMA_INDEX)116 reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;117 else118 reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;119 120 WREG32(reg, (ring->wptr << 2) & 0x3fffc);121 (void)RREG32(reg);122}123 124/**125 * cik_sdma_ring_ib_execute - Schedule an IB on the DMA engine126 *127 * @rdev: radeon_device pointer128 * @ib: IB object to schedule129 *130 * Schedule an IB in the DMA ring (CIK).131 */132void cik_sdma_ring_ib_execute(struct radeon_device *rdev,133 struct radeon_ib *ib)134{135 struct radeon_ring *ring = &rdev->ring[ib->ring];136 u32 extra_bits = (ib->vm ? ib->vm->ids[ib->ring].id : 0) & 0xf;137 138 if (rdev->wb.enabled) {139 u32 next_rptr = ring->wptr + 5;140 while ((next_rptr & 7) != 4)141 next_rptr++;142 next_rptr += 4;143 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));144 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);145 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));146 radeon_ring_write(ring, 1); /* number of DWs to follow */147 radeon_ring_write(ring, next_rptr);148 }149 150 /* IB packet must end on a 8 DW boundary */151 while ((ring->wptr & 7) != 4)152 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));153 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));154 radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */155 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr));156 radeon_ring_write(ring, ib->length_dw);157 158}159 160/**161 * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring162 *163 * @rdev: radeon_device pointer164 * @ridx: radeon ring index165 *166 * Emit an hdp flush packet on the requested DMA ring.167 */168static void cik_sdma_hdp_flush_ring_emit(struct radeon_device *rdev,169 int ridx)170{171 struct radeon_ring *ring = &rdev->ring[ridx];172 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |173 SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */174 u32 ref_and_mask;175 176 if (ridx == R600_RING_TYPE_DMA_INDEX)177 ref_and_mask = SDMA0;178 else179 ref_and_mask = SDMA1;180 181 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));182 radeon_ring_write(ring, GPU_HDP_FLUSH_DONE);183 radeon_ring_write(ring, GPU_HDP_FLUSH_REQ);184 radeon_ring_write(ring, ref_and_mask); /* reference */185 radeon_ring_write(ring, ref_and_mask); /* mask */186 radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */187}188 189/**190 * cik_sdma_fence_ring_emit - emit a fence on the DMA ring191 *192 * @rdev: radeon_device pointer193 * @fence: radeon fence object194 *195 * Add a DMA fence packet to the ring to write196 * the fence seq number and DMA trap packet to generate197 * an interrupt if needed (CIK).198 */199void cik_sdma_fence_ring_emit(struct radeon_device *rdev,200 struct radeon_fence *fence)201{202 struct radeon_ring *ring = &rdev->ring[fence->ring];203 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;204 205 /* write the fence */206 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));207 radeon_ring_write(ring, lower_32_bits(addr));208 radeon_ring_write(ring, upper_32_bits(addr));209 radeon_ring_write(ring, fence->seq);210 /* generate an interrupt */211 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));212 /* flush HDP */213 cik_sdma_hdp_flush_ring_emit(rdev, fence->ring);214}215 216/**217 * cik_sdma_semaphore_ring_emit - emit a semaphore on the dma ring218 *219 * @rdev: radeon_device pointer220 * @ring: radeon_ring structure holding ring information221 * @semaphore: radeon semaphore object222 * @emit_wait: wait or signal semaphore223 *224 * Add a DMA semaphore packet to the ring wait on or signal225 * other rings (CIK).226 */227bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,228 struct radeon_ring *ring,229 struct radeon_semaphore *semaphore,230 bool emit_wait)231{232 u64 addr = semaphore->gpu_addr;233 u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S;234 235 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits));236 radeon_ring_write(ring, addr & 0xfffffff8);237 radeon_ring_write(ring, upper_32_bits(addr));238 239 return true;240}241 242/**243 * cik_sdma_gfx_stop - stop the gfx async dma engines244 *245 * @rdev: radeon_device pointer246 *247 * Stop the gfx async dma ring buffers (CIK).248 */249static void cik_sdma_gfx_stop(struct radeon_device *rdev)250{251 u32 rb_cntl, reg_offset;252 int i;253 254 if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||255 (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))256 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);257 258 for (i = 0; i < 2; i++) {259 if (i == 0)260 reg_offset = SDMA0_REGISTER_OFFSET;261 else262 reg_offset = SDMA1_REGISTER_OFFSET;263 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset);264 rb_cntl &= ~SDMA_RB_ENABLE;265 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);266 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0);267 }268 rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false;269 rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false;270 271 /* FIXME use something else than big hammer but after few days can not272 * seem to find good combination so reset SDMA blocks as it seems we273 * do not shut them down properly. This fix hibernation and does not274 * affect suspend to ram.275 */276 WREG32(SRBM_SOFT_RESET, SOFT_RESET_SDMA | SOFT_RESET_SDMA1);277 (void)RREG32(SRBM_SOFT_RESET);278 udelay(50);279 WREG32(SRBM_SOFT_RESET, 0);280 (void)RREG32(SRBM_SOFT_RESET);281}282 283/**284 * cik_sdma_rlc_stop - stop the compute async dma engines285 *286 * @rdev: radeon_device pointer287 *288 * Stop the compute async dma queues (CIK).289 */290static void cik_sdma_rlc_stop(struct radeon_device *rdev)291{292 /* XXX todo */293}294 295/**296 * cik_sdma_ctx_switch_enable - enable/disable sdma engine preemption297 *298 * @rdev: radeon_device pointer299 * @enable: enable/disable preemption.300 *301 * Halt or unhalt the async dma engines (CIK).302 */303static void cik_sdma_ctx_switch_enable(struct radeon_device *rdev, bool enable)304{305 uint32_t reg_offset, value;306 int i;307 308 for (i = 0; i < 2; i++) {309 if (i == 0)310 reg_offset = SDMA0_REGISTER_OFFSET;311 else312 reg_offset = SDMA1_REGISTER_OFFSET;313 value = RREG32(SDMA0_CNTL + reg_offset);314 if (enable)315 value |= AUTO_CTXSW_ENABLE;316 else317 value &= ~AUTO_CTXSW_ENABLE;318 WREG32(SDMA0_CNTL + reg_offset, value);319 }320}321 322/**323 * cik_sdma_enable - stop the async dma engines324 *325 * @rdev: radeon_device pointer326 * @enable: enable/disable the DMA MEs.327 *328 * Halt or unhalt the async dma engines (CIK).329 */330void cik_sdma_enable(struct radeon_device *rdev, bool enable)331{332 u32 me_cntl, reg_offset;333 int i;334 335 if (!enable) {336 cik_sdma_gfx_stop(rdev);337 cik_sdma_rlc_stop(rdev);338 }339 340 for (i = 0; i < 2; i++) {341 if (i == 0)342 reg_offset = SDMA0_REGISTER_OFFSET;343 else344 reg_offset = SDMA1_REGISTER_OFFSET;345 me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset);346 if (enable)347 me_cntl &= ~SDMA_HALT;348 else349 me_cntl |= SDMA_HALT;350 WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl);351 }352 353 cik_sdma_ctx_switch_enable(rdev, enable);354}355 356/**357 * cik_sdma_gfx_resume - setup and start the async dma engines358 *359 * @rdev: radeon_device pointer360 *361 * Set up the gfx DMA ring buffers and enable them (CIK).362 * Returns 0 for success, error for failure.363 */364static int cik_sdma_gfx_resume(struct radeon_device *rdev)365{366 struct radeon_ring *ring;367 u32 rb_cntl, ib_cntl;368 u32 rb_bufsz;369 u32 reg_offset, wb_offset;370 int i, r;371 372 for (i = 0; i < 2; i++) {373 if (i == 0) {374 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];375 reg_offset = SDMA0_REGISTER_OFFSET;376 wb_offset = R600_WB_DMA_RPTR_OFFSET;377 } else {378 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];379 reg_offset = SDMA1_REGISTER_OFFSET;380 wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET;381 }382 383 WREG32(SDMA0_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);384 WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);385 386 /* Set ring buffer size in dwords */387 rb_bufsz = order_base_2(ring->ring_size / 4);388 rb_cntl = rb_bufsz << 1;389#ifdef __BIG_ENDIAN390 rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE;391#endif392 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);393 394 /* Initialize the ring buffer's read and write pointers */395 WREG32(SDMA0_GFX_RB_RPTR + reg_offset, 0);396 WREG32(SDMA0_GFX_RB_WPTR + reg_offset, 0);397 398 /* set the wb address whether it's enabled or not */399 WREG32(SDMA0_GFX_RB_RPTR_ADDR_HI + reg_offset,400 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);401 WREG32(SDMA0_GFX_RB_RPTR_ADDR_LO + reg_offset,402 ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));403 404 if (rdev->wb.enabled)405 rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE;406 407 WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8);408 WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40);409 410 ring->wptr = 0;411 WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2);412 413 /* enable DMA RB */414 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE);415 416 ib_cntl = SDMA_IB_ENABLE;417#ifdef __BIG_ENDIAN418 ib_cntl |= SDMA_IB_SWAP_ENABLE;419#endif420 /* enable DMA IBs */421 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl);422 423 ring->ready = true;424 425 r = radeon_ring_test(rdev, ring->idx, ring);426 if (r) {427 ring->ready = false;428 return r;429 }430 }431 432 if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||433 (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))434 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);435 436 return 0;437}438 439/**440 * cik_sdma_rlc_resume - setup and start the async dma engines441 *442 * @rdev: radeon_device pointer443 *444 * Set up the compute DMA queues and enable them (CIK).445 * Returns 0 for success, error for failure.446 */447static int cik_sdma_rlc_resume(struct radeon_device *rdev)448{449 /* XXX todo */450 return 0;451}452 453/**454 * cik_sdma_load_microcode - load the sDMA ME ucode455 *456 * @rdev: radeon_device pointer457 *458 * Loads the sDMA0/1 ucode.459 * Returns 0 for success, -EINVAL if the ucode is not available.460 */461static int cik_sdma_load_microcode(struct radeon_device *rdev)462{463 int i;464 465 if (!rdev->sdma_fw)466 return -EINVAL;467 468 /* halt the MEs */469 cik_sdma_enable(rdev, false);470 471 if (rdev->new_fw) {472 const struct sdma_firmware_header_v1_0 *hdr =473 (const struct sdma_firmware_header_v1_0 *)rdev->sdma_fw->data;474 const __le32 *fw_data;475 u32 fw_size;476 477 radeon_ucode_print_sdma_hdr(&hdr->header);478 479 /* sdma0 */480 fw_data = (const __le32 *)481 (rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));482 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;483 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);484 for (i = 0; i < fw_size; i++)485 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, le32_to_cpup(fw_data++));486 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);487 488 /* sdma1 */489 fw_data = (const __le32 *)490 (rdev->sdma_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));491 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;492 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);493 for (i = 0; i < fw_size; i++)494 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, le32_to_cpup(fw_data++));495 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);496 } else {497 const __be32 *fw_data;498 499 /* sdma0 */500 fw_data = (const __be32 *)rdev->sdma_fw->data;501 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);502 for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++)503 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++));504 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);505 506 /* sdma1 */507 fw_data = (const __be32 *)rdev->sdma_fw->data;508 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);509 for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++)510 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++));511 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);512 }513 514 WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);515 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);516 return 0;517}518 519/**520 * cik_sdma_resume - setup and start the async dma engines521 *522 * @rdev: radeon_device pointer523 *524 * Set up the DMA engines and enable them (CIK).525 * Returns 0 for success, error for failure.526 */527int cik_sdma_resume(struct radeon_device *rdev)528{529 int r;530 531 r = cik_sdma_load_microcode(rdev);532 if (r)533 return r;534 535 /* unhalt the MEs */536 cik_sdma_enable(rdev, true);537 538 /* start the gfx rings and rlc compute queues */539 r = cik_sdma_gfx_resume(rdev);540 if (r)541 return r;542 r = cik_sdma_rlc_resume(rdev);543 if (r)544 return r;545 546 return 0;547}548 549/**550 * cik_sdma_fini - tear down the async dma engines551 *552 * @rdev: radeon_device pointer553 *554 * Stop the async dma engines and free the rings (CIK).555 */556void cik_sdma_fini(struct radeon_device *rdev)557{558 /* halt the MEs */559 cik_sdma_enable(rdev, false);560 radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);561 radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);562 /* XXX - compute dma queue tear down */563}564 565/**566 * cik_copy_dma - copy pages using the DMA engine567 *568 * @rdev: radeon_device pointer569 * @src_offset: src GPU address570 * @dst_offset: dst GPU address571 * @num_gpu_pages: number of GPU pages to xfer572 * @resv: reservation object to sync to573 *574 * Copy GPU paging using the DMA engine (CIK).575 * Used by the radeon ttm implementation to move pages if576 * registered as the asic copy callback.577 */578struct radeon_fence *cik_copy_dma(struct radeon_device *rdev,579 uint64_t src_offset, uint64_t dst_offset,580 unsigned num_gpu_pages,581 struct dma_resv *resv)582{583 struct radeon_fence *fence;584 struct radeon_sync sync;585 int ring_index = rdev->asic->copy.dma_ring_index;586 struct radeon_ring *ring = &rdev->ring[ring_index];587 u32 size_in_bytes, cur_size_in_bytes;588 int i, num_loops;589 int r = 0;590 591 radeon_sync_create(&sync);592 593 size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);594 num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);595 r = radeon_ring_lock(rdev, ring, num_loops * 7 + 14);596 if (r) {597 DRM_ERROR("radeon: moving bo (%d).\n", r);598 radeon_sync_free(rdev, &sync, NULL);599 return ERR_PTR(r);600 }601 602 radeon_sync_resv(rdev, &sync, resv, false);603 radeon_sync_rings(rdev, &sync, ring->idx);604 605 for (i = 0; i < num_loops; i++) {606 cur_size_in_bytes = size_in_bytes;607 if (cur_size_in_bytes > 0x1fffff)608 cur_size_in_bytes = 0x1fffff;609 size_in_bytes -= cur_size_in_bytes;610 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0));611 radeon_ring_write(ring, cur_size_in_bytes);612 radeon_ring_write(ring, 0); /* src/dst endian swap */613 radeon_ring_write(ring, lower_32_bits(src_offset));614 radeon_ring_write(ring, upper_32_bits(src_offset));615 radeon_ring_write(ring, lower_32_bits(dst_offset));616 radeon_ring_write(ring, upper_32_bits(dst_offset));617 src_offset += cur_size_in_bytes;618 dst_offset += cur_size_in_bytes;619 }620 621 r = radeon_fence_emit(rdev, &fence, ring->idx);622 if (r) {623 radeon_ring_unlock_undo(rdev, ring);624 radeon_sync_free(rdev, &sync, NULL);625 return ERR_PTR(r);626 }627 628 radeon_ring_unlock_commit(rdev, ring, false);629 radeon_sync_free(rdev, &sync, fence);630 631 return fence;632}633 634/**635 * cik_sdma_ring_test - simple async dma engine test636 *637 * @rdev: radeon_device pointer638 * @ring: radeon_ring structure holding ring information639 *640 * Test the DMA engine by writing using it to write an641 * value to memory. (CIK).642 * Returns 0 for success, error for failure.643 */644int cik_sdma_ring_test(struct radeon_device *rdev,645 struct radeon_ring *ring)646{647 unsigned i;648 int r;649 unsigned index;650 u32 tmp;651 u64 gpu_addr;652 653 if (ring->idx == R600_RING_TYPE_DMA_INDEX)654 index = R600_WB_DMA_RING_TEST_OFFSET;655 else656 index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;657 658 gpu_addr = rdev->wb.gpu_addr + index;659 660 tmp = 0xCAFEDEAD;661 rdev->wb.wb[index/4] = cpu_to_le32(tmp);662 663 r = radeon_ring_lock(rdev, ring, 5);664 if (r) {665 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);666 return r;667 }668 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));669 radeon_ring_write(ring, lower_32_bits(gpu_addr));670 radeon_ring_write(ring, upper_32_bits(gpu_addr));671 radeon_ring_write(ring, 1); /* number of DWs to follow */672 radeon_ring_write(ring, 0xDEADBEEF);673 radeon_ring_unlock_commit(rdev, ring, false);674 675 for (i = 0; i < rdev->usec_timeout; i++) {676 tmp = le32_to_cpu(rdev->wb.wb[index/4]);677 if (tmp == 0xDEADBEEF)678 break;679 udelay(1);680 }681 682 if (i < rdev->usec_timeout) {683 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);684 } else {685 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",686 ring->idx, tmp);687 r = -EINVAL;688 }689 return r;690}691 692/**693 * cik_sdma_ib_test - test an IB on the DMA engine694 *695 * @rdev: radeon_device pointer696 * @ring: radeon_ring structure holding ring information697 *698 * Test a simple IB in the DMA ring (CIK).699 * Returns 0 on success, error on failure.700 */701int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)702{703 struct radeon_ib ib;704 unsigned i;705 unsigned index;706 int r;707 u32 tmp = 0;708 u64 gpu_addr;709 710 if (ring->idx == R600_RING_TYPE_DMA_INDEX)711 index = R600_WB_DMA_RING_TEST_OFFSET;712 else713 index = CAYMAN_WB_DMA1_RING_TEST_OFFSET;714 715 gpu_addr = rdev->wb.gpu_addr + index;716 717 tmp = 0xCAFEDEAD;718 rdev->wb.wb[index/4] = cpu_to_le32(tmp);719 720 r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);721 if (r) {722 DRM_ERROR("radeon: failed to get ib (%d).\n", r);723 return r;724 }725 726 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);727 ib.ptr[1] = lower_32_bits(gpu_addr);728 ib.ptr[2] = upper_32_bits(gpu_addr);729 ib.ptr[3] = 1;730 ib.ptr[4] = 0xDEADBEEF;731 ib.length_dw = 5;732 733 r = radeon_ib_schedule(rdev, &ib, NULL, false);734 if (r) {735 radeon_ib_free(rdev, &ib);736 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);737 return r;738 }739 r = radeon_fence_wait_timeout(ib.fence, false, usecs_to_jiffies(740 RADEON_USEC_IB_TEST_TIMEOUT));741 if (r < 0) {742 DRM_ERROR("radeon: fence wait failed (%d).\n", r);743 return r;744 } else if (r == 0) {745 DRM_ERROR("radeon: fence wait timed out.\n");746 return -ETIMEDOUT;747 }748 r = 0;749 for (i = 0; i < rdev->usec_timeout; i++) {750 tmp = le32_to_cpu(rdev->wb.wb[index/4]);751 if (tmp == 0xDEADBEEF)752 break;753 udelay(1);754 }755 if (i < rdev->usec_timeout) {756 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);757 } else {758 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);759 r = -EINVAL;760 }761 radeon_ib_free(rdev, &ib);762 return r;763}764 765/**766 * cik_sdma_is_lockup - Check if the DMA engine is locked up767 *768 * @rdev: radeon_device pointer769 * @ring: radeon_ring structure holding ring information770 *771 * Check if the async DMA engine is locked up (CIK).772 * Returns true if the engine appears to be locked up, false if not.773 */774bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)775{776 u32 reset_mask = cik_gpu_check_soft_reset(rdev);777 u32 mask;778 779 if (ring->idx == R600_RING_TYPE_DMA_INDEX)780 mask = RADEON_RESET_DMA;781 else782 mask = RADEON_RESET_DMA1;783 784 if (!(reset_mask & mask)) {785 radeon_ring_lockup_update(rdev, ring);786 return false;787 }788 return radeon_ring_test_lockup(rdev, ring);789}790 791/**792 * cik_sdma_vm_copy_pages - update PTEs by copying them from the GART793 *794 * @rdev: radeon_device pointer795 * @ib: indirect buffer to fill with commands796 * @pe: addr of the page entry797 * @src: src addr to copy from798 * @count: number of page entries to update799 *800 * Update PTEs by copying them from the GART using sDMA (CIK).801 */802void cik_sdma_vm_copy_pages(struct radeon_device *rdev,803 struct radeon_ib *ib,804 uint64_t pe, uint64_t src,805 unsigned count)806{807 while (count) {808 unsigned bytes = count * 8;809 if (bytes > 0x1FFFF8)810 bytes = 0x1FFFF8;811 812 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY,813 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);814 ib->ptr[ib->length_dw++] = bytes;815 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */816 ib->ptr[ib->length_dw++] = lower_32_bits(src);817 ib->ptr[ib->length_dw++] = upper_32_bits(src);818 ib->ptr[ib->length_dw++] = lower_32_bits(pe);819 ib->ptr[ib->length_dw++] = upper_32_bits(pe);820 821 pe += bytes;822 src += bytes;823 count -= bytes / 8;824 }825}826 827/**828 * cik_sdma_vm_write_pages - update PTEs by writing them manually829 *830 * @rdev: radeon_device pointer831 * @ib: indirect buffer to fill with commands832 * @pe: addr of the page entry833 * @addr: dst addr to write into pe834 * @count: number of page entries to update835 * @incr: increase next addr by incr bytes836 * @flags: access flags837 *838 * Update PTEs by writing them manually using sDMA (CIK).839 */840void cik_sdma_vm_write_pages(struct radeon_device *rdev,841 struct radeon_ib *ib,842 uint64_t pe,843 uint64_t addr, unsigned count,844 uint32_t incr, uint32_t flags)845{846 uint64_t value;847 unsigned ndw;848 849 while (count) {850 ndw = count * 2;851 if (ndw > 0xFFFFE)852 ndw = 0xFFFFE;853 854 /* for non-physically contiguous pages (system) */855 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_WRITE,856 SDMA_WRITE_SUB_OPCODE_LINEAR, 0);857 ib->ptr[ib->length_dw++] = pe;858 ib->ptr[ib->length_dw++] = upper_32_bits(pe);859 ib->ptr[ib->length_dw++] = ndw;860 for (; ndw > 0; ndw -= 2, --count, pe += 8) {861 if (flags & R600_PTE_SYSTEM) {862 value = radeon_vm_map_gart(rdev, addr);863 } else if (flags & R600_PTE_VALID) {864 value = addr;865 } else {866 value = 0;867 }868 addr += incr;869 value |= flags;870 ib->ptr[ib->length_dw++] = value;871 ib->ptr[ib->length_dw++] = upper_32_bits(value);872 }873 }874}875 876/**877 * cik_sdma_vm_set_pages - update the page tables using sDMA878 *879 * @rdev: radeon_device pointer880 * @ib: indirect buffer to fill with commands881 * @pe: addr of the page entry882 * @addr: dst addr to write into pe883 * @count: number of page entries to update884 * @incr: increase next addr by incr bytes885 * @flags: access flags886 *887 * Update the page tables using sDMA (CIK).888 */889void cik_sdma_vm_set_pages(struct radeon_device *rdev,890 struct radeon_ib *ib,891 uint64_t pe,892 uint64_t addr, unsigned count,893 uint32_t incr, uint32_t flags)894{895 uint64_t value;896 unsigned ndw;897 898 while (count) {899 ndw = count;900 if (ndw > 0x7FFFF)901 ndw = 0x7FFFF;902 903 if (flags & R600_PTE_VALID)904 value = addr;905 else906 value = 0;907 908 /* for physically contiguous pages (vram) */909 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_GENERATE_PTE_PDE, 0, 0);910 ib->ptr[ib->length_dw++] = pe; /* dst addr */911 ib->ptr[ib->length_dw++] = upper_32_bits(pe);912 ib->ptr[ib->length_dw++] = flags; /* mask */913 ib->ptr[ib->length_dw++] = 0;914 ib->ptr[ib->length_dw++] = value; /* value */915 ib->ptr[ib->length_dw++] = upper_32_bits(value);916 ib->ptr[ib->length_dw++] = incr; /* increment size */917 ib->ptr[ib->length_dw++] = 0;918 ib->ptr[ib->length_dw++] = ndw; /* number of entries */919 920 pe += ndw * 8;921 addr += ndw * incr;922 count -= ndw;923 }924}925 926/**927 * cik_sdma_vm_pad_ib - pad the IB to the required number of dw928 *929 * @ib: indirect buffer to fill with padding930 *931 */932void cik_sdma_vm_pad_ib(struct radeon_ib *ib)933{934 while (ib->length_dw & 0x7)935 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0);936}937 938/*939 * cik_dma_vm_flush - cik vm flush using sDMA940 *941 * Update the page table base and flush the VM TLB942 * using sDMA (CIK).943 */944void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,945 unsigned vm_id, uint64_t pd_addr)946{947 u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |948 SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */949 950 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));951 if (vm_id < 8) {952 radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2);953 } else {954 radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2);955 }956 radeon_ring_write(ring, pd_addr >> 12);957 958 /* update SH_MEM_* regs */959 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));960 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);961 radeon_ring_write(ring, VMID(vm_id));962 963 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));964 radeon_ring_write(ring, SH_MEM_BASES >> 2);965 radeon_ring_write(ring, 0);966 967 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));968 radeon_ring_write(ring, SH_MEM_CONFIG >> 2);969 radeon_ring_write(ring, 0);970 971 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));972 radeon_ring_write(ring, SH_MEM_APE1_BASE >> 2);973 radeon_ring_write(ring, 1);974 975 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));976 radeon_ring_write(ring, SH_MEM_APE1_LIMIT >> 2);977 radeon_ring_write(ring, 0);978 979 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));980 radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);981 radeon_ring_write(ring, VMID(0));982 983 /* flush HDP */984 cik_sdma_hdp_flush_ring_emit(rdev, ring->idx);985 986 /* flush TLB */987 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));988 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);989 radeon_ring_write(ring, 1 << vm_id);990 991 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));992 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);993 radeon_ring_write(ring, 0);994 radeon_ring_write(ring, 0); /* reference */995 radeon_ring_write(ring, 0); /* mask */996 radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */997}998 999