2173 lines · c
1/*2 * Copyright 2012 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: Alex Deucher23 */24#ifndef CIK_H25#define CIK_H26 27#define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x1201000128#define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x1201100329 30#define CIK_RB_BITMAP_WIDTH_PER_SH 231#define HAWAII_RB_BITMAP_WIDTH_PER_SH 432 33/* DIDT IND registers */34#define DIDT_SQ_CTRL0 0x035# define DIDT_CTRL_EN (1 << 0)36#define DIDT_DB_CTRL0 0x2037#define DIDT_TD_CTRL0 0x4038#define DIDT_TCP_CTRL0 0x6039 40/* SMC IND registers */41#define DPM_TABLE_475 0x3F76842# define SamuBootLevel(x) ((x) << 0)43# define SamuBootLevel_MASK 0x000000ff44# define SamuBootLevel_SHIFT 045# define AcpBootLevel(x) ((x) << 8)46# define AcpBootLevel_MASK 0x0000ff0047# define AcpBootLevel_SHIFT 848# define VceBootLevel(x) ((x) << 16)49# define VceBootLevel_MASK 0x00ff000050# define VceBootLevel_SHIFT 1651# define UvdBootLevel(x) ((x) << 24)52# define UvdBootLevel_MASK 0xff00000053# define UvdBootLevel_SHIFT 2454 55#define FIRMWARE_FLAGS 0x3F80056# define INTERRUPTS_ENABLED (1 << 0)57 58#define NB_DPM_CONFIG_1 0x3F9E859# define Dpm0PgNbPsLo(x) ((x) << 0)60# define Dpm0PgNbPsLo_MASK 0x000000ff61# define Dpm0PgNbPsLo_SHIFT 062# define Dpm0PgNbPsHi(x) ((x) << 8)63# define Dpm0PgNbPsHi_MASK 0x0000ff0064# define Dpm0PgNbPsHi_SHIFT 865# define DpmXNbPsLo(x) ((x) << 16)66# define DpmXNbPsLo_MASK 0x00ff000067# define DpmXNbPsLo_SHIFT 1668# define DpmXNbPsHi(x) ((x) << 24)69# define DpmXNbPsHi_MASK 0xff00000070# define DpmXNbPsHi_SHIFT 2471 72#define SMC_SYSCON_RESET_CNTL 0x8000000073# define RST_REG (1 << 0)74#define SMC_SYSCON_CLOCK_CNTL_0 0x8000000475# define CK_DISABLE (1 << 0)76# define CKEN (1 << 24)77 78#define SMC_SYSCON_MISC_CNTL 0x8000001079 80#define SMC_SYSCON_MSG_ARG_0 0x8000006881 82#define SMC_PC_C 0x8000037083 84#define SMC_SCRATCH9 0x8000042485 86#define RCU_UC_EVENTS 0xC000000487# define BOOT_SEQ_DONE (1 << 7)88 89#define GENERAL_PWRMGT 0xC020000090# define GLOBAL_PWRMGT_EN (1 << 0)91# define STATIC_PM_EN (1 << 1)92# define THERMAL_PROTECTION_DIS (1 << 2)93# define THERMAL_PROTECTION_TYPE (1 << 3)94# define SW_SMIO_INDEX(x) ((x) << 6)95# define SW_SMIO_INDEX_MASK (1 << 6)96# define SW_SMIO_INDEX_SHIFT 697# define VOLT_PWRMGT_EN (1 << 10)98# define GPU_COUNTER_CLK (1 << 15)99# define DYN_SPREAD_SPECTRUM_EN (1 << 23)100 101#define CNB_PWRMGT_CNTL 0xC0200004102# define GNB_SLOW_MODE(x) ((x) << 0)103# define GNB_SLOW_MODE_MASK (3 << 0)104# define GNB_SLOW_MODE_SHIFT 0105# define GNB_SLOW (1 << 2)106# define FORCE_NB_PS1 (1 << 3)107# define DPM_ENABLED (1 << 4)108 109#define SCLK_PWRMGT_CNTL 0xC0200008110# define SCLK_PWRMGT_OFF (1 << 0)111# define RESET_BUSY_CNT (1 << 4)112# define RESET_SCLK_CNT (1 << 5)113# define DYNAMIC_PM_EN (1 << 21)114 115#define TARGET_AND_CURRENT_PROFILE_INDEX 0xC0200014116# define CURRENT_STATE_MASK (0xf << 4)117# define CURRENT_STATE_SHIFT 4118# define CURR_MCLK_INDEX_MASK (0xf << 8)119# define CURR_MCLK_INDEX_SHIFT 8120# define CURR_SCLK_INDEX_MASK (0x1f << 16)121# define CURR_SCLK_INDEX_SHIFT 16122 123#define CG_SSP 0xC0200044124# define SST(x) ((x) << 0)125# define SST_MASK (0xffff << 0)126# define SSTU(x) ((x) << 16)127# define SSTU_MASK (0xf << 16)128 129#define CG_DISPLAY_GAP_CNTL 0xC0200060130# define DISP_GAP(x) ((x) << 0)131# define DISP_GAP_MASK (3 << 0)132# define VBI_TIMER_COUNT(x) ((x) << 4)133# define VBI_TIMER_COUNT_MASK (0x3fff << 4)134# define VBI_TIMER_UNIT(x) ((x) << 20)135# define VBI_TIMER_UNIT_MASK (7 << 20)136# define DISP_GAP_MCHG(x) ((x) << 24)137# define DISP_GAP_MCHG_MASK (3 << 24)138 139#define SMU_VOLTAGE_STATUS 0xC0200094140# define SMU_VOLTAGE_CURRENT_LEVEL_MASK (0xff << 1)141# define SMU_VOLTAGE_CURRENT_LEVEL_SHIFT 1142 143#define TARGET_AND_CURRENT_PROFILE_INDEX_1 0xC02000F0144# define CURR_PCIE_INDEX_MASK (0xf << 24)145# define CURR_PCIE_INDEX_SHIFT 24146 147#define CG_ULV_PARAMETER 0xC0200158148 149#define CG_FTV_0 0xC02001A8150#define CG_FTV_1 0xC02001AC151#define CG_FTV_2 0xC02001B0152#define CG_FTV_3 0xC02001B4153#define CG_FTV_4 0xC02001B8154#define CG_FTV_5 0xC02001BC155#define CG_FTV_6 0xC02001C0156#define CG_FTV_7 0xC02001C4157 158#define CG_DISPLAY_GAP_CNTL2 0xC0200230159 160#define LCAC_SX0_OVR_SEL 0xC0400D04161#define LCAC_SX0_OVR_VAL 0xC0400D08162 163#define LCAC_MC0_CNTL 0xC0400D30164#define LCAC_MC0_OVR_SEL 0xC0400D34165#define LCAC_MC0_OVR_VAL 0xC0400D38166#define LCAC_MC1_CNTL 0xC0400D3C167#define LCAC_MC1_OVR_SEL 0xC0400D40168#define LCAC_MC1_OVR_VAL 0xC0400D44169 170#define LCAC_MC2_OVR_SEL 0xC0400D4C171#define LCAC_MC2_OVR_VAL 0xC0400D50172 173#define LCAC_MC3_OVR_SEL 0xC0400D58174#define LCAC_MC3_OVR_VAL 0xC0400D5C175 176#define LCAC_CPL_CNTL 0xC0400D80177#define LCAC_CPL_OVR_SEL 0xC0400D84178#define LCAC_CPL_OVR_VAL 0xC0400D88179 180/* dGPU */181#define CG_THERMAL_CTRL 0xC0300004182#define DPM_EVENT_SRC(x) ((x) << 0)183#define DPM_EVENT_SRC_MASK (7 << 0)184#define DIG_THERM_DPM(x) ((x) << 14)185#define DIG_THERM_DPM_MASK 0x003FC000186#define DIG_THERM_DPM_SHIFT 14187#define CG_THERMAL_STATUS 0xC0300008188#define FDO_PWM_DUTY(x) ((x) << 9)189#define FDO_PWM_DUTY_MASK (0xff << 9)190#define FDO_PWM_DUTY_SHIFT 9191#define CG_THERMAL_INT 0xC030000C192#define CI_DIG_THERM_INTH(x) ((x) << 8)193#define CI_DIG_THERM_INTH_MASK 0x0000FF00194#define CI_DIG_THERM_INTH_SHIFT 8195#define CI_DIG_THERM_INTL(x) ((x) << 16)196#define CI_DIG_THERM_INTL_MASK 0x00FF0000197#define CI_DIG_THERM_INTL_SHIFT 16198#define THERM_INT_MASK_HIGH (1 << 24)199#define THERM_INT_MASK_LOW (1 << 25)200#define CG_MULT_THERMAL_CTRL 0xC0300010201#define TEMP_SEL(x) ((x) << 20)202#define TEMP_SEL_MASK (0xff << 20)203#define TEMP_SEL_SHIFT 20204#define CG_MULT_THERMAL_STATUS 0xC0300014205#define ASIC_MAX_TEMP(x) ((x) << 0)206#define ASIC_MAX_TEMP_MASK 0x000001ff207#define ASIC_MAX_TEMP_SHIFT 0208#define CTF_TEMP(x) ((x) << 9)209#define CTF_TEMP_MASK 0x0003fe00210#define CTF_TEMP_SHIFT 9211 212#define CG_FDO_CTRL0 0xC0300064213#define FDO_STATIC_DUTY(x) ((x) << 0)214#define FDO_STATIC_DUTY_MASK 0x000000FF215#define FDO_STATIC_DUTY_SHIFT 0216#define CG_FDO_CTRL1 0xC0300068217#define FMAX_DUTY100(x) ((x) << 0)218#define FMAX_DUTY100_MASK 0x000000FF219#define FMAX_DUTY100_SHIFT 0220#define CG_FDO_CTRL2 0xC030006C221#define TMIN(x) ((x) << 0)222#define TMIN_MASK 0x000000FF223#define TMIN_SHIFT 0224#define FDO_PWM_MODE(x) ((x) << 11)225#define FDO_PWM_MODE_MASK (7 << 11)226#define FDO_PWM_MODE_SHIFT 11227#define TACH_PWM_RESP_RATE(x) ((x) << 25)228#define TACH_PWM_RESP_RATE_MASK (0x7f << 25)229#define TACH_PWM_RESP_RATE_SHIFT 25230#define CG_TACH_CTRL 0xC0300070231# define EDGE_PER_REV(x) ((x) << 0)232# define EDGE_PER_REV_MASK (0x7 << 0)233# define EDGE_PER_REV_SHIFT 0234# define TARGET_PERIOD(x) ((x) << 3)235# define TARGET_PERIOD_MASK 0xfffffff8236# define TARGET_PERIOD_SHIFT 3237#define CG_TACH_STATUS 0xC0300074238# define TACH_PERIOD(x) ((x) << 0)239# define TACH_PERIOD_MASK 0xffffffff240# define TACH_PERIOD_SHIFT 0241 242#define CG_ECLK_CNTL 0xC05000AC243# define ECLK_DIVIDER_MASK 0x7f244# define ECLK_DIR_CNTL_EN (1 << 8)245#define CG_ECLK_STATUS 0xC05000B0246# define ECLK_STATUS (1 << 0)247 248#define CG_SPLL_FUNC_CNTL 0xC0500140249#define SPLL_RESET (1 << 0)250#define SPLL_PWRON (1 << 1)251#define SPLL_BYPASS_EN (1 << 3)252#define SPLL_REF_DIV(x) ((x) << 5)253#define SPLL_REF_DIV_MASK (0x3f << 5)254#define SPLL_PDIV_A(x) ((x) << 20)255#define SPLL_PDIV_A_MASK (0x7f << 20)256#define SPLL_PDIV_A_SHIFT 20257#define CG_SPLL_FUNC_CNTL_2 0xC0500144258#define SCLK_MUX_SEL(x) ((x) << 0)259#define SCLK_MUX_SEL_MASK (0x1ff << 0)260#define CG_SPLL_FUNC_CNTL_3 0xC0500148261#define SPLL_FB_DIV(x) ((x) << 0)262#define SPLL_FB_DIV_MASK (0x3ffffff << 0)263#define SPLL_FB_DIV_SHIFT 0264#define SPLL_DITHEN (1 << 28)265#define CG_SPLL_FUNC_CNTL_4 0xC050014C266 267#define CG_SPLL_SPREAD_SPECTRUM 0xC0500164268#define SSEN (1 << 0)269#define CLK_S(x) ((x) << 4)270#define CLK_S_MASK (0xfff << 4)271#define CLK_S_SHIFT 4272#define CG_SPLL_SPREAD_SPECTRUM_2 0xC0500168273#define CLK_V(x) ((x) << 0)274#define CLK_V_MASK (0x3ffffff << 0)275#define CLK_V_SHIFT 0276 277#define MPLL_BYPASSCLK_SEL 0xC050019C278# define MPLL_CLKOUT_SEL(x) ((x) << 8)279# define MPLL_CLKOUT_SEL_MASK 0xFF00280#define CG_CLKPIN_CNTL 0xC05001A0281# define XTALIN_DIVIDE (1 << 1)282# define BCLK_AS_XCLK (1 << 2)283#define CG_CLKPIN_CNTL_2 0xC05001A4284# define FORCE_BIF_REFCLK_EN (1 << 3)285# define MUX_TCLK_TO_XCLK (1 << 8)286#define THM_CLK_CNTL 0xC05001A8287# define CMON_CLK_SEL(x) ((x) << 0)288# define CMON_CLK_SEL_MASK 0xFF289# define TMON_CLK_SEL(x) ((x) << 8)290# define TMON_CLK_SEL_MASK 0xFF00291#define MISC_CLK_CTRL 0xC05001AC292# define DEEP_SLEEP_CLK_SEL(x) ((x) << 0)293# define DEEP_SLEEP_CLK_SEL_MASK 0xFF294# define ZCLK_SEL(x) ((x) << 8)295# define ZCLK_SEL_MASK 0xFF00296 297/* KV/KB */298#define CG_THERMAL_INT_CTRL 0xC2100028299#define DIG_THERM_INTH(x) ((x) << 0)300#define DIG_THERM_INTH_MASK 0x000000FF301#define DIG_THERM_INTH_SHIFT 0302#define DIG_THERM_INTL(x) ((x) << 8)303#define DIG_THERM_INTL_MASK 0x0000FF00304#define DIG_THERM_INTL_SHIFT 8305#define THERM_INTH_MASK (1 << 24)306#define THERM_INTL_MASK (1 << 25)307 308/* PCIE registers idx/data 0x38/0x3c */309#define PB0_PIF_PWRDOWN_0 0x1100012 /* PCIE */310# define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7)311# define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7)312# define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7313# define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10)314# define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10)315# define PLL_POWER_STATE_IN_OFF_0_SHIFT 10316# define PLL_RAMP_UP_TIME_0(x) ((x) << 24)317# define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24)318# define PLL_RAMP_UP_TIME_0_SHIFT 24319#define PB0_PIF_PWRDOWN_1 0x1100013 /* PCIE */320# define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7)321# define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7)322# define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7323# define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10)324# define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10)325# define PLL_POWER_STATE_IN_OFF_1_SHIFT 10326# define PLL_RAMP_UP_TIME_1(x) ((x) << 24)327# define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24)328# define PLL_RAMP_UP_TIME_1_SHIFT 24329 330#define PCIE_CNTL2 0x1001001c /* PCIE */331# define SLV_MEM_LS_EN (1 << 16)332# define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17)333# define MST_MEM_LS_EN (1 << 18)334# define REPLAY_MEM_LS_EN (1 << 19)335 336#define PCIE_LC_STATUS1 0x1400028 /* PCIE */337# define LC_REVERSE_RCVR (1 << 0)338# define LC_REVERSE_XMIT (1 << 1)339# define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2)340# define LC_OPERATING_LINK_WIDTH_SHIFT 2341# define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5)342# define LC_DETECTED_LINK_WIDTH_SHIFT 5343 344#define PCIE_P_CNTL 0x1400040 /* PCIE */345# define P_IGNORE_EDB_ERR (1 << 6)346 347#define PB1_PIF_PWRDOWN_0 0x2100012 /* PCIE */348#define PB1_PIF_PWRDOWN_1 0x2100013 /* PCIE */349 350#define PCIE_LC_CNTL 0x100100A0 /* PCIE */351# define LC_L0S_INACTIVITY(x) ((x) << 8)352# define LC_L0S_INACTIVITY_MASK (0xf << 8)353# define LC_L0S_INACTIVITY_SHIFT 8354# define LC_L1_INACTIVITY(x) ((x) << 12)355# define LC_L1_INACTIVITY_MASK (0xf << 12)356# define LC_L1_INACTIVITY_SHIFT 12357# define LC_PMI_TO_L1_DIS (1 << 16)358# define LC_ASPM_TO_L1_DIS (1 << 24)359 360#define PCIE_LC_LINK_WIDTH_CNTL 0x100100A2 /* PCIE */361# define LC_LINK_WIDTH_SHIFT 0362# define LC_LINK_WIDTH_MASK 0x7363# define LC_LINK_WIDTH_X0 0364# define LC_LINK_WIDTH_X1 1365# define LC_LINK_WIDTH_X2 2366# define LC_LINK_WIDTH_X4 3367# define LC_LINK_WIDTH_X8 4368# define LC_LINK_WIDTH_X16 6369# define LC_LINK_WIDTH_RD_SHIFT 4370# define LC_LINK_WIDTH_RD_MASK 0x70371# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)372# define LC_RECONFIG_NOW (1 << 8)373# define LC_RENEGOTIATION_SUPPORT (1 << 9)374# define LC_RENEGOTIATE_EN (1 << 10)375# define LC_SHORT_RECONFIG_EN (1 << 11)376# define LC_UPCONFIGURE_SUPPORT (1 << 12)377# define LC_UPCONFIGURE_DIS (1 << 13)378# define LC_DYN_LANES_PWR_STATE(x) ((x) << 21)379# define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21)380# define LC_DYN_LANES_PWR_STATE_SHIFT 21381#define PCIE_LC_N_FTS_CNTL 0x100100a3 /* PCIE */382# define LC_XMIT_N_FTS(x) ((x) << 0)383# define LC_XMIT_N_FTS_MASK (0xff << 0)384# define LC_XMIT_N_FTS_SHIFT 0385# define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8)386# define LC_N_FTS_MASK (0xff << 24)387#define PCIE_LC_SPEED_CNTL 0x100100A4 /* PCIE */388# define LC_GEN2_EN_STRAP (1 << 0)389# define LC_GEN3_EN_STRAP (1 << 1)390# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2)391# define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3)392# define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3393# define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5)394# define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6)395# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7)396# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8)397# define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9)398# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10)399# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10400# define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */401# define LC_CURRENT_DATA_RATE_SHIFT 13402# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16)403# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18)404# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19)405# define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20)406# define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21)407 408#define PCIE_LC_CNTL2 0x100100B1 /* PCIE */409# define LC_ALLOW_PDWN_IN_L1 (1 << 17)410# define LC_ALLOW_PDWN_IN_L23 (1 << 18)411 412#define PCIE_LC_CNTL3 0x100100B5 /* PCIE */413# define LC_GO_TO_RECOVERY (1 << 30)414#define PCIE_LC_CNTL4 0x100100B6 /* PCIE */415# define LC_REDO_EQ (1 << 5)416# define LC_SET_QUIESCE (1 << 13)417 418/* direct registers */419#define PCIE_INDEX 0x38420#define PCIE_DATA 0x3C421 422#define SMC_IND_INDEX_0 0x200423#define SMC_IND_DATA_0 0x204424 425#define SMC_IND_ACCESS_CNTL 0x240426#define AUTO_INCREMENT_IND_0 (1 << 0)427 428#define SMC_MESSAGE_0 0x250429#define SMC_MSG_MASK 0xffff430#define SMC_RESP_0 0x254431#define SMC_RESP_MASK 0xffff432 433#define SMC_MSG_ARG_0 0x290434 435#define VGA_HDP_CONTROL 0x328436#define VGA_MEMORY_DISABLE (1 << 4)437 438#define DMIF_ADDR_CALC 0xC00439 440#define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0441# define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0)442# define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4)443 444#define SRBM_GFX_CNTL 0xE44445#define PIPEID(x) ((x) << 0)446#define MEID(x) ((x) << 2)447#define VMID(x) ((x) << 4)448#define QUEUEID(x) ((x) << 8)449 450#define SRBM_STATUS2 0xE4C451#define SDMA_BUSY (1 << 5)452#define SDMA1_BUSY (1 << 6)453#define SRBM_STATUS 0xE50454#define UVD_RQ_PENDING (1 << 1)455#define GRBM_RQ_PENDING (1 << 5)456#define VMC_BUSY (1 << 8)457#define MCB_BUSY (1 << 9)458#define MCB_NON_DISPLAY_BUSY (1 << 10)459#define MCC_BUSY (1 << 11)460#define MCD_BUSY (1 << 12)461#define SEM_BUSY (1 << 14)462#define IH_BUSY (1 << 17)463#define UVD_BUSY (1 << 19)464 465#define SRBM_SOFT_RESET 0xE60466#define SOFT_RESET_BIF (1 << 1)467#define SOFT_RESET_R0PLL (1 << 4)468#define SOFT_RESET_DC (1 << 5)469#define SOFT_RESET_SDMA1 (1 << 6)470#define SOFT_RESET_GRBM (1 << 8)471#define SOFT_RESET_HDP (1 << 9)472#define SOFT_RESET_IH (1 << 10)473#define SOFT_RESET_MC (1 << 11)474#define SOFT_RESET_ROM (1 << 14)475#define SOFT_RESET_SEM (1 << 15)476#define SOFT_RESET_VMC (1 << 17)477#define SOFT_RESET_SDMA (1 << 20)478#define SOFT_RESET_TST (1 << 21)479#define SOFT_RESET_REGBB (1 << 22)480#define SOFT_RESET_ORB (1 << 23)481#define SOFT_RESET_VCE (1 << 24)482 483#define SRBM_READ_ERROR 0xE98484#define SRBM_INT_CNTL 0xEA0485#define SRBM_INT_ACK 0xEA8486 487#define VM_L2_CNTL 0x1400488#define ENABLE_L2_CACHE (1 << 0)489#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)490#define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2)491#define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4)492#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)493#define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)494#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15)495#define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19)496#define VM_L2_CNTL2 0x1404497#define INVALIDATE_ALL_L1_TLBS (1 << 0)498#define INVALIDATE_L2_CACHE (1 << 1)499#define INVALIDATE_CACHE_MODE(x) ((x) << 26)500#define INVALIDATE_PTE_AND_PDE_CACHES 0501#define INVALIDATE_ONLY_PTE_CACHES 1502#define INVALIDATE_ONLY_PDE_CACHES 2503#define VM_L2_CNTL3 0x1408504#define BANK_SELECT(x) ((x) << 0)505#define L2_CACHE_UPDATE_MODE(x) ((x) << 6)506#define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)507#define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)508#define VM_L2_STATUS 0x140C509#define L2_BUSY (1 << 0)510#define VM_CONTEXT0_CNTL 0x1410511#define ENABLE_CONTEXT (1 << 0)512#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)513#define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)514#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)515#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)516#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)517#define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)518#define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)519#define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)520#define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)521#define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)522#define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)523#define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)524#define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)525#define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24)526#define VM_CONTEXT1_CNTL 0x1414527#define VM_CONTEXT0_CNTL2 0x1430528#define VM_CONTEXT1_CNTL2 0x1434529#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438530#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c531#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440532#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444533#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448534#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c535#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450536#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454537 538#define VM_INVALIDATE_REQUEST 0x1478539#define VM_INVALIDATE_RESPONSE 0x147c540 541#define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC542#define PROTECTIONS_MASK (0xf << 0)543#define PROTECTIONS_SHIFT 0544 /* bit 0: range545 * bit 1: pde0546 * bit 2: valid547 * bit 3: read548 * bit 4: write549 */550#define MEMORY_CLIENT_ID_MASK (0xff << 12)551#define HAWAII_MEMORY_CLIENT_ID_MASK (0x1ff << 12)552#define MEMORY_CLIENT_ID_SHIFT 12553#define MEMORY_CLIENT_RW_MASK (1 << 24)554#define MEMORY_CLIENT_RW_SHIFT 24555#define FAULT_VMID_MASK (0xf << 25)556#define FAULT_VMID_SHIFT 25557 558#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x14E4559 560#define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC561 562#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518563#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c564 565#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c566#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540567#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544568#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548569#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c570#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550571#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554572#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558573#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c574#define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560575 576#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C577#define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580578 579#define VM_L2_CG 0x15c0580#define MC_CG_ENABLE (1 << 18)581#define MC_LS_ENABLE (1 << 19)582 583#define MC_SHARED_CHMAP 0x2004584#define NOOFCHAN_SHIFT 12585#define NOOFCHAN_MASK 0x0000f000586#define MC_SHARED_CHREMAP 0x2008587 588#define CHUB_CONTROL 0x1864589#define BYPASS_VM (1 << 0)590 591#define MC_VM_FB_LOCATION 0x2024592#define MC_VM_AGP_TOP 0x2028593#define MC_VM_AGP_BOT 0x202C594#define MC_VM_AGP_BASE 0x2030595#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034596#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038597#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C598 599#define MC_VM_MX_L1_TLB_CNTL 0x2064600#define ENABLE_L1_TLB (1 << 0)601#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)602#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)603#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)604#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)605#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)606#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)607#define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)608#define MC_VM_FB_OFFSET 0x2068609 610#define MC_SHARED_BLACKOUT_CNTL 0x20ac611 612#define MC_HUB_MISC_HUB_CG 0x20b8613#define MC_HUB_MISC_VM_CG 0x20bc614 615#define MC_HUB_MISC_SIP_CG 0x20c0616 617#define MC_XPB_CLK_GAT 0x2478618 619#define MC_CITF_MISC_RD_CG 0x2648620#define MC_CITF_MISC_WR_CG 0x264c621#define MC_CITF_MISC_VM_CG 0x2650622 623#define MC_ARB_RAMCFG 0x2760624#define NOOFBANK_SHIFT 0625#define NOOFBANK_MASK 0x00000003626#define NOOFRANK_SHIFT 2627#define NOOFRANK_MASK 0x00000004628#define NOOFROWS_SHIFT 3629#define NOOFROWS_MASK 0x00000038630#define NOOFCOLS_SHIFT 6631#define NOOFCOLS_MASK 0x000000C0632#define CHANSIZE_SHIFT 8633#define CHANSIZE_MASK 0x00000100634#define NOOFGROUPS_SHIFT 12635#define NOOFGROUPS_MASK 0x00001000636 637#define MC_ARB_DRAM_TIMING 0x2774638#define MC_ARB_DRAM_TIMING2 0x2778639 640#define MC_ARB_BURST_TIME 0x2808641#define STATE0(x) ((x) << 0)642#define STATE0_MASK (0x1f << 0)643#define STATE0_SHIFT 0644#define STATE1(x) ((x) << 5)645#define STATE1_MASK (0x1f << 5)646#define STATE1_SHIFT 5647#define STATE2(x) ((x) << 10)648#define STATE2_MASK (0x1f << 10)649#define STATE2_SHIFT 10650#define STATE3(x) ((x) << 15)651#define STATE3_MASK (0x1f << 15)652#define STATE3_SHIFT 15653 654#define MC_SEQ_RAS_TIMING 0x28a0655#define MC_SEQ_CAS_TIMING 0x28a4656#define MC_SEQ_MISC_TIMING 0x28a8657#define MC_SEQ_MISC_TIMING2 0x28ac658#define MC_SEQ_PMG_TIMING 0x28b0659#define MC_SEQ_RD_CTL_D0 0x28b4660#define MC_SEQ_RD_CTL_D1 0x28b8661#define MC_SEQ_WR_CTL_D0 0x28bc662#define MC_SEQ_WR_CTL_D1 0x28c0663 664#define MC_SEQ_SUP_CNTL 0x28c8665#define RUN_MASK (1 << 0)666#define MC_SEQ_SUP_PGM 0x28cc667#define MC_PMG_AUTO_CMD 0x28d0668 669#define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8670#define TRAIN_DONE_D0 (1 << 30)671#define TRAIN_DONE_D1 (1 << 31)672 673#define MC_IO_PAD_CNTL_D0 0x29d0674#define MEM_FALL_OUT_CMD (1 << 8)675 676#define MC_SEQ_MISC0 0x2a00677#define MC_SEQ_MISC0_VEN_ID_SHIFT 8678#define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00679#define MC_SEQ_MISC0_VEN_ID_VALUE 3680#define MC_SEQ_MISC0_REV_ID_SHIFT 12681#define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000682#define MC_SEQ_MISC0_REV_ID_VALUE 1683#define MC_SEQ_MISC0_GDDR5_SHIFT 28684#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000685#define MC_SEQ_MISC0_GDDR5_VALUE 5686#define MC_SEQ_MISC1 0x2a04687#define MC_SEQ_RESERVE_M 0x2a08688#define MC_PMG_CMD_EMRS 0x2a0c689 690#define MC_SEQ_IO_DEBUG_INDEX 0x2a44691#define MC_SEQ_IO_DEBUG_DATA 0x2a48692 693#define MC_SEQ_MISC5 0x2a54694#define MC_SEQ_MISC6 0x2a58695 696#define MC_SEQ_MISC7 0x2a64697 698#define MC_SEQ_RAS_TIMING_LP 0x2a6c699#define MC_SEQ_CAS_TIMING_LP 0x2a70700#define MC_SEQ_MISC_TIMING_LP 0x2a74701#define MC_SEQ_MISC_TIMING2_LP 0x2a78702#define MC_SEQ_WR_CTL_D0_LP 0x2a7c703#define MC_SEQ_WR_CTL_D1_LP 0x2a80704#define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84705#define MC_SEQ_PMG_CMD_MRS_LP 0x2a88706 707#define MC_PMG_CMD_MRS 0x2aac708 709#define MC_SEQ_RD_CTL_D0_LP 0x2b1c710#define MC_SEQ_RD_CTL_D1_LP 0x2b20711 712#define MC_PMG_CMD_MRS1 0x2b44713#define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48714#define MC_SEQ_PMG_TIMING_LP 0x2b4c715 716#define MC_SEQ_WR_CTL_2 0x2b54717#define MC_SEQ_WR_CTL_2_LP 0x2b58718#define MC_PMG_CMD_MRS2 0x2b5c719#define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60720 721#define MCLK_PWRMGT_CNTL 0x2ba0722# define DLL_SPEED(x) ((x) << 0)723# define DLL_SPEED_MASK (0x1f << 0)724# define DLL_READY (1 << 6)725# define MC_INT_CNTL (1 << 7)726# define MRDCK0_PDNB (1 << 8)727# define MRDCK1_PDNB (1 << 9)728# define MRDCK0_RESET (1 << 16)729# define MRDCK1_RESET (1 << 17)730# define DLL_READY_READ (1 << 24)731#define DLL_CNTL 0x2ba4732# define MRDCK0_BYPASS (1 << 24)733# define MRDCK1_BYPASS (1 << 25)734 735#define MPLL_FUNC_CNTL 0x2bb4736#define BWCTRL(x) ((x) << 20)737#define BWCTRL_MASK (0xff << 20)738#define MPLL_FUNC_CNTL_1 0x2bb8739#define VCO_MODE(x) ((x) << 0)740#define VCO_MODE_MASK (3 << 0)741#define CLKFRAC(x) ((x) << 4)742#define CLKFRAC_MASK (0xfff << 4)743#define CLKF(x) ((x) << 16)744#define CLKF_MASK (0xfff << 16)745#define MPLL_FUNC_CNTL_2 0x2bbc746#define MPLL_AD_FUNC_CNTL 0x2bc0747#define YCLK_POST_DIV(x) ((x) << 0)748#define YCLK_POST_DIV_MASK (7 << 0)749#define MPLL_DQ_FUNC_CNTL 0x2bc4750#define YCLK_SEL(x) ((x) << 4)751#define YCLK_SEL_MASK (1 << 4)752 753#define MPLL_SS1 0x2bcc754#define CLKV(x) ((x) << 0)755#define CLKV_MASK (0x3ffffff << 0)756#define MPLL_SS2 0x2bd0757#define CLKS(x) ((x) << 0)758#define CLKS_MASK (0xfff << 0)759 760#define HDP_HOST_PATH_CNTL 0x2C00761#define CLOCK_GATING_DIS (1 << 23)762#define HDP_NONSURFACE_BASE 0x2C04763#define HDP_NONSURFACE_INFO 0x2C08764#define HDP_NONSURFACE_SIZE 0x2C0C765 766#define HDP_ADDR_CONFIG 0x2F48767#define HDP_MISC_CNTL 0x2F4C768#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)769#define HDP_MEM_POWER_LS 0x2F50770#define HDP_LS_ENABLE (1 << 0)771 772#define ATC_MISC_CG 0x3350773 774#define GMCON_RENG_EXECUTE 0x3508775#define RENG_EXECUTE_ON_PWR_UP (1 << 0)776#define GMCON_MISC 0x350c777#define RENG_EXECUTE_ON_REG_UPDATE (1 << 11)778#define STCTRL_STUTTER_EN (1 << 16)779 780#define GMCON_PGFSM_CONFIG 0x3538781#define GMCON_PGFSM_WRITE 0x353c782#define GMCON_PGFSM_READ 0x3540783#define GMCON_MISC3 0x3544784 785#define MC_SEQ_CNTL_3 0x3600786# define CAC_EN (1 << 31)787#define MC_SEQ_G5PDX_CTRL 0x3604788#define MC_SEQ_G5PDX_CTRL_LP 0x3608789#define MC_SEQ_G5PDX_CMD0 0x360c790#define MC_SEQ_G5PDX_CMD0_LP 0x3610791#define MC_SEQ_G5PDX_CMD1 0x3614792#define MC_SEQ_G5PDX_CMD1_LP 0x3618793 794#define MC_SEQ_PMG_DVS_CTL 0x3628795#define MC_SEQ_PMG_DVS_CTL_LP 0x362c796#define MC_SEQ_PMG_DVS_CMD 0x3630797#define MC_SEQ_PMG_DVS_CMD_LP 0x3634798#define MC_SEQ_DLL_STBY 0x3638799#define MC_SEQ_DLL_STBY_LP 0x363c800 801#define IH_RB_CNTL 0x3e00802# define IH_RB_ENABLE (1 << 0)803# define IH_RB_SIZE(x) ((x) << 1) /* log2 */804# define IH_RB_FULL_DRAIN_ENABLE (1 << 6)805# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)806# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */807# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)808# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)809#define IH_RB_BASE 0x3e04810#define IH_RB_RPTR 0x3e08811#define IH_RB_WPTR 0x3e0c812# define RB_OVERFLOW (1 << 0)813# define WPTR_OFFSET_MASK 0x3fffc814#define IH_RB_WPTR_ADDR_HI 0x3e10815#define IH_RB_WPTR_ADDR_LO 0x3e14816#define IH_CNTL 0x3e18817# define ENABLE_INTR (1 << 0)818# define IH_MC_SWAP(x) ((x) << 1)819# define IH_MC_SWAP_NONE 0820# define IH_MC_SWAP_16BIT 1821# define IH_MC_SWAP_32BIT 2822# define IH_MC_SWAP_64BIT 3823# define RPTR_REARM (1 << 4)824# define MC_WRREQ_CREDIT(x) ((x) << 15)825# define MC_WR_CLEAN_CNT(x) ((x) << 20)826# define MC_VMID(x) ((x) << 25)827 828#define BIF_LNCNT_RESET 0x5220829# define RESET_LNCNT_EN (1 << 0)830 831#define CONFIG_MEMSIZE 0x5428832 833#define INTERRUPT_CNTL 0x5468834# define IH_DUMMY_RD_OVERRIDE (1 << 0)835# define IH_DUMMY_RD_EN (1 << 1)836# define IH_REQ_NONSNOOP_EN (1 << 3)837# define GEN_IH_INT_EN (1 << 8)838#define INTERRUPT_CNTL2 0x546c839 840#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480841 842#define BIF_FB_EN 0x5490843#define FB_READ_EN (1 << 0)844#define FB_WRITE_EN (1 << 1)845 846#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0847 848#define GPU_HDP_FLUSH_REQ 0x54DC849#define GPU_HDP_FLUSH_DONE 0x54E0850#define CP0 (1 << 0)851#define CP1 (1 << 1)852#define CP2 (1 << 2)853#define CP3 (1 << 3)854#define CP4 (1 << 4)855#define CP5 (1 << 5)856#define CP6 (1 << 6)857#define CP7 (1 << 7)858#define CP8 (1 << 8)859#define CP9 (1 << 9)860#define SDMA0 (1 << 10)861#define SDMA1 (1 << 11)862 863/* 0x6b04, 0x7704, 0x10304, 0x10f04, 0x11b04, 0x12704 */864#define LB_MEMORY_CTRL 0x6b04865#define LB_MEMORY_SIZE(x) ((x) << 0)866#define LB_MEMORY_CONFIG(x) ((x) << 20)867 868#define DPG_WATERMARK_MASK_CONTROL 0x6cc8869# define LATENCY_WATERMARK_MASK(x) ((x) << 8)870#define DPG_PIPE_LATENCY_CONTROL 0x6ccc871# define LATENCY_LOW_WATERMARK(x) ((x) << 0)872# define LATENCY_HIGH_WATERMARK(x) ((x) << 16)873 874/* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */875#define LB_VLINE_STATUS 0x6b24876# define VLINE_OCCURRED (1 << 0)877# define VLINE_ACK (1 << 4)878# define VLINE_STAT (1 << 12)879# define VLINE_INTERRUPT (1 << 16)880# define VLINE_INTERRUPT_TYPE (1 << 17)881/* 0x6b2c, 0x772c, 0x1032c, 0x10f2c, 0x11b2c, 0x1272c */882#define LB_VBLANK_STATUS 0x6b2c883# define VBLANK_OCCURRED (1 << 0)884# define VBLANK_ACK (1 << 4)885# define VBLANK_STAT (1 << 12)886# define VBLANK_INTERRUPT (1 << 16)887# define VBLANK_INTERRUPT_TYPE (1 << 17)888 889/* 0x6b20, 0x7720, 0x10320, 0x10f20, 0x11b20, 0x12720 */890#define LB_INTERRUPT_MASK 0x6b20891# define VBLANK_INTERRUPT_MASK (1 << 0)892# define VLINE_INTERRUPT_MASK (1 << 4)893# define VLINE2_INTERRUPT_MASK (1 << 8)894 895#define DISP_INTERRUPT_STATUS 0x60f4896# define LB_D1_VLINE_INTERRUPT (1 << 2)897# define LB_D1_VBLANK_INTERRUPT (1 << 3)898# define DC_HPD1_INTERRUPT (1 << 17)899# define DC_HPD1_RX_INTERRUPT (1 << 18)900# define DACA_AUTODETECT_INTERRUPT (1 << 22)901# define DACB_AUTODETECT_INTERRUPT (1 << 23)902# define DC_I2C_SW_DONE_INTERRUPT (1 << 24)903# define DC_I2C_HW_DONE_INTERRUPT (1 << 25)904#define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8905# define LB_D2_VLINE_INTERRUPT (1 << 2)906# define LB_D2_VBLANK_INTERRUPT (1 << 3)907# define DC_HPD2_INTERRUPT (1 << 17)908# define DC_HPD2_RX_INTERRUPT (1 << 18)909# define DISP_TIMER_INTERRUPT (1 << 24)910#define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc911# define LB_D3_VLINE_INTERRUPT (1 << 2)912# define LB_D3_VBLANK_INTERRUPT (1 << 3)913# define DC_HPD3_INTERRUPT (1 << 17)914# define DC_HPD3_RX_INTERRUPT (1 << 18)915#define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100916# define LB_D4_VLINE_INTERRUPT (1 << 2)917# define LB_D4_VBLANK_INTERRUPT (1 << 3)918# define DC_HPD4_INTERRUPT (1 << 17)919# define DC_HPD4_RX_INTERRUPT (1 << 18)920#define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c921# define LB_D5_VLINE_INTERRUPT (1 << 2)922# define LB_D5_VBLANK_INTERRUPT (1 << 3)923# define DC_HPD5_INTERRUPT (1 << 17)924# define DC_HPD5_RX_INTERRUPT (1 << 18)925#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150926# define LB_D6_VLINE_INTERRUPT (1 << 2)927# define LB_D6_VBLANK_INTERRUPT (1 << 3)928# define DC_HPD6_INTERRUPT (1 << 17)929# define DC_HPD6_RX_INTERRUPT (1 << 18)930#define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780931 932/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */933#define GRPH_INT_STATUS 0x6858934# define GRPH_PFLIP_INT_OCCURRED (1 << 0)935# define GRPH_PFLIP_INT_CLEAR (1 << 8)936/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */937#define GRPH_INT_CONTROL 0x685c938# define GRPH_PFLIP_INT_MASK (1 << 0)939# define GRPH_PFLIP_INT_TYPE (1 << 8)940 941#define DAC_AUTODETECT_INT_CONTROL 0x67c8942 943#define DC_HPD1_INT_STATUS 0x601c944#define DC_HPD2_INT_STATUS 0x6028945#define DC_HPD3_INT_STATUS 0x6034946#define DC_HPD4_INT_STATUS 0x6040947#define DC_HPD5_INT_STATUS 0x604c948#define DC_HPD6_INT_STATUS 0x6058949# define DC_HPDx_INT_STATUS (1 << 0)950# define DC_HPDx_SENSE (1 << 1)951# define DC_HPDx_SENSE_DELAYED (1 << 4)952# define DC_HPDx_RX_INT_STATUS (1 << 8)953 954#define DC_HPD1_INT_CONTROL 0x6020955#define DC_HPD2_INT_CONTROL 0x602c956#define DC_HPD3_INT_CONTROL 0x6038957#define DC_HPD4_INT_CONTROL 0x6044958#define DC_HPD5_INT_CONTROL 0x6050959#define DC_HPD6_INT_CONTROL 0x605c960# define DC_HPDx_INT_ACK (1 << 0)961# define DC_HPDx_INT_POLARITY (1 << 8)962# define DC_HPDx_INT_EN (1 << 16)963# define DC_HPDx_RX_INT_ACK (1 << 20)964# define DC_HPDx_RX_INT_EN (1 << 24)965 966#define DC_HPD1_CONTROL 0x6024967#define DC_HPD2_CONTROL 0x6030968#define DC_HPD3_CONTROL 0x603c969#define DC_HPD4_CONTROL 0x6048970#define DC_HPD5_CONTROL 0x6054971#define DC_HPD6_CONTROL 0x6060972# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)973# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)974# define DC_HPDx_EN (1 << 28)975 976#define DPG_PIPE_STUTTER_CONTROL 0x6cd4977# define STUTTER_ENABLE (1 << 0)978 979/* DCE8 FMT blocks */980#define FMT_DYNAMIC_EXP_CNTL 0x6fb4981# define FMT_DYNAMIC_EXP_EN (1 << 0)982# define FMT_DYNAMIC_EXP_MODE (1 << 4)983 /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */984#define FMT_CONTROL 0x6fb8985# define FMT_PIXEL_ENCODING (1 << 16)986 /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */987#define FMT_BIT_DEPTH_CONTROL 0x6fc8988# define FMT_TRUNCATE_EN (1 << 0)989# define FMT_TRUNCATE_MODE (1 << 1)990# define FMT_TRUNCATE_DEPTH(x) ((x) << 4) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */991# define FMT_SPATIAL_DITHER_EN (1 << 8)992# define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9)993# define FMT_SPATIAL_DITHER_DEPTH(x) ((x) << 11) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */994# define FMT_FRAME_RANDOM_ENABLE (1 << 13)995# define FMT_RGB_RANDOM_ENABLE (1 << 14)996# define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15)997# define FMT_TEMPORAL_DITHER_EN (1 << 16)998# define FMT_TEMPORAL_DITHER_DEPTH(x) ((x) << 17) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */999# define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21)1000# define FMT_TEMPORAL_LEVEL (1 << 24)1001# define FMT_TEMPORAL_DITHER_RESET (1 << 25)1002# define FMT_25FRC_SEL(x) ((x) << 26)1003# define FMT_50FRC_SEL(x) ((x) << 28)1004# define FMT_75FRC_SEL(x) ((x) << 30)1005#define FMT_CLAMP_CONTROL 0x6fe41006# define FMT_CLAMP_DATA_EN (1 << 0)1007# define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16)1008# define FMT_CLAMP_6BPC 01009# define FMT_CLAMP_8BPC 11010# define FMT_CLAMP_10BPC 21011 1012#define GRBM_CNTL 0x80001013#define GRBM_READ_TIMEOUT(x) ((x) << 0)1014 1015#define GRBM_STATUS2 0x80081016#define ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000F1017#define ME0PIPE1_CF_RQ_PENDING (1 << 4)1018#define ME0PIPE1_PF_RQ_PENDING (1 << 5)1019#define ME1PIPE0_RQ_PENDING (1 << 6)1020#define ME1PIPE1_RQ_PENDING (1 << 7)1021#define ME1PIPE2_RQ_PENDING (1 << 8)1022#define ME1PIPE3_RQ_PENDING (1 << 9)1023#define ME2PIPE0_RQ_PENDING (1 << 10)1024#define ME2PIPE1_RQ_PENDING (1 << 11)1025#define ME2PIPE2_RQ_PENDING (1 << 12)1026#define ME2PIPE3_RQ_PENDING (1 << 13)1027#define RLC_RQ_PENDING (1 << 14)1028#define RLC_BUSY (1 << 24)1029#define TC_BUSY (1 << 25)1030#define CPF_BUSY (1 << 28)1031#define CPC_BUSY (1 << 29)1032#define CPG_BUSY (1 << 30)1033 1034#define GRBM_STATUS 0x80101035#define ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000F1036#define SRBM_RQ_PENDING (1 << 5)1037#define ME0PIPE0_CF_RQ_PENDING (1 << 7)1038#define ME0PIPE0_PF_RQ_PENDING (1 << 8)1039#define GDS_DMA_RQ_PENDING (1 << 9)1040#define DB_CLEAN (1 << 12)1041#define CB_CLEAN (1 << 13)1042#define TA_BUSY (1 << 14)1043#define GDS_BUSY (1 << 15)1044#define WD_BUSY_NO_DMA (1 << 16)1045#define VGT_BUSY (1 << 17)1046#define IA_BUSY_NO_DMA (1 << 18)1047#define IA_BUSY (1 << 19)1048#define SX_BUSY (1 << 20)1049#define WD_BUSY (1 << 21)1050#define SPI_BUSY (1 << 22)1051#define BCI_BUSY (1 << 23)1052#define SC_BUSY (1 << 24)1053#define PA_BUSY (1 << 25)1054#define DB_BUSY (1 << 26)1055#define CP_COHERENCY_BUSY (1 << 28)1056#define CP_BUSY (1 << 29)1057#define CB_BUSY (1 << 30)1058#define GUI_ACTIVE (1 << 31)1059#define GRBM_STATUS_SE0 0x80141060#define GRBM_STATUS_SE1 0x80181061#define GRBM_STATUS_SE2 0x80381062#define GRBM_STATUS_SE3 0x803C1063#define SE_DB_CLEAN (1 << 1)1064#define SE_CB_CLEAN (1 << 2)1065#define SE_BCI_BUSY (1 << 22)1066#define SE_VGT_BUSY (1 << 23)1067#define SE_PA_BUSY (1 << 24)1068#define SE_TA_BUSY (1 << 25)1069#define SE_SX_BUSY (1 << 26)1070#define SE_SPI_BUSY (1 << 27)1071#define SE_SC_BUSY (1 << 29)1072#define SE_DB_BUSY (1 << 30)1073#define SE_CB_BUSY (1 << 31)1074 1075#define GRBM_SOFT_RESET 0x80201076#define SOFT_RESET_CP (1 << 0) /* All CP blocks */1077#define SOFT_RESET_RLC (1 << 2) /* RLC */1078#define SOFT_RESET_GFX (1 << 16) /* GFX */1079#define SOFT_RESET_CPF (1 << 17) /* CP fetcher shared by gfx and compute */1080#define SOFT_RESET_CPC (1 << 18) /* CP Compute (MEC1/2) */1081#define SOFT_RESET_CPG (1 << 19) /* CP GFX (PFP, ME, CE) */1082 1083#define GRBM_INT_CNTL 0x80601084# define RDERR_INT_ENABLE (1 << 0)1085# define GUI_IDLE_INT_ENABLE (1 << 19)1086 1087#define CP_CPC_STATUS 0x82101088#define CP_CPC_BUSY_STAT 0x82141089#define CP_CPC_STALLED_STAT1 0x82181090#define CP_CPF_STATUS 0x821c1091#define CP_CPF_BUSY_STAT 0x82201092#define CP_CPF_STALLED_STAT1 0x82241093 1094#define CP_MEC_CNTL 0x82341095#define MEC_ME2_HALT (1 << 28)1096#define MEC_ME1_HALT (1 << 30)1097 1098#define CP_MEC_CNTL 0x82341099#define MEC_ME2_HALT (1 << 28)1100#define MEC_ME1_HALT (1 << 30)1101 1102#define CP_STALLED_STAT3 0x86701103#define CP_STALLED_STAT1 0x86741104#define CP_STALLED_STAT2 0x86781105 1106#define CP_STAT 0x86801107 1108#define CP_ME_CNTL 0x86D81109#define CP_CE_HALT (1 << 24)1110#define CP_PFP_HALT (1 << 26)1111#define CP_ME_HALT (1 << 28)1112 1113#define CP_RB0_RPTR 0x87001114#define CP_RB_WPTR_DELAY 0x87041115#define CP_RB_WPTR_POLL_CNTL 0x87081116#define IDLE_POLL_COUNT(x) ((x) << 16)1117#define IDLE_POLL_COUNT_MASK (0xffff << 16)1118 1119#define CP_MEQ_THRESHOLDS 0x87641120#define MEQ1_START(x) ((x) << 0)1121#define MEQ2_START(x) ((x) << 8)1122 1123#define VGT_VTX_VECT_EJECT_REG 0x88B01124 1125#define VGT_CACHE_INVALIDATION 0x88C41126#define CACHE_INVALIDATION(x) ((x) << 0)1127#define VC_ONLY 01128#define TC_ONLY 11129#define VC_AND_TC 21130#define AUTO_INVLD_EN(x) ((x) << 6)1131#define NO_AUTO 01132#define ES_AUTO 11133#define GS_AUTO 21134#define ES_AND_GS_AUTO 31135 1136#define VGT_GS_VERTEX_REUSE 0x88D41137 1138#define CC_GC_SHADER_ARRAY_CONFIG 0x89bc1139#define INACTIVE_CUS_MASK 0xFFFF00001140#define INACTIVE_CUS_SHIFT 161141#define GC_USER_SHADER_ARRAY_CONFIG 0x89c01142 1143#define PA_CL_ENHANCE 0x8A141144#define CLIP_VTX_REORDER_ENA (1 << 0)1145#define NUM_CLIP_SEQ(x) ((x) << 1)1146 1147#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B241148#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)1149#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)1150 1151#define PA_SC_FIFO_SIZE 0x8BCC1152#define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0)1153#define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6)1154#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15)1155#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23)1156 1157#define PA_SC_ENHANCE 0x8BF01158#define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0)1159#define DISABLE_PA_SC_GUIDANCE (1 << 13)1160 1161#define SQ_CONFIG 0x8C001162 1163#define SH_MEM_BASES 0x8C281164/* if PTR32, these are the bases for scratch and lds */1165#define PRIVATE_BASE(x) ((x) << 0) /* scratch */1166#define SHARED_BASE(x) ((x) << 16) /* LDS */1167#define SH_MEM_APE1_BASE 0x8C2C1168/* if PTR32, this is the base location of GPUVM */1169#define SH_MEM_APE1_LIMIT 0x8C301170/* if PTR32, this is the upper limit of GPUVM */1171#define SH_MEM_CONFIG 0x8C341172#define PTR32 (1 << 0)1173#define ALIGNMENT_MODE(x) ((x) << 2)1174#define SH_MEM_ALIGNMENT_MODE_DWORD 01175#define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 11176#define SH_MEM_ALIGNMENT_MODE_STRICT 21177#define SH_MEM_ALIGNMENT_MODE_UNALIGNED 31178#define DEFAULT_MTYPE(x) ((x) << 4)1179#define APE1_MTYPE(x) ((x) << 7)1180/* valid for both DEFAULT_MTYPE and APE1_MTYPE */1181#define MTYPE_CACHED 01182#define MTYPE_NONCACHED 31183 1184#define SX_DEBUG_1 0x90601185 1186#define SPI_CONFIG_CNTL 0x91001187 1188#define SPI_CONFIG_CNTL_1 0x913C1189#define VTX_DONE_DELAY(x) ((x) << 0)1190#define INTERP_ONE_PRIM_PER_ROW (1 << 4)1191 1192#define TA_CNTL_AUX 0x95081193 1194#define DB_DEBUG 0x98301195#define DB_DEBUG2 0x98341196#define DB_DEBUG3 0x98381197 1198#define CC_RB_BACKEND_DISABLE 0x98F41199#define BACKEND_DISABLE(x) ((x) << 16)1200#define GB_ADDR_CONFIG 0x98F81201#define NUM_PIPES(x) ((x) << 0)1202#define NUM_PIPES_MASK 0x000000071203#define NUM_PIPES_SHIFT 01204#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)1205#define PIPE_INTERLEAVE_SIZE_MASK 0x000000701206#define PIPE_INTERLEAVE_SIZE_SHIFT 41207#define NUM_SHADER_ENGINES(x) ((x) << 12)1208#define NUM_SHADER_ENGINES_MASK 0x000030001209#define NUM_SHADER_ENGINES_SHIFT 121210#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)1211#define SHADER_ENGINE_TILE_SIZE_MASK 0x000700001212#define SHADER_ENGINE_TILE_SIZE_SHIFT 161213#define ROW_SIZE(x) ((x) << 28)1214#define ROW_SIZE_MASK 0x300000001215#define ROW_SIZE_SHIFT 281216 1217#define GB_TILE_MODE0 0x99101218# define ARRAY_MODE(x) ((x) << 2)1219# define ARRAY_LINEAR_GENERAL 01220# define ARRAY_LINEAR_ALIGNED 11221# define ARRAY_1D_TILED_THIN1 21222# define ARRAY_2D_TILED_THIN1 41223# define ARRAY_PRT_TILED_THIN1 51224# define ARRAY_PRT_2D_TILED_THIN1 61225# define PIPE_CONFIG(x) ((x) << 6)1226# define ADDR_SURF_P2 01227# define ADDR_SURF_P4_8x16 41228# define ADDR_SURF_P4_16x16 51229# define ADDR_SURF_P4_16x32 61230# define ADDR_SURF_P4_32x32 71231# define ADDR_SURF_P8_16x16_8x16 81232# define ADDR_SURF_P8_16x32_8x16 91233# define ADDR_SURF_P8_32x32_8x16 101234# define ADDR_SURF_P8_16x32_16x16 111235# define ADDR_SURF_P8_32x32_16x16 121236# define ADDR_SURF_P8_32x32_16x32 131237# define ADDR_SURF_P8_32x64_32x32 141238# define ADDR_SURF_P16_32x32_8x16 161239# define ADDR_SURF_P16_32x32_16x16 171240# define TILE_SPLIT(x) ((x) << 11)1241# define ADDR_SURF_TILE_SPLIT_64B 01242# define ADDR_SURF_TILE_SPLIT_128B 11243# define ADDR_SURF_TILE_SPLIT_256B 21244# define ADDR_SURF_TILE_SPLIT_512B 31245# define ADDR_SURF_TILE_SPLIT_1KB 41246# define ADDR_SURF_TILE_SPLIT_2KB 51247# define ADDR_SURF_TILE_SPLIT_4KB 61248# define MICRO_TILE_MODE_NEW(x) ((x) << 22)1249# define ADDR_SURF_DISPLAY_MICRO_TILING 01250# define ADDR_SURF_THIN_MICRO_TILING 11251# define ADDR_SURF_DEPTH_MICRO_TILING 21252# define ADDR_SURF_ROTATED_MICRO_TILING 31253# define SAMPLE_SPLIT(x) ((x) << 25)1254# define ADDR_SURF_SAMPLE_SPLIT_1 01255# define ADDR_SURF_SAMPLE_SPLIT_2 11256# define ADDR_SURF_SAMPLE_SPLIT_4 21257# define ADDR_SURF_SAMPLE_SPLIT_8 31258 1259#define GB_MACROTILE_MODE0 0x99901260# define BANK_WIDTH(x) ((x) << 0)1261# define ADDR_SURF_BANK_WIDTH_1 01262# define ADDR_SURF_BANK_WIDTH_2 11263# define ADDR_SURF_BANK_WIDTH_4 21264# define ADDR_SURF_BANK_WIDTH_8 31265# define BANK_HEIGHT(x) ((x) << 2)1266# define ADDR_SURF_BANK_HEIGHT_1 01267# define ADDR_SURF_BANK_HEIGHT_2 11268# define ADDR_SURF_BANK_HEIGHT_4 21269# define ADDR_SURF_BANK_HEIGHT_8 31270# define MACRO_TILE_ASPECT(x) ((x) << 4)1271# define ADDR_SURF_MACRO_ASPECT_1 01272# define ADDR_SURF_MACRO_ASPECT_2 11273# define ADDR_SURF_MACRO_ASPECT_4 21274# define ADDR_SURF_MACRO_ASPECT_8 31275# define NUM_BANKS(x) ((x) << 6)1276# define ADDR_SURF_2_BANK 01277# define ADDR_SURF_4_BANK 11278# define ADDR_SURF_8_BANK 21279# define ADDR_SURF_16_BANK 31280 1281#define CB_HW_CONTROL 0x9A101282 1283#define GC_USER_RB_BACKEND_DISABLE 0x9B7C1284#define BACKEND_DISABLE_MASK 0x00FF00001285#define BACKEND_DISABLE_SHIFT 161286 1287#define TCP_CHAN_STEER_LO 0xac0c1288#define TCP_CHAN_STEER_HI 0xac101289 1290#define TC_CFG_L1_LOAD_POLICY0 0xAC681291#define TC_CFG_L1_LOAD_POLICY1 0xAC6C1292#define TC_CFG_L1_STORE_POLICY 0xAC701293#define TC_CFG_L2_LOAD_POLICY0 0xAC741294#define TC_CFG_L2_LOAD_POLICY1 0xAC781295#define TC_CFG_L2_STORE_POLICY0 0xAC7C1296#define TC_CFG_L2_STORE_POLICY1 0xAC801297#define TC_CFG_L2_ATOMIC_POLICY 0xAC841298#define TC_CFG_L1_VOLATILE 0xAC881299#define TC_CFG_L2_VOLATILE 0xAC8C1300 1301#define CP_RB0_BASE 0xC1001302#define CP_RB0_CNTL 0xC1041303#define RB_BUFSZ(x) ((x) << 0)1304#define RB_BLKSZ(x) ((x) << 8)1305#define BUF_SWAP_32BIT (2 << 16)1306#define RB_NO_UPDATE (1 << 27)1307#define RB_RPTR_WR_ENA (1 << 31)1308 1309#define CP_RB0_RPTR_ADDR 0xC10C1310#define RB_RPTR_SWAP_32BIT (2 << 0)1311#define CP_RB0_RPTR_ADDR_HI 0xC1101312#define CP_RB0_WPTR 0xC1141313 1314#define CP_DEVICE_ID 0xC12C1315#define CP_ENDIAN_SWAP 0xC1401316#define CP_RB_VMID 0xC1441317 1318#define CP_PFP_UCODE_ADDR 0xC1501319#define CP_PFP_UCODE_DATA 0xC1541320#define CP_ME_RAM_RADDR 0xC1581321#define CP_ME_RAM_WADDR 0xC15C1322#define CP_ME_RAM_DATA 0xC1601323 1324#define CP_CE_UCODE_ADDR 0xC1681325#define CP_CE_UCODE_DATA 0xC16C1326#define CP_MEC_ME1_UCODE_ADDR 0xC1701327#define CP_MEC_ME1_UCODE_DATA 0xC1741328#define CP_MEC_ME2_UCODE_ADDR 0xC1781329#define CP_MEC_ME2_UCODE_DATA 0xC17C1330 1331#define CP_INT_CNTL_RING0 0xC1A81332# define CNTX_BUSY_INT_ENABLE (1 << 19)1333# define CNTX_EMPTY_INT_ENABLE (1 << 20)1334# define PRIV_INSTR_INT_ENABLE (1 << 22)1335# define PRIV_REG_INT_ENABLE (1 << 23)1336# define OPCODE_ERROR_INT_ENABLE (1 << 24)1337# define TIME_STAMP_INT_ENABLE (1 << 26)1338# define CP_RINGID2_INT_ENABLE (1 << 29)1339# define CP_RINGID1_INT_ENABLE (1 << 30)1340# define CP_RINGID0_INT_ENABLE (1 << 31)1341 1342#define CP_INT_STATUS_RING0 0xC1B41343# define PRIV_INSTR_INT_STAT (1 << 22)1344# define PRIV_REG_INT_STAT (1 << 23)1345# define TIME_STAMP_INT_STAT (1 << 26)1346# define CP_RINGID2_INT_STAT (1 << 29)1347# define CP_RINGID1_INT_STAT (1 << 30)1348# define CP_RINGID0_INT_STAT (1 << 31)1349 1350#define CP_MEM_SLP_CNTL 0xC1E41351# define CP_MEM_LS_EN (1 << 0)1352 1353#define CP_CPF_DEBUG 0xC2001354 1355#define CP_PQ_WPTR_POLL_CNTL 0xC20C1356#define WPTR_POLL_EN (1 << 31)1357 1358#define CP_ME1_PIPE0_INT_CNTL 0xC2141359#define CP_ME1_PIPE1_INT_CNTL 0xC2181360#define CP_ME1_PIPE2_INT_CNTL 0xC21C1361#define CP_ME1_PIPE3_INT_CNTL 0xC2201362#define CP_ME2_PIPE0_INT_CNTL 0xC2241363#define CP_ME2_PIPE1_INT_CNTL 0xC2281364#define CP_ME2_PIPE2_INT_CNTL 0xC22C1365#define CP_ME2_PIPE3_INT_CNTL 0xC2301366# define DEQUEUE_REQUEST_INT_ENABLE (1 << 13)1367# define WRM_POLL_TIMEOUT_INT_ENABLE (1 << 17)1368# define PRIV_REG_INT_ENABLE (1 << 23)1369# define TIME_STAMP_INT_ENABLE (1 << 26)1370# define GENERIC2_INT_ENABLE (1 << 29)1371# define GENERIC1_INT_ENABLE (1 << 30)1372# define GENERIC0_INT_ENABLE (1 << 31)1373#define CP_ME1_PIPE0_INT_STATUS 0xC2141374#define CP_ME1_PIPE1_INT_STATUS 0xC2181375#define CP_ME1_PIPE2_INT_STATUS 0xC21C1376#define CP_ME1_PIPE3_INT_STATUS 0xC2201377#define CP_ME2_PIPE0_INT_STATUS 0xC2241378#define CP_ME2_PIPE1_INT_STATUS 0xC2281379#define CP_ME2_PIPE2_INT_STATUS 0xC22C1380#define CP_ME2_PIPE3_INT_STATUS 0xC2301381# define DEQUEUE_REQUEST_INT_STATUS (1 << 13)1382# define WRM_POLL_TIMEOUT_INT_STATUS (1 << 17)1383# define PRIV_REG_INT_STATUS (1 << 23)1384# define TIME_STAMP_INT_STATUS (1 << 26)1385# define GENERIC2_INT_STATUS (1 << 29)1386# define GENERIC1_INT_STATUS (1 << 30)1387# define GENERIC0_INT_STATUS (1 << 31)1388 1389#define CP_MAX_CONTEXT 0xC2B81390 1391#define CP_RB0_BASE_HI 0xC2C41392 1393#define RLC_CNTL 0xC3001394# define RLC_ENABLE (1 << 0)1395 1396#define RLC_MC_CNTL 0xC30C1397 1398#define RLC_MEM_SLP_CNTL 0xC3181399# define RLC_MEM_LS_EN (1 << 0)1400 1401#define RLC_LB_CNTR_MAX 0xC3481402 1403#define RLC_LB_CNTL 0xC3641404# define LOAD_BALANCE_ENABLE (1 << 0)1405 1406#define RLC_LB_CNTR_INIT 0xC36C1407 1408#define RLC_SAVE_AND_RESTORE_BASE 0xC3741409#define RLC_DRIVER_DMA_STATUS 0xC378 /* dGPU */1410#define RLC_CP_TABLE_RESTORE 0xC378 /* APU */1411#define RLC_PG_DELAY_2 0xC37C1412 1413#define RLC_GPM_UCODE_ADDR 0xC3881414#define RLC_GPM_UCODE_DATA 0xC38C1415#define RLC_GPU_CLOCK_COUNT_LSB 0xC3901416#define RLC_GPU_CLOCK_COUNT_MSB 0xC3941417#define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC3981418#define RLC_UCODE_CNTL 0xC39C1419 1420#define RLC_GPM_STAT 0xC4001421# define RLC_GPM_BUSY (1 << 0)1422# define GFX_POWER_STATUS (1 << 1)1423# define GFX_CLOCK_STATUS (1 << 2)1424 1425#define RLC_PG_CNTL 0xC40C1426# define GFX_PG_ENABLE (1 << 0)1427# define GFX_PG_SRC (1 << 1)1428# define DYN_PER_CU_PG_ENABLE (1 << 2)1429# define STATIC_PER_CU_PG_ENABLE (1 << 3)1430# define DISABLE_GDS_PG (1 << 13)1431# define DISABLE_CP_PG (1 << 15)1432# define SMU_CLK_SLOWDOWN_ON_PU_ENABLE (1 << 17)1433# define SMU_CLK_SLOWDOWN_ON_PD_ENABLE (1 << 18)1434 1435#define RLC_CGTT_MGCG_OVERRIDE 0xC4201436#define RLC_CGCG_CGLS_CTRL 0xC4241437# define CGCG_EN (1 << 0)1438# define CGLS_EN (1 << 1)1439 1440#define RLC_PG_DELAY 0xC4341441 1442#define RLC_LB_INIT_CU_MASK 0xC43C1443 1444#define RLC_LB_PARAMS 0xC4441445 1446#define RLC_PG_AO_CU_MASK 0xC44C1447 1448#define RLC_MAX_PG_CU 0xC4501449# define MAX_PU_CU(x) ((x) << 0)1450# define MAX_PU_CU_MASK (0xff << 0)1451#define RLC_AUTO_PG_CTRL 0xC4541452# define AUTO_PG_EN (1 << 0)1453# define GRBM_REG_SGIT(x) ((x) << 3)1454# define GRBM_REG_SGIT_MASK (0xffff << 3)1455 1456#define RLC_SERDES_WR_CU_MASTER_MASK 0xC4741457#define RLC_SERDES_WR_NONCU_MASTER_MASK 0xC4781458#define RLC_SERDES_WR_CTRL 0xC47C1459#define BPM_ADDR(x) ((x) << 0)1460#define BPM_ADDR_MASK (0xff << 0)1461#define CGLS_ENABLE (1 << 16)1462#define CGCG_OVERRIDE_0 (1 << 20)1463#define MGCG_OVERRIDE_0 (1 << 22)1464#define MGCG_OVERRIDE_1 (1 << 23)1465 1466#define RLC_SERDES_CU_MASTER_BUSY 0xC4841467#define RLC_SERDES_NONCU_MASTER_BUSY 0xC4881468# define SE_MASTER_BUSY_MASK 0x0000ffff1469# define GC_MASTER_BUSY (1 << 16)1470# define TC0_MASTER_BUSY (1 << 17)1471# define TC1_MASTER_BUSY (1 << 18)1472 1473#define RLC_GPM_SCRATCH_ADDR 0xC4B01474#define RLC_GPM_SCRATCH_DATA 0xC4B41475 1476#define RLC_GPR_REG2 0xC4E81477#define REQ 0x000000011478#define MESSAGE(x) ((x) << 1)1479#define MESSAGE_MASK 0x0000001e1480#define MSG_ENTER_RLC_SAFE_MODE 11481#define MSG_EXIT_RLC_SAFE_MODE 01482 1483#define CP_HPD_EOP_BASE_ADDR 0xC9041484#define CP_HPD_EOP_BASE_ADDR_HI 0xC9081485#define CP_HPD_EOP_VMID 0xC90C1486#define CP_HPD_EOP_CONTROL 0xC9101487#define EOP_SIZE(x) ((x) << 0)1488#define EOP_SIZE_MASK (0x3f << 0)1489#define CP_MQD_BASE_ADDR 0xC9141490#define CP_MQD_BASE_ADDR_HI 0xC9181491#define CP_HQD_ACTIVE 0xC91C1492#define CP_HQD_VMID 0xC9201493 1494#define CP_HQD_PERSISTENT_STATE 0xC924u1495#define DEFAULT_CP_HQD_PERSISTENT_STATE (0x33U << 8)1496 1497#define CP_HQD_PIPE_PRIORITY 0xC928u1498#define CP_HQD_QUEUE_PRIORITY 0xC92Cu1499#define CP_HQD_QUANTUM 0xC930u1500#define QUANTUM_EN 1U1501#define QUANTUM_SCALE_1MS (1U << 4)1502#define QUANTUM_DURATION(x) ((x) << 8)1503 1504#define CP_HQD_PQ_BASE 0xC9341505#define CP_HQD_PQ_BASE_HI 0xC9381506#define CP_HQD_PQ_RPTR 0xC93C1507#define CP_HQD_PQ_RPTR_REPORT_ADDR 0xC9401508#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI 0xC9441509#define CP_HQD_PQ_WPTR_POLL_ADDR 0xC9481510#define CP_HQD_PQ_WPTR_POLL_ADDR_HI 0xC94C1511#define CP_HQD_PQ_DOORBELL_CONTROL 0xC9501512#define DOORBELL_OFFSET(x) ((x) << 2)1513#define DOORBELL_OFFSET_MASK (0x1fffff << 2)1514#define DOORBELL_SOURCE (1 << 28)1515#define DOORBELL_SCHD_HIT (1 << 29)1516#define DOORBELL_EN (1 << 30)1517#define DOORBELL_HIT (1 << 31)1518#define CP_HQD_PQ_WPTR 0xC9541519#define CP_HQD_PQ_CONTROL 0xC9581520#define QUEUE_SIZE(x) ((x) << 0)1521#define QUEUE_SIZE_MASK (0x3f << 0)1522#define RPTR_BLOCK_SIZE(x) ((x) << 8)1523#define RPTR_BLOCK_SIZE_MASK (0x3f << 8)1524#define PQ_VOLATILE (1 << 26)1525#define NO_UPDATE_RPTR (1 << 27)1526#define UNORD_DISPATCH (1 << 28)1527#define ROQ_PQ_IB_FLIP (1 << 29)1528#define PRIV_STATE (1 << 30)1529#define KMD_QUEUE (1 << 31)1530 1531#define CP_HQD_IB_BASE_ADDR 0xC95Cu1532#define CP_HQD_IB_BASE_ADDR_HI 0xC960u1533#define CP_HQD_IB_RPTR 0xC964u1534#define CP_HQD_IB_CONTROL 0xC968u1535#define IB_ATC_EN (1U << 23)1536#define DEFAULT_MIN_IB_AVAIL_SIZE (3U << 20)1537 1538#define CP_HQD_DEQUEUE_REQUEST 0xC9741539#define DEQUEUE_REQUEST_DRAIN 11540#define DEQUEUE_REQUEST_RESET 21541 1542#define CP_MQD_CONTROL 0xC99C1543#define MQD_VMID(x) ((x) << 0)1544#define MQD_VMID_MASK (0xf << 0)1545 1546#define CP_HQD_SEMA_CMD 0xC97Cu1547#define CP_HQD_MSG_TYPE 0xC980u1548#define CP_HQD_ATOMIC0_PREOP_LO 0xC984u1549#define CP_HQD_ATOMIC0_PREOP_HI 0xC988u1550#define CP_HQD_ATOMIC1_PREOP_LO 0xC98Cu1551#define CP_HQD_ATOMIC1_PREOP_HI 0xC990u1552#define CP_HQD_HQ_SCHEDULER0 0xC994u1553#define CP_HQD_HQ_SCHEDULER1 0xC998u1554 1555#define SH_STATIC_MEM_CONFIG 0x9604u1556 1557#define DB_RENDER_CONTROL 0x280001558 1559#define PA_SC_RASTER_CONFIG 0x283501560# define RASTER_CONFIG_RB_MAP_0 01561# define RASTER_CONFIG_RB_MAP_1 11562# define RASTER_CONFIG_RB_MAP_2 21563# define RASTER_CONFIG_RB_MAP_3 31564#define PKR_MAP(x) ((x) << 8)1565 1566#define VGT_EVENT_INITIATOR 0x28a901567# define SAMPLE_STREAMOUTSTATS1 (1 << 0)1568# define SAMPLE_STREAMOUTSTATS2 (2 << 0)1569# define SAMPLE_STREAMOUTSTATS3 (3 << 0)1570# define CACHE_FLUSH_TS (4 << 0)1571# define CACHE_FLUSH (6 << 0)1572# define CS_PARTIAL_FLUSH (7 << 0)1573# define VGT_STREAMOUT_RESET (10 << 0)1574# define END_OF_PIPE_INCR_DE (11 << 0)1575# define END_OF_PIPE_IB_END (12 << 0)1576# define RST_PIX_CNT (13 << 0)1577# define VS_PARTIAL_FLUSH (15 << 0)1578# define PS_PARTIAL_FLUSH (16 << 0)1579# define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0)1580# define ZPASS_DONE (21 << 0)1581# define CACHE_FLUSH_AND_INV_EVENT (22 << 0)1582# define PERFCOUNTER_START (23 << 0)1583# define PERFCOUNTER_STOP (24 << 0)1584# define PIPELINESTAT_START (25 << 0)1585# define PIPELINESTAT_STOP (26 << 0)1586# define PERFCOUNTER_SAMPLE (27 << 0)1587# define SAMPLE_PIPELINESTAT (30 << 0)1588# define SO_VGT_STREAMOUT_FLUSH (31 << 0)1589# define SAMPLE_STREAMOUTSTATS (32 << 0)1590# define RESET_VTX_CNT (33 << 0)1591# define VGT_FLUSH (36 << 0)1592# define BOTTOM_OF_PIPE_TS (40 << 0)1593# define DB_CACHE_FLUSH_AND_INV (42 << 0)1594# define FLUSH_AND_INV_DB_DATA_TS (43 << 0)1595# define FLUSH_AND_INV_DB_META (44 << 0)1596# define FLUSH_AND_INV_CB_DATA_TS (45 << 0)1597# define FLUSH_AND_INV_CB_META (46 << 0)1598# define CS_DONE (47 << 0)1599# define PS_DONE (48 << 0)1600# define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0)1601# define THREAD_TRACE_START (51 << 0)1602# define THREAD_TRACE_STOP (52 << 0)1603# define THREAD_TRACE_FLUSH (54 << 0)1604# define THREAD_TRACE_FINISH (55 << 0)1605# define PIXEL_PIPE_STAT_CONTROL (56 << 0)1606# define PIXEL_PIPE_STAT_DUMP (57 << 0)1607# define PIXEL_PIPE_STAT_RESET (58 << 0)1608 1609#define SCRATCH_REG0 0x301001610#define SCRATCH_REG1 0x301041611#define SCRATCH_REG2 0x301081612#define SCRATCH_REG3 0x3010C1613#define SCRATCH_REG4 0x301101614#define SCRATCH_REG5 0x301141615#define SCRATCH_REG6 0x301181616#define SCRATCH_REG7 0x3011C1617 1618#define SCRATCH_UMSK 0x301401619#define SCRATCH_ADDR 0x301441620 1621#define CP_SEM_WAIT_TIMER 0x301BC1622 1623#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x301C81624 1625#define CP_WAIT_REG_MEM_TIMEOUT 0x301D01626 1627#define GRBM_GFX_INDEX 0x308001628#define INSTANCE_INDEX(x) ((x) << 0)1629#define SH_INDEX(x) ((x) << 8)1630#define SE_INDEX(x) ((x) << 16)1631#define SH_BROADCAST_WRITES (1 << 29)1632#define INSTANCE_BROADCAST_WRITES (1 << 30)1633#define SE_BROADCAST_WRITES (1 << 31)1634 1635#define VGT_ESGS_RING_SIZE 0x309001636#define VGT_GSVS_RING_SIZE 0x309041637#define VGT_PRIMITIVE_TYPE 0x309081638#define VGT_INDEX_TYPE 0x3090C1639 1640#define VGT_NUM_INDICES 0x309301641#define VGT_NUM_INSTANCES 0x309341642#define VGT_TF_RING_SIZE 0x309381643#define VGT_HS_OFFCHIP_PARAM 0x3093C1644#define VGT_TF_MEMORY_BASE 0x309401645 1646#define PA_SU_LINE_STIPPLE_VALUE 0x30a001647#define PA_SC_LINE_STIPPLE_STATE 0x30a041648 1649#define SQC_CACHES 0x30d201650 1651#define CP_PERFMON_CNTL 0x360201652 1653#define CGTS_SM_CTRL_REG 0x3c0001654#define SM_MODE(x) ((x) << 17)1655#define SM_MODE_MASK (0x7 << 17)1656#define SM_MODE_ENABLE (1 << 20)1657#define CGTS_OVERRIDE (1 << 21)1658#define CGTS_LS_OVERRIDE (1 << 22)1659#define ON_MONITOR_ADD_EN (1 << 23)1660#define ON_MONITOR_ADD(x) ((x) << 24)1661#define ON_MONITOR_ADD_MASK (0xff << 24)1662 1663#define CGTS_TCC_DISABLE 0x3c00c1664#define CGTS_USER_TCC_DISABLE 0x3c0101665#define TCC_DISABLE_MASK 0xFFFF00001666#define TCC_DISABLE_SHIFT 161667 1668#define CB_CGTT_SCLK_CTRL 0x3c2a01669 1670/*1671 * PM41672 */1673#define PACKET_TYPE0 01674#define PACKET_TYPE1 11675#define PACKET_TYPE2 21676#define PACKET_TYPE3 31677 1678#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)1679#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)1680#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)1681#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)1682#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \1683 (((reg) >> 2) & 0xFFFF) | \1684 ((n) & 0x3FFF) << 16)1685#define CP_PACKET2 0x800000001686#define PACKET2_PAD_SHIFT 01687#define PACKET2_PAD_MASK (0x3fffffff << 0)1688 1689#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))1690 1691#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \1692 (((op) & 0xFF) << 8) | \1693 ((n) & 0x3FFF) << 16)1694 1695#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)1696 1697/* Packet 3 types */1698#define PACKET3_NOP 0x101699#define PACKET3_SET_BASE 0x111700#define PACKET3_BASE_INDEX(x) ((x) << 0)1701#define CE_PARTITION_BASE 31702#define PACKET3_CLEAR_STATE 0x121703#define PACKET3_INDEX_BUFFER_SIZE 0x131704#define PACKET3_DISPATCH_DIRECT 0x151705#define PACKET3_DISPATCH_INDIRECT 0x161706#define PACKET3_ATOMIC_GDS 0x1D1707#define PACKET3_ATOMIC_MEM 0x1E1708#define PACKET3_OCCLUSION_QUERY 0x1F1709#define PACKET3_SET_PREDICATION 0x201710#define PACKET3_REG_RMW 0x211711#define PACKET3_COND_EXEC 0x221712#define PACKET3_PRED_EXEC 0x231713#define PACKET3_DRAW_INDIRECT 0x241714#define PACKET3_DRAW_INDEX_INDIRECT 0x251715#define PACKET3_INDEX_BASE 0x261716#define PACKET3_DRAW_INDEX_2 0x271717#define PACKET3_CONTEXT_CONTROL 0x281718#define PACKET3_INDEX_TYPE 0x2A1719#define PACKET3_DRAW_INDIRECT_MULTI 0x2C1720#define PACKET3_DRAW_INDEX_AUTO 0x2D1721#define PACKET3_NUM_INSTANCES 0x2F1722#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x301723#define PACKET3_INDIRECT_BUFFER_CONST 0x331724#define PACKET3_STRMOUT_BUFFER_UPDATE 0x341725#define PACKET3_DRAW_INDEX_OFFSET_2 0x351726#define PACKET3_DRAW_PREAMBLE 0x361727#define PACKET3_WRITE_DATA 0x371728#define WRITE_DATA_DST_SEL(x) ((x) << 8)1729 /* 0 - register1730 * 1 - memory (sync - via GRBM)1731 * 2 - gl21732 * 3 - gds1733 * 4 - reserved1734 * 5 - memory (async - direct)1735 */1736#define WR_ONE_ADDR (1 << 16)1737#define WR_CONFIRM (1 << 20)1738#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)1739 /* 0 - LRU1740 * 1 - Stream1741 */1742#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)1743 /* 0 - me1744 * 1 - pfp1745 * 2 - ce1746 */1747#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x381748#define PACKET3_MEM_SEMAPHORE 0x391749# define PACKET3_SEM_USE_MAILBOX (0x1 << 16)1750# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */1751# define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */1752# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)1753# define PACKET3_SEM_SEL_WAIT (0x7 << 29)1754#define PACKET3_COPY_DW 0x3B1755#define PACKET3_WAIT_REG_MEM 0x3C1756#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)1757 /* 0 - always1758 * 1 - <1759 * 2 - <=1760 * 3 - ==1761 * 4 - !=1762 * 5 - >=1763 * 6 - >1764 */1765#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)1766 /* 0 - reg1767 * 1 - mem1768 */1769#define WAIT_REG_MEM_OPERATION(x) ((x) << 6)1770 /* 0 - wait_reg_mem1771 * 1 - wr_wait_wr_reg1772 */1773#define WAIT_REG_MEM_ENGINE(x) ((x) << 8)1774 /* 0 - me1775 * 1 - pfp1776 */1777#define PACKET3_INDIRECT_BUFFER 0x3F1778#define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22)1779#define INDIRECT_BUFFER_VALID (1 << 23)1780#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)1781 /* 0 - LRU1782 * 1 - Stream1783 * 2 - Bypass1784 */1785#define PACKET3_COPY_DATA 0x401786#define PACKET3_PFP_SYNC_ME 0x421787#define PACKET3_SURFACE_SYNC 0x431788# define PACKET3_DEST_BASE_0_ENA (1 << 0)1789# define PACKET3_DEST_BASE_1_ENA (1 << 1)1790# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)1791# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)1792# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)1793# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)1794# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)1795# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)1796# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)1797# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)1798# define PACKET3_DB_DEST_BASE_ENA (1 << 14)1799# define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15)1800# define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */1801# define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */1802# define PACKET3_DEST_BASE_2_ENA (1 << 19)1803# define PACKET3_DEST_BASE_3_ENA (1 << 21)1804# define PACKET3_TCL1_ACTION_ENA (1 << 22)1805# define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */1806# define PACKET3_CB_ACTION_ENA (1 << 25)1807# define PACKET3_DB_ACTION_ENA (1 << 26)1808# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)1809# define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28)1810# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)1811#define PACKET3_COND_WRITE 0x451812#define PACKET3_EVENT_WRITE 0x461813#define EVENT_TYPE(x) ((x) << 0)1814#define EVENT_INDEX(x) ((x) << 8)1815 /* 0 - any non-TS event1816 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*1817 * 2 - SAMPLE_PIPELINESTAT1818 * 3 - SAMPLE_STREAMOUTSTAT*1819 * 4 - *S_PARTIAL_FLUSH1820 * 5 - EOP events1821 * 6 - EOS events1822 */1823#define PACKET3_EVENT_WRITE_EOP 0x471824#define EOP_TCL1_VOL_ACTION_EN (1 << 12)1825#define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */1826#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */1827#define EOP_TCL1_ACTION_EN (1 << 16)1828#define EOP_TC_ACTION_EN (1 << 17) /* L2 */1829#define EOP_TCL2_VOLATILE (1 << 24)1830#define EOP_CACHE_POLICY(x) ((x) << 25)1831 /* 0 - LRU1832 * 1 - Stream1833 * 2 - Bypass1834 */1835#define DATA_SEL(x) ((x) << 29)1836 /* 0 - discard1837 * 1 - send low 32bit data1838 * 2 - send 64bit data1839 * 3 - send 64bit GPU counter value1840 * 4 - send 64bit sys counter value1841 */1842#define INT_SEL(x) ((x) << 24)1843 /* 0 - none1844 * 1 - interrupt only (DATA_SEL = 0)1845 * 2 - interrupt when data write is confirmed1846 */1847#define DST_SEL(x) ((x) << 16)1848 /* 0 - MC1849 * 1 - TC/L21850 */1851#define PACKET3_EVENT_WRITE_EOS 0x481852#define PACKET3_RELEASE_MEM 0x491853#define PACKET3_PREAMBLE_CNTL 0x4A1854# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)1855# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)1856#define PACKET3_DMA_DATA 0x501857/* 1. header1858 * 2. CONTROL1859 * 3. SRC_ADDR_LO or DATA [31:0]1860 * 4. SRC_ADDR_HI [31:0]1861 * 5. DST_ADDR_LO [31:0]1862 * 6. DST_ADDR_HI [7:0]1863 * 7. COMMAND [30:21] | BYTE_COUNT [20:0]1864 */1865/* CONTROL */1866# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0)1867 /* 0 - ME1868 * 1 - PFP1869 */1870# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)1871 /* 0 - LRU1872 * 1 - Stream1873 * 2 - Bypass1874 */1875# define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15)1876# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20)1877 /* 0 - DST_ADDR using DAS1878 * 1 - GDS1879 * 3 - DST_ADDR using L21880 */1881# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)1882 /* 0 - LRU1883 * 1 - Stream1884 * 2 - Bypass1885 */1886# define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27)1887# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29)1888 /* 0 - SRC_ADDR using SAS1889 * 1 - GDS1890 * 2 - DATA1891 * 3 - SRC_ADDR using L21892 */1893# define PACKET3_DMA_DATA_CP_SYNC (1 << 31)1894/* COMMAND */1895# define PACKET3_DMA_DATA_DIS_WC (1 << 21)1896# define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22)1897 /* 0 - none1898 * 1 - 8 in 161899 * 2 - 8 in 321900 * 3 - 8 in 641901 */1902# define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24)1903 /* 0 - none1904 * 1 - 8 in 161905 * 2 - 8 in 321906 * 3 - 8 in 641907 */1908# define PACKET3_DMA_DATA_CMD_SAS (1 << 26)1909 /* 0 - memory1910 * 1 - register1911 */1912# define PACKET3_DMA_DATA_CMD_DAS (1 << 27)1913 /* 0 - memory1914 * 1 - register1915 */1916# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28)1917# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29)1918# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30)1919#define PACKET3_AQUIRE_MEM 0x581920#define PACKET3_REWIND 0x591921#define PACKET3_LOAD_UCONFIG_REG 0x5E1922#define PACKET3_LOAD_SH_REG 0x5F1923#define PACKET3_LOAD_CONFIG_REG 0x601924#define PACKET3_LOAD_CONTEXT_REG 0x611925#define PACKET3_SET_CONFIG_REG 0x681926#define PACKET3_SET_CONFIG_REG_START 0x000080001927#define PACKET3_SET_CONFIG_REG_END 0x0000b0001928#define PACKET3_SET_CONTEXT_REG 0x691929#define PACKET3_SET_CONTEXT_REG_START 0x000280001930#define PACKET3_SET_CONTEXT_REG_END 0x000290001931#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x731932#define PACKET3_SET_SH_REG 0x761933#define PACKET3_SET_SH_REG_START 0x0000b0001934#define PACKET3_SET_SH_REG_END 0x0000c0001935#define PACKET3_SET_SH_REG_OFFSET 0x771936#define PACKET3_SET_QUEUE_REG 0x781937#define PACKET3_SET_UCONFIG_REG 0x791938#define PACKET3_SET_UCONFIG_REG_START 0x000300001939#define PACKET3_SET_UCONFIG_REG_END 0x000310001940#define PACKET3_SCRATCH_RAM_WRITE 0x7D1941#define PACKET3_SCRATCH_RAM_READ 0x7E1942#define PACKET3_LOAD_CONST_RAM 0x801943#define PACKET3_WRITE_CONST_RAM 0x811944#define PACKET3_DUMP_CONST_RAM 0x831945#define PACKET3_INCREMENT_CE_COUNTER 0x841946#define PACKET3_INCREMENT_DE_COUNTER 0x851947#define PACKET3_WAIT_ON_CE_COUNTER 0x861948#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x881949#define PACKET3_SWITCH_BUFFER 0x8B1950 1951/* SDMA - first instance at 0xd000, second at 0xd800 */1952#define SDMA0_REGISTER_OFFSET 0x0 /* not a register */1953#define SDMA1_REGISTER_OFFSET 0x800 /* not a register */1954 1955#define SDMA0_UCODE_ADDR 0xD0001956#define SDMA0_UCODE_DATA 0xD0041957#define SDMA0_POWER_CNTL 0xD0081958#define SDMA0_CLK_CTRL 0xD00C1959 1960#define SDMA0_CNTL 0xD0101961# define TRAP_ENABLE (1 << 0)1962# define SEM_INCOMPLETE_INT_ENABLE (1 << 1)1963# define SEM_WAIT_INT_ENABLE (1 << 2)1964# define DATA_SWAP_ENABLE (1 << 3)1965# define FENCE_SWAP_ENABLE (1 << 4)1966# define AUTO_CTXSW_ENABLE (1 << 18)1967# define CTXEMPTY_INT_ENABLE (1 << 28)1968 1969#define SDMA0_TILING_CONFIG 0xD0181970 1971#define SDMA0_SEM_INCOMPLETE_TIMER_CNTL 0xD0201972#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0xD0241973 1974#define SDMA0_STATUS_REG 0xd0341975# define SDMA_IDLE (1 << 0)1976 1977#define SDMA0_ME_CNTL 0xD0481978# define SDMA_HALT (1 << 0)1979 1980#define SDMA0_GFX_RB_CNTL 0xD2001981# define SDMA_RB_ENABLE (1 << 0)1982# define SDMA_RB_SIZE(x) ((x) << 1) /* log2 */1983# define SDMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */1984# define SDMA_RPTR_WRITEBACK_ENABLE (1 << 12)1985# define SDMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */1986# define SDMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */1987#define SDMA0_GFX_RB_BASE 0xD2041988#define SDMA0_GFX_RB_BASE_HI 0xD2081989#define SDMA0_GFX_RB_RPTR 0xD20C1990#define SDMA0_GFX_RB_WPTR 0xD2101991 1992#define SDMA0_GFX_RB_RPTR_ADDR_HI 0xD2201993#define SDMA0_GFX_RB_RPTR_ADDR_LO 0xD2241994#define SDMA0_GFX_IB_CNTL 0xD2281995# define SDMA_IB_ENABLE (1 << 0)1996# define SDMA_IB_SWAP_ENABLE (1 << 4)1997# define SDMA_SWITCH_INSIDE_IB (1 << 8)1998# define SDMA_CMD_VMID(x) ((x) << 16)1999 2000#define SDMA0_GFX_VIRTUAL_ADDR 0xD29C2001#define SDMA0_GFX_APE1_CNTL 0xD2A02002 2003#define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \2004 (((sub_op) & 0xFF) << 8) | \2005 (((op) & 0xFF) << 0))2006/* sDMA opcodes */2007#define SDMA_OPCODE_NOP 02008#define SDMA_OPCODE_COPY 12009# define SDMA_COPY_SUB_OPCODE_LINEAR 02010# define SDMA_COPY_SUB_OPCODE_TILED 12011# define SDMA_COPY_SUB_OPCODE_SOA 32012# define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 42013# define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 52014# define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 62015#define SDMA_OPCODE_WRITE 22016# define SDMA_WRITE_SUB_OPCODE_LINEAR 02017# define SDMA_WRITE_SUB_OPCODE_TILED 12018#define SDMA_OPCODE_INDIRECT_BUFFER 42019#define SDMA_OPCODE_FENCE 52020#define SDMA_OPCODE_TRAP 62021#define SDMA_OPCODE_SEMAPHORE 72022# define SDMA_SEMAPHORE_EXTRA_O (1 << 13)2023 /* 0 - increment2024 * 1 - write 12025 */2026# define SDMA_SEMAPHORE_EXTRA_S (1 << 14)2027 /* 0 - wait2028 * 1 - signal2029 */2030# define SDMA_SEMAPHORE_EXTRA_M (1 << 15)2031 /* mailbox */2032#define SDMA_OPCODE_POLL_REG_MEM 82033# define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10)2034 /* 0 - wait_reg_mem2035 * 1 - wr_wait_wr_reg2036 */2037# define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12)2038 /* 0 - always2039 * 1 - <2040 * 2 - <=2041 * 3 - ==2042 * 4 - !=2043 * 5 - >=2044 * 6 - >2045 */2046# define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15)2047 /* 0 = register2048 * 1 = memory2049 */2050#define SDMA_OPCODE_COND_EXEC 92051#define SDMA_OPCODE_CONSTANT_FILL 112052# define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14)2053 /* 0 = byte fill2054 * 2 = DW fill2055 */2056#define SDMA_OPCODE_GENERATE_PTE_PDE 122057#define SDMA_OPCODE_TIMESTAMP 132058# define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 02059# define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 12060# define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 22061#define SDMA_OPCODE_SRBM_WRITE 142062# define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12)2063 /* byte mask */2064 2065/* UVD */2066 2067#define UVD_UDEC_ADDR_CONFIG 0xef4c2068#define UVD_UDEC_DB_ADDR_CONFIG 0xef502069#define UVD_UDEC_DBW_ADDR_CONFIG 0xef542070#define UVD_NO_OP 0xeffc2071 2072#define UVD_LMI_EXT40_ADDR 0xf4982073#define UVD_GP_SCRATCH4 0xf4e02074#define UVD_LMI_ADDR_EXT 0xf5942075#define UVD_VCPU_CACHE_OFFSET0 0xf6082076#define UVD_VCPU_CACHE_SIZE0 0xf60c2077#define UVD_VCPU_CACHE_OFFSET1 0xf6102078#define UVD_VCPU_CACHE_SIZE1 0xf6142079#define UVD_VCPU_CACHE_OFFSET2 0xf6182080#define UVD_VCPU_CACHE_SIZE2 0xf61c2081 2082#define UVD_RBC_RB_RPTR 0xf6902083#define UVD_RBC_RB_WPTR 0xf6942084 2085#define UVD_CGC_CTRL 0xF4B02086# define DCM (1 << 0)2087# define CG_DT(x) ((x) << 2)2088# define CG_DT_MASK (0xf << 2)2089# define CLK_OD(x) ((x) << 6)2090# define CLK_OD_MASK (0x1f << 6)2091 2092#define UVD_STATUS 0xf6bc2093 2094/* UVD clocks */2095 2096#define CG_DCLK_CNTL 0xC050009C2097# define DCLK_DIVIDER_MASK 0x7f2098# define DCLK_DIR_CNTL_EN (1 << 8)2099#define CG_DCLK_STATUS 0xC05000A02100# define DCLK_STATUS (1 << 0)2101#define CG_VCLK_CNTL 0xC05000A42102#define CG_VCLK_STATUS 0xC05000A82103 2104/* UVD CTX indirect */2105#define UVD_CGC_MEM_CTRL 0xC02106 2107/* VCE */2108 2109#define VCE_VCPU_CACHE_OFFSET0 0x200242110#define VCE_VCPU_CACHE_SIZE0 0x200282111#define VCE_VCPU_CACHE_OFFSET1 0x2002c2112#define VCE_VCPU_CACHE_SIZE1 0x200302113#define VCE_VCPU_CACHE_OFFSET2 0x200342114#define VCE_VCPU_CACHE_SIZE2 0x200382115#define VCE_RB_RPTR2 0x201782116#define VCE_RB_WPTR2 0x2017c2117#define VCE_RB_RPTR 0x2018c2118#define VCE_RB_WPTR 0x201902119#define VCE_CLOCK_GATING_A 0x202f82120# define CGC_CLK_GATE_DLY_TIMER_MASK (0xf << 0)2121# define CGC_CLK_GATE_DLY_TIMER(x) ((x) << 0)2122# define CGC_CLK_GATER_OFF_DLY_TIMER_MASK (0xff << 4)2123# define CGC_CLK_GATER_OFF_DLY_TIMER(x) ((x) << 4)2124# define CGC_UENC_WAIT_AWAKE (1 << 18)2125#define VCE_CLOCK_GATING_B 0x202fc2126#define VCE_CGTT_CLK_OVERRIDE 0x207a02127#define VCE_UENC_CLOCK_GATING 0x207bc2128# define CLOCK_ON_DELAY_MASK (0xf << 0)2129# define CLOCK_ON_DELAY(x) ((x) << 0)2130# define CLOCK_OFF_DELAY_MASK (0xff << 4)2131# define CLOCK_OFF_DELAY(x) ((x) << 4)2132#define VCE_UENC_REG_CLOCK_GATING 0x207c02133#define VCE_SYS_INT_EN 0x213002134# define VCE_SYS_INT_TRAP_INTERRUPT_EN (1 << 3)2135#define VCE_LMI_VCPU_CACHE_40BIT_BAR 0x2145c2136#define VCE_LMI_CTRL2 0x214742137#define VCE_LMI_CTRL 0x214982138#define VCE_LMI_VM_CTRL 0x214a02139#define VCE_LMI_SWAP_CNTL 0x214b42140#define VCE_LMI_SWAP_CNTL1 0x214b82141#define VCE_LMI_CACHE_CTRL 0x214f42142 2143#define VCE_CMD_NO_OP 0x000000002144#define VCE_CMD_END 0x000000012145#define VCE_CMD_IB 0x000000022146#define VCE_CMD_FENCE 0x000000032147#define VCE_CMD_TRAP 0x000000042148#define VCE_CMD_IB_AUTO 0x000000052149#define VCE_CMD_SEMAPHORE 0x000000062150 2151#define ATC_VMID_PASID_MAPPING_UPDATE_STATUS 0x3398u2152#define ATC_VMID0_PASID_MAPPING 0x339Cu2153#define ATC_VMID_PASID_MAPPING_PASID_MASK (0xFFFF)2154#define ATC_VMID_PASID_MAPPING_PASID_SHIFT 02155#define ATC_VMID_PASID_MAPPING_VALID_MASK (0x1 << 31)2156#define ATC_VMID_PASID_MAPPING_VALID_SHIFT 312157 2158#define ATC_VM_APERTURE0_CNTL 0x3310u2159#define ATS_ACCESS_MODE_NEVER 02160#define ATS_ACCESS_MODE_ALWAYS 12161 2162#define ATC_VM_APERTURE0_CNTL2 0x3318u2163#define ATC_VM_APERTURE0_HIGH_ADDR 0x3308u2164#define ATC_VM_APERTURE0_LOW_ADDR 0x3300u2165#define ATC_VM_APERTURE1_CNTL 0x3314u2166#define ATC_VM_APERTURE1_CNTL2 0x331Cu2167#define ATC_VM_APERTURE1_HIGH_ADDR 0x330Cu2168#define ATC_VM_APERTURE1_LOW_ADDR 0x3304u2169 2170#define IH_VMID_0_LUT 0x3D40u2171 2172#endif2173