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1/*2 * Copyright 2013 Advanced Micro Devices, Inc.3 * Copyright 2014 Rafał Miłecki4 *5 * Permission is hereby granted, free of charge, to any person obtaining a6 * copy of this software and associated documentation files (the "Software"),7 * to deal in the Software without restriction, including without limitation8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,9 * and/or sell copies of the Software, and to permit persons to whom the10 * Software is furnished to do so, subject to the following conditions:11 *12 * The above copyright notice and this permission notice shall be included in13 * all copies or substantial portions of the Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR21 * OTHER DEALINGS IN THE SOFTWARE.22 */23#include <linux/hdmi.h>24#include <drm/drm_edid.h>25 26#include "radeon.h"27#include "radeon_asic.h"28#include "radeon_audio.h"29#include "r600d.h"30 31void dce3_2_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,32 u8 *sadb, int sad_count)33{34 struct radeon_device *rdev = encoder->dev->dev_private;35 u32 tmp;36 37 /* program the speaker allocation */38 tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);39 tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);40 /* set HDMI mode */41 tmp |= HDMI_CONNECTION;42 if (sad_count)43 tmp |= SPEAKER_ALLOCATION(sadb[0]);44 else45 tmp |= SPEAKER_ALLOCATION(5); /* stereo */46 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);47}48 49void dce3_2_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,50 u8 *sadb, int sad_count)51{52 struct radeon_device *rdev = encoder->dev->dev_private;53 u32 tmp;54 55 /* program the speaker allocation */56 tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);57 tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);58 /* set DP mode */59 tmp |= DP_CONNECTION;60 if (sad_count)61 tmp |= SPEAKER_ALLOCATION(sadb[0]);62 else63 tmp |= SPEAKER_ALLOCATION(5); /* stereo */64 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);65}66 67void dce3_2_afmt_write_sad_regs(struct drm_encoder *encoder,68 struct cea_sad *sads, int sad_count)69{70 int i;71 struct radeon_device *rdev = encoder->dev->dev_private;72 static const u16 eld_reg_to_type[][2] = {73 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },74 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },75 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },76 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },77 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },78 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },79 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },80 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },81 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },82 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },83 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },84 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },85 };86 87 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {88 u32 value = 0;89 u8 stereo_freqs = 0;90 int max_channels = -1;91 int j;92 93 for (j = 0; j < sad_count; j++) {94 struct cea_sad *sad = &sads[j];95 96 if (sad->format == eld_reg_to_type[i][1]) {97 if (sad->channels > max_channels) {98 value = MAX_CHANNELS(sad->channels) |99 DESCRIPTOR_BYTE_2(sad->byte2) |100 SUPPORTED_FREQUENCIES(sad->freq);101 max_channels = sad->channels;102 }103 104 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)105 stereo_freqs |= sad->freq;106 else107 break;108 }109 }110 111 value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);112 113 WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);114 }115}116 117void dce3_2_audio_set_dto(struct radeon_device *rdev,118 struct radeon_crtc *crtc, unsigned int clock)119{120 struct radeon_encoder *radeon_encoder;121 struct radeon_encoder_atom_dig *dig;122 unsigned int max_ratio = clock / 24000;123 u32 dto_phase;124 u32 wallclock_ratio;125 u32 dto_cntl;126 127 if (!crtc)128 return;129 130 radeon_encoder = to_radeon_encoder(crtc->encoder);131 dig = radeon_encoder->enc_priv;132 133 if (!dig)134 return;135 136 if (max_ratio >= 8) {137 dto_phase = 192 * 1000;138 wallclock_ratio = 3;139 } else if (max_ratio >= 4) {140 dto_phase = 96 * 1000;141 wallclock_ratio = 2;142 } else if (max_ratio >= 2) {143 dto_phase = 48 * 1000;144 wallclock_ratio = 1;145 } else {146 dto_phase = 24 * 1000;147 wallclock_ratio = 0;148 }149 150 /* Express [24MHz / target pixel clock] as an exact rational151 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE152 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator153 */154 if (dig->dig_encoder == 0) {155 dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;156 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);157 WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);158 WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);159 WREG32(DCCG_AUDIO_DTO0_MODULE, clock);160 WREG32(DCCG_AUDIO_DTO_SELECT, 0); /* select DTO0 */161 } else {162 dto_cntl = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;163 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);164 WREG32(DCCG_AUDIO_DTO1_CNTL, dto_cntl);165 WREG32(DCCG_AUDIO_DTO1_PHASE, dto_phase);166 WREG32(DCCG_AUDIO_DTO1_MODULE, clock);167 WREG32(DCCG_AUDIO_DTO_SELECT, 1); /* select DTO1 */168 }169}170 171void dce3_2_hdmi_update_acr(struct drm_encoder *encoder, long offset,172 const struct radeon_hdmi_acr *acr)173{174 struct drm_device *dev = encoder->dev;175 struct radeon_device *rdev = dev->dev_private;176 177 WREG32(DCE3_HDMI0_ACR_PACKET_CONTROL + offset,178 HDMI0_ACR_SOURCE | /* select SW CTS value */179 HDMI0_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */180 181 WREG32_P(HDMI0_ACR_32_0 + offset,182 HDMI0_ACR_CTS_32(acr->cts_32khz),183 ~HDMI0_ACR_CTS_32_MASK);184 WREG32_P(HDMI0_ACR_32_1 + offset,185 HDMI0_ACR_N_32(acr->n_32khz),186 ~HDMI0_ACR_N_32_MASK);187 188 WREG32_P(HDMI0_ACR_44_0 + offset,189 HDMI0_ACR_CTS_44(acr->cts_44_1khz),190 ~HDMI0_ACR_CTS_44_MASK);191 WREG32_P(HDMI0_ACR_44_1 + offset,192 HDMI0_ACR_N_44(acr->n_44_1khz),193 ~HDMI0_ACR_N_44_MASK);194 195 WREG32_P(HDMI0_ACR_48_0 + offset,196 HDMI0_ACR_CTS_48(acr->cts_48khz),197 ~HDMI0_ACR_CTS_48_MASK);198 WREG32_P(HDMI0_ACR_48_1 + offset,199 HDMI0_ACR_N_48(acr->n_48khz),200 ~HDMI0_ACR_N_48_MASK);201}202 203void dce3_2_set_audio_packet(struct drm_encoder *encoder, u32 offset)204{205 struct drm_device *dev = encoder->dev;206 struct radeon_device *rdev = dev->dev_private;207 208 WREG32(HDMI0_AUDIO_PACKET_CONTROL + offset,209 HDMI0_AUDIO_DELAY_EN(1) | /* default audio delay */210 HDMI0_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */211 212 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,213 AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */214 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */215 216 WREG32_OR(HDMI0_INFOFRAME_CONTROL0 + offset,217 HDMI0_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */218 HDMI0_AUDIO_INFO_CONT); /* send audio info frames every frame/field */219 220 WREG32_OR(HDMI0_INFOFRAME_CONTROL1 + offset,221 HDMI0_AUDIO_INFO_LINE(2)); /* anything other than 0 */222}223 224void dce3_2_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)225{226 struct drm_device *dev = encoder->dev;227 struct radeon_device *rdev = dev->dev_private;228 229 if (mute)230 WREG32_OR(HDMI0_GC + offset, HDMI0_GC_AVMUTE);231 else232 WREG32_AND(HDMI0_GC + offset, ~HDMI0_GC_AVMUTE);233}234