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1/*2 * Copyright 2008 Advanced Micro Devices, Inc.3 * Copyright 2008 Red Hat Inc.4 * Copyright 2009 Christian König.5 *6 * Permission is hereby granted, free of charge, to any person obtaining a7 * copy of this software and associated documentation files (the "Software"),8 * to deal in the Software without restriction, including without limitation9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,10 * and/or sell copies of the Software, and to permit persons to whom the11 * Software is furnished to do so, subject to the following conditions:12 *13 * The above copyright notice and this permission notice shall be included in14 * all copies or substantial portions of the Software.15 *16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR22 * OTHER DEALINGS IN THE SOFTWARE.23 *24 * Authors: Christian König25 * Rafał Miłecki26 */27#include <linux/hdmi.h>28 29#include <drm/drm_edid.h>30#include <drm/radeon_drm.h>31#include "evergreen_hdmi.h"32#include "radeon.h"33#include "radeon_asic.h"34#include "radeon_audio.h"35#include "evergreend.h"36#include "atom.h"37 38/* enable the audio stream */39void dce4_audio_enable(struct radeon_device *rdev,40 struct r600_audio_pin *pin,41 u8 enable_mask)42{43 u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);44 45 if (!pin)46 return;47 48 if (enable_mask) {49 tmp |= AUDIO_ENABLED;50 if (enable_mask & 1)51 tmp |= PIN0_AUDIO_ENABLED;52 if (enable_mask & 2)53 tmp |= PIN1_AUDIO_ENABLED;54 if (enable_mask & 4)55 tmp |= PIN2_AUDIO_ENABLED;56 if (enable_mask & 8)57 tmp |= PIN3_AUDIO_ENABLED;58 } else {59 tmp &= ~(AUDIO_ENABLED |60 PIN0_AUDIO_ENABLED |61 PIN1_AUDIO_ENABLED |62 PIN2_AUDIO_ENABLED |63 PIN3_AUDIO_ENABLED);64 }65 66 WREG32(AZ_HOT_PLUG_CONTROL, tmp);67}68 69void evergreen_hdmi_update_acr(struct drm_encoder *encoder, long offset,70 const struct radeon_hdmi_acr *acr)71{72 struct drm_device *dev = encoder->dev;73 struct radeon_device *rdev = dev->dev_private;74 int bpc = 8;75 76 if (encoder->crtc) {77 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);78 bpc = radeon_crtc->bpc;79 }80 81 if (bpc > 8)82 WREG32(HDMI_ACR_PACKET_CONTROL + offset,83 HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */84 else85 WREG32(HDMI_ACR_PACKET_CONTROL + offset,86 HDMI_ACR_SOURCE | /* select SW CTS value */87 HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */88 89 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr->cts_32khz));90 WREG32(HDMI_ACR_32_1 + offset, acr->n_32khz);91 92 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr->cts_44_1khz));93 WREG32(HDMI_ACR_44_1 + offset, acr->n_44_1khz);94 95 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr->cts_48khz));96 WREG32(HDMI_ACR_48_1 + offset, acr->n_48khz);97}98 99void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,100 struct drm_connector *connector, struct drm_display_mode *mode)101{102 struct radeon_device *rdev = encoder->dev->dev_private;103 u32 tmp = 0;104 105 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {106 if (connector->latency_present[1])107 tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |108 AUDIO_LIPSYNC(connector->audio_latency[1]);109 else110 tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);111 } else {112 if (connector->latency_present[0])113 tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |114 AUDIO_LIPSYNC(connector->audio_latency[0]);115 else116 tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);117 }118 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);119}120 121void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,122 u8 *sadb, int sad_count)123{124 struct radeon_device *rdev = encoder->dev->dev_private;125 u32 tmp;126 127 /* program the speaker allocation */128 tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);129 tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);130 /* set HDMI mode */131 tmp |= HDMI_CONNECTION;132 if (sad_count)133 tmp |= SPEAKER_ALLOCATION(sadb[0]);134 else135 tmp |= SPEAKER_ALLOCATION(5); /* stereo */136 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);137}138 139void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,140 u8 *sadb, int sad_count)141{142 struct radeon_device *rdev = encoder->dev->dev_private;143 u32 tmp;144 145 /* program the speaker allocation */146 tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);147 tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);148 /* set DP mode */149 tmp |= DP_CONNECTION;150 if (sad_count)151 tmp |= SPEAKER_ALLOCATION(sadb[0]);152 else153 tmp |= SPEAKER_ALLOCATION(5); /* stereo */154 WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);155}156 157void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder,158 struct cea_sad *sads, int sad_count)159{160 int i;161 struct radeon_device *rdev = encoder->dev->dev_private;162 static const u16 eld_reg_to_type[][2] = {163 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },164 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },165 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },166 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },167 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },168 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },169 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },170 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },171 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },172 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },173 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },174 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },175 };176 177 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {178 u32 value = 0;179 u8 stereo_freqs = 0;180 int max_channels = -1;181 int j;182 183 for (j = 0; j < sad_count; j++) {184 struct cea_sad *sad = &sads[j];185 186 if (sad->format == eld_reg_to_type[i][1]) {187 if (sad->channels > max_channels) {188 value = MAX_CHANNELS(sad->channels) |189 DESCRIPTOR_BYTE_2(sad->byte2) |190 SUPPORTED_FREQUENCIES(sad->freq);191 max_channels = sad->channels;192 }193 194 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)195 stereo_freqs |= sad->freq;196 else197 break;198 }199 }200 201 value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);202 203 WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);204 }205}206 207/*208 * build a AVI Info Frame209 */210void evergreen_set_avi_packet(struct radeon_device *rdev, u32 offset,211 unsigned char *buffer, size_t size)212{213 uint8_t *frame = buffer + 3;214 215 WREG32(AFMT_AVI_INFO0 + offset,216 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));217 WREG32(AFMT_AVI_INFO1 + offset,218 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));219 WREG32(AFMT_AVI_INFO2 + offset,220 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));221 WREG32(AFMT_AVI_INFO3 + offset,222 frame[0xC] | (frame[0xD] << 8) | (buffer[1] << 24));223 224 WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,225 HDMI_AVI_INFO_LINE(2), /* anything other than 0 */226 ~HDMI_AVI_INFO_LINE_MASK);227}228 229void dce4_hdmi_audio_set_dto(struct radeon_device *rdev,230 struct radeon_crtc *crtc, unsigned int clock)231{232 unsigned int max_ratio = clock / 24000;233 u32 dto_phase;234 u32 wallclock_ratio;235 u32 value;236 237 if (max_ratio >= 8) {238 dto_phase = 192 * 1000;239 wallclock_ratio = 3;240 } else if (max_ratio >= 4) {241 dto_phase = 96 * 1000;242 wallclock_ratio = 2;243 } else if (max_ratio >= 2) {244 dto_phase = 48 * 1000;245 wallclock_ratio = 1;246 } else {247 dto_phase = 24 * 1000;248 wallclock_ratio = 0;249 }250 251 value = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;252 value |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);253 value &= ~DCCG_AUDIO_DTO1_USE_512FBR_DTO;254 WREG32(DCCG_AUDIO_DTO0_CNTL, value);255 256 /* Two dtos; generally use dto0 for HDMI */257 value = 0;258 259 if (crtc)260 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);261 262 WREG32(DCCG_AUDIO_DTO_SOURCE, value);263 264 /* Express [24MHz / target pixel clock] as an exact rational265 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE266 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator267 */268 WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);269 WREG32(DCCG_AUDIO_DTO0_MODULE, clock);270}271 272void dce4_dp_audio_set_dto(struct radeon_device *rdev,273 struct radeon_crtc *crtc, unsigned int clock)274{275 u32 value;276 277 value = RREG32(DCCG_AUDIO_DTO1_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;278 value |= DCCG_AUDIO_DTO1_USE_512FBR_DTO;279 WREG32(DCCG_AUDIO_DTO1_CNTL, value);280 281 /* Two dtos; generally use dto1 for DP */282 value = 0;283 value |= DCCG_AUDIO_DTO_SEL;284 285 if (crtc)286 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id);287 288 WREG32(DCCG_AUDIO_DTO_SOURCE, value);289 290 /* Express [24MHz / target pixel clock] as an exact rational291 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE292 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator293 */294 if (ASIC_IS_DCE41(rdev)) {295 unsigned int div = (RREG32(DCE41_DENTIST_DISPCLK_CNTL) &296 DENTIST_DPREFCLK_WDIVIDER_MASK) >>297 DENTIST_DPREFCLK_WDIVIDER_SHIFT;298 div = radeon_audio_decode_dfs_div(div);299 300 if (div)301 clock = 100 * clock / div;302 }303 304 WREG32(DCCG_AUDIO_DTO1_PHASE, 24000);305 WREG32(DCCG_AUDIO_DTO1_MODULE, clock);306}307 308void dce4_set_vbi_packet(struct drm_encoder *encoder, u32 offset)309{310 struct drm_device *dev = encoder->dev;311 struct radeon_device *rdev = dev->dev_private;312 313 WREG32(HDMI_VBI_PACKET_CONTROL + offset,314 HDMI_NULL_SEND | /* send null packets when required */315 HDMI_GC_SEND | /* send general control packets */316 HDMI_GC_CONT); /* send general control packets every frame */317}318 319void dce4_hdmi_set_color_depth(struct drm_encoder *encoder, u32 offset, int bpc)320{321 struct drm_device *dev = encoder->dev;322 struct radeon_device *rdev = dev->dev_private;323 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);324 uint32_t val;325 326 val = RREG32(HDMI_CONTROL + offset);327 val &= ~HDMI_DEEP_COLOR_ENABLE;328 val &= ~HDMI_DEEP_COLOR_DEPTH_MASK;329 330 switch (bpc) {331 case 0:332 case 6:333 case 8:334 case 16:335 default:336 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",337 connector->name, bpc);338 break;339 case 10:340 val |= HDMI_DEEP_COLOR_ENABLE;341 val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR);342 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",343 connector->name);344 break;345 case 12:346 val |= HDMI_DEEP_COLOR_ENABLE;347 val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR);348 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",349 connector->name);350 break;351 }352 353 WREG32(HDMI_CONTROL + offset, val);354}355 356void dce4_set_audio_packet(struct drm_encoder *encoder, u32 offset)357{358 struct drm_device *dev = encoder->dev;359 struct radeon_device *rdev = dev->dev_private;360 361 WREG32(AFMT_INFOFRAME_CONTROL0 + offset,362 AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */363 364 WREG32(AFMT_60958_0 + offset,365 AFMT_60958_CS_CHANNEL_NUMBER_L(1));366 367 WREG32(AFMT_60958_1 + offset,368 AFMT_60958_CS_CHANNEL_NUMBER_R(2));369 370 WREG32(AFMT_60958_2 + offset,371 AFMT_60958_CS_CHANNEL_NUMBER_2(3) |372 AFMT_60958_CS_CHANNEL_NUMBER_3(4) |373 AFMT_60958_CS_CHANNEL_NUMBER_4(5) |374 AFMT_60958_CS_CHANNEL_NUMBER_5(6) |375 AFMT_60958_CS_CHANNEL_NUMBER_6(7) |376 AFMT_60958_CS_CHANNEL_NUMBER_7(8));377 378 WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,379 AFMT_AUDIO_CHANNEL_ENABLE(0xff));380 381 WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,382 HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */383 HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */384 385 /* allow 60958 channel status and send audio packets fields to be updated */386 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,387 AFMT_RESET_FIFO_WHEN_AUDIO_DIS | AFMT_60958_CS_UPDATE);388}389 390 391void dce4_set_mute(struct drm_encoder *encoder, u32 offset, bool mute)392{393 struct drm_device *dev = encoder->dev;394 struct radeon_device *rdev = dev->dev_private;395 396 if (mute)397 WREG32_OR(HDMI_GC + offset, HDMI_GC_AVMUTE);398 else399 WREG32_AND(HDMI_GC + offset, ~HDMI_GC_AVMUTE);400}401 402void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)403{404 struct drm_device *dev = encoder->dev;405 struct radeon_device *rdev = dev->dev_private;406 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);407 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;408 409 if (!dig || !dig->afmt)410 return;411 412 if (enable) {413 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);414 415 if (connector && connector->display_info.has_audio) {416 WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,417 HDMI_AVI_INFO_SEND | /* enable AVI info frames */418 HDMI_AVI_INFO_CONT | /* required for audio info values to be updated */419 HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */420 HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */421 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,422 AFMT_AUDIO_SAMPLE_SEND);423 } else {424 WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset,425 HDMI_AVI_INFO_SEND | /* enable AVI info frames */426 HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */427 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,428 ~AFMT_AUDIO_SAMPLE_SEND);429 }430 } else {431 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,432 ~AFMT_AUDIO_SAMPLE_SEND);433 WREG32(HDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, 0);434 }435 436 dig->afmt->enabled = enable;437 438 DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",439 enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);440}441 442void evergreen_dp_enable(struct drm_encoder *encoder, bool enable)443{444 struct drm_device *dev = encoder->dev;445 struct radeon_device *rdev = dev->dev_private;446 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);447 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;448 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);449 450 if (!dig || !dig->afmt)451 return;452 453 if (enable && connector && connector->display_info.has_audio) {454 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);455 struct radeon_connector *radeon_connector = to_radeon_connector(connector);456 struct radeon_connector_atom_dig *dig_connector;457 uint32_t val;458 459 WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,460 AFMT_AUDIO_SAMPLE_SEND);461 462 WREG32(EVERGREEN_DP_SEC_TIMESTAMP + dig->afmt->offset,463 EVERGREEN_DP_SEC_TIMESTAMP_MODE(1));464 465 if (!ASIC_IS_DCE6(rdev) && radeon_connector->con_priv) {466 dig_connector = radeon_connector->con_priv;467 val = RREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset);468 val &= ~EVERGREEN_DP_SEC_N_BASE_MULTIPLE(0xf);469 470 if (dig_connector->dp_clock == 162000)471 val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(3);472 else473 val |= EVERGREEN_DP_SEC_N_BASE_MULTIPLE(5);474 475 WREG32(EVERGREEN_DP_SEC_AUD_N + dig->afmt->offset, val);476 }477 478 WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset,479 EVERGREEN_DP_SEC_ASP_ENABLE | /* Audio packet transmission */480 EVERGREEN_DP_SEC_ATP_ENABLE | /* Audio timestamp packet transmission */481 EVERGREEN_DP_SEC_AIP_ENABLE | /* Audio infoframe packet transmission */482 EVERGREEN_DP_SEC_STREAM_ENABLE); /* Master enable for secondary stream engine */483 } else {484 WREG32(EVERGREEN_DP_SEC_CNTL + dig->afmt->offset, 0);485 WREG32_AND(AFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset,486 ~AFMT_AUDIO_SAMPLE_SEND);487 }488 489 dig->afmt->enabled = enable;490}491