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1/*2 * Copyright 2012 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23#ifndef __NI_DPM_H__24#define __NI_DPM_H__25 26#include "cypress_dpm.h"27#include "btc_dpm.h"28#include "nislands_smc.h"29 30struct ni_clock_registers {31 u32 cg_spll_func_cntl;32 u32 cg_spll_func_cntl_2;33 u32 cg_spll_func_cntl_3;34 u32 cg_spll_func_cntl_4;35 u32 cg_spll_spread_spectrum;36 u32 cg_spll_spread_spectrum_2;37 u32 mclk_pwrmgt_cntl;38 u32 dll_cntl;39 u32 mpll_ad_func_cntl;40 u32 mpll_ad_func_cntl_2;41 u32 mpll_dq_func_cntl;42 u32 mpll_dq_func_cntl_2;43 u32 mpll_ss1;44 u32 mpll_ss2;45};46 47struct ni_mc_reg_entry {48 u32 mclk_max;49 u32 mc_data[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];50};51 52struct ni_mc_reg_table {53 u8 last;54 u8 num_entries;55 u16 valid_flag;56 struct ni_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];57 SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE];58};59 60#define NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT 261 62enum ni_dc_cac_level {63 NISLANDS_DCCAC_LEVEL_0 = 0,64 NISLANDS_DCCAC_LEVEL_1,65 NISLANDS_DCCAC_LEVEL_2,66 NISLANDS_DCCAC_LEVEL_3,67 NISLANDS_DCCAC_LEVEL_4,68 NISLANDS_DCCAC_LEVEL_5,69 NISLANDS_DCCAC_LEVEL_6,70 NISLANDS_DCCAC_LEVEL_7,71 NISLANDS_DCCAC_MAX_LEVELS72};73 74struct ni_leakage_coeffients {75 u32 at;76 u32 bt;77 u32 av;78 u32 bv;79 s32 t_slope;80 s32 t_intercept;81 u32 t_ref;82};83 84struct ni_cac_data {85 struct ni_leakage_coeffients leakage_coefficients;86 u32 i_leakage;87 s32 leakage_minimum_temperature;88 u32 pwr_const;89 u32 dc_cac_value;90 u32 bif_cac_value;91 u32 lkge_pwr;92 u8 mc_wr_weight;93 u8 mc_rd_weight;94 u8 allow_ovrflw;95 u8 num_win_tdp;96 u8 l2num_win_tdp;97 u8 lts_truncate_n;98};99 100struct ni_cac_weights {101 u32 weight_tcp_sig0;102 u32 weight_tcp_sig1;103 u32 weight_ta_sig;104 u32 weight_tcc_en0;105 u32 weight_tcc_en1;106 u32 weight_tcc_en2;107 u32 weight_cb_en0;108 u32 weight_cb_en1;109 u32 weight_cb_en2;110 u32 weight_cb_en3;111 u32 weight_db_sig0;112 u32 weight_db_sig1;113 u32 weight_db_sig2;114 u32 weight_db_sig3;115 u32 weight_sxm_sig0;116 u32 weight_sxm_sig1;117 u32 weight_sxm_sig2;118 u32 weight_sxs_sig0;119 u32 weight_sxs_sig1;120 u32 weight_xbr_0;121 u32 weight_xbr_1;122 u32 weight_xbr_2;123 u32 weight_spi_sig0;124 u32 weight_spi_sig1;125 u32 weight_spi_sig2;126 u32 weight_spi_sig3;127 u32 weight_spi_sig4;128 u32 weight_spi_sig5;129 u32 weight_lds_sig0;130 u32 weight_lds_sig1;131 u32 weight_sc;132 u32 weight_bif;133 u32 weight_cp;134 u32 weight_pa_sig0;135 u32 weight_pa_sig1;136 u32 weight_vgt_sig0;137 u32 weight_vgt_sig1;138 u32 weight_vgt_sig2;139 u32 weight_dc_sig0;140 u32 weight_dc_sig1;141 u32 weight_dc_sig2;142 u32 weight_dc_sig3;143 u32 weight_uvd_sig0;144 u32 weight_uvd_sig1;145 u32 weight_spare0;146 u32 weight_spare1;147 u32 weight_sq_vsp;148 u32 weight_sq_vsp0;149 u32 weight_sq_gpr;150 u32 ovr_mode_spare_0;151 u32 ovr_val_spare_0;152 u32 ovr_mode_spare_1;153 u32 ovr_val_spare_1;154 u32 vsp;155 u32 vsp0;156 u32 gpr;157 u8 mc_read_weight;158 u8 mc_write_weight;159 u32 tid_cnt;160 u32 tid_unit;161 u32 l2_lta_window_size;162 u32 lts_truncate;163 u32 dc_cac[NISLANDS_DCCAC_MAX_LEVELS];164 u32 pcie_cac[SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES];165 bool enable_power_containment_by_default;166};167 168struct ni_ps {169 u16 performance_level_count;170 bool dc_compatible;171 struct rv7xx_pl performance_levels[NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE];172};173 174struct ni_power_info {175 /* must be first! */176 struct evergreen_power_info eg;177 struct ni_clock_registers clock_registers;178 struct ni_mc_reg_table mc_reg_table;179 u32 mclk_rtt_mode_threshold;180 /* flags */181 bool use_power_boost_limit;182 bool support_cac_long_term_average;183 bool cac_enabled;184 bool cac_configuration_required;185 bool driver_calculate_cac_leakage;186 bool pc_enabled;187 bool enable_power_containment;188 bool enable_cac;189 bool enable_sq_ramping;190 /* smc offsets */191 u16 arb_table_start;192 u16 fan_table_start;193 u16 cac_table_start;194 u16 spll_table_start;195 /* CAC stuff */196 struct ni_cac_data cac_data;197 u32 dc_cac_table[NISLANDS_DCCAC_MAX_LEVELS];198 const struct ni_cac_weights *cac_weights;199 u8 lta_window_size;200 u8 lts_truncate;201 struct ni_ps current_ps;202 struct ni_ps requested_ps;203 /* scratch structs */204 SMC_NIslands_MCRegisters smc_mc_reg_table;205 NISLANDS_SMC_STATETABLE smc_statetable;206};207 208#define NISLANDS_INITIAL_STATE_ARB_INDEX 0209#define NISLANDS_ACPI_STATE_ARB_INDEX 1210#define NISLANDS_ULV_STATE_ARB_INDEX 2211#define NISLANDS_DRIVER_STATE_ARB_INDEX 3212 213#define NISLANDS_DPM2_MAX_PULSE_SKIP 256214 215#define NISLANDS_DPM2_NEAR_TDP_DEC 10216#define NISLANDS_DPM2_ABOVE_SAFE_INC 5217#define NISLANDS_DPM2_BELOW_SAFE_INC 20218 219#define NISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT 80220 221#define NISLANDS_DPM2_MAXPS_PERCENT_H 90222#define NISLANDS_DPM2_MAXPS_PERCENT_M 0223 224#define NISLANDS_DPM2_SQ_RAMP_MAX_POWER 0x3FFF225#define NISLANDS_DPM2_SQ_RAMP_MIN_POWER 0x12226#define NISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15227#define NISLANDS_DPM2_SQ_RAMP_STI_SIZE 0x1E228#define NISLANDS_DPM2_SQ_RAMP_LTI_RATIO 0xF229 230int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,231 u32 arb_freq_src, u32 arb_freq_dest);232void ni_update_current_ps(struct radeon_device *rdev,233 struct radeon_ps *rps);234void ni_update_requested_ps(struct radeon_device *rdev,235 struct radeon_ps *rps);236 237void ni_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,238 struct radeon_ps *new_ps,239 struct radeon_ps *old_ps);240void ni_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,241 struct radeon_ps *new_ps,242 struct radeon_ps *old_ps);243 244bool ni_dpm_vblank_too_short(struct radeon_device *rdev);245 246struct ni_power_info *ni_get_pi(struct radeon_device *rdev);247struct ni_ps *ni_get_ps(struct radeon_ps *rps);248 249#endif250