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1/*2 * Copyright 2008 Advanced Micro Devices, Inc.3 * Copyright 2008 Red Hat Inc.4 * Copyright 2009 Jerome Glisse.5 *6 * Permission is hereby granted, free of charge, to any person obtaining a7 * copy of this software and associated documentation files (the "Software"),8 * to deal in the Software without restriction, including without limitation9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,10 * and/or sell copies of the Software, and to permit persons to whom the11 * Software is furnished to do so, subject to the following conditions:12 *13 * The above copyright notice and this permission notice shall be included in14 * all copies or substantial portions of the Software.15 *16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR22 * OTHER DEALINGS IN THE SOFTWARE.23 *24 * Authors: Dave Airlie25 * Alex Deucher26 * Jerome Glisse27 */28#ifndef __R100D_H__29#define __R100D_H__30 31#define CP_PACKET0 0x0000000032#define PACKET0_BASE_INDEX_SHIFT 033#define PACKET0_BASE_INDEX_MASK (0x1ffff << 0)34#define PACKET0_COUNT_SHIFT 1635#define PACKET0_COUNT_MASK (0x3fff << 16)36#define CP_PACKET1 0x4000000037#define CP_PACKET2 0x8000000038#define PACKET2_PAD_SHIFT 039#define PACKET2_PAD_MASK (0x3fffffff << 0)40#define CP_PACKET3 0xC000000041#define PACKET3_IT_OPCODE_SHIFT 842#define PACKET3_IT_OPCODE_MASK (0xff << 8)43#define PACKET3_COUNT_SHIFT 1644#define PACKET3_COUNT_MASK (0x3fff << 16)45/* PACKET3 op code */46#define PACKET3_NOP 0x1047#define PACKET3_3D_DRAW_VBUF 0x2848#define PACKET3_3D_DRAW_IMMD 0x2949#define PACKET3_3D_DRAW_INDX 0x2A50#define PACKET3_3D_LOAD_VBPNTR 0x2F51#define PACKET3_3D_CLEAR_ZMASK 0x3252#define PACKET3_INDX_BUFFER 0x3353#define PACKET3_3D_DRAW_VBUF_2 0x3454#define PACKET3_3D_DRAW_IMMD_2 0x3555#define PACKET3_3D_DRAW_INDX_2 0x3656#define PACKET3_3D_CLEAR_HIZ 0x3757#define PACKET3_BITBLT_MULTI 0x9B58 59#define PACKET0(reg, n) (CP_PACKET0 | \60 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \61 REG_SET(PACKET0_COUNT, (n)))62#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))63#define PACKET3(op, n) (CP_PACKET3 | \64 REG_SET(PACKET3_IT_OPCODE, (op)) | \65 REG_SET(PACKET3_COUNT, (n)))66 67/* Registers */68#define R_0000F0_RBBM_SOFT_RESET 0x0000F069#define S_0000F0_SOFT_RESET_CP(x) (((x) & 0x1) << 0)70#define G_0000F0_SOFT_RESET_CP(x) (((x) >> 0) & 0x1)71#define C_0000F0_SOFT_RESET_CP 0xFFFFFFFE72#define S_0000F0_SOFT_RESET_HI(x) (((x) & 0x1) << 1)73#define G_0000F0_SOFT_RESET_HI(x) (((x) >> 1) & 0x1)74#define C_0000F0_SOFT_RESET_HI 0xFFFFFFFD75#define S_0000F0_SOFT_RESET_SE(x) (((x) & 0x1) << 2)76#define G_0000F0_SOFT_RESET_SE(x) (((x) >> 2) & 0x1)77#define C_0000F0_SOFT_RESET_SE 0xFFFFFFFB78#define S_0000F0_SOFT_RESET_RE(x) (((x) & 0x1) << 3)79#define G_0000F0_SOFT_RESET_RE(x) (((x) >> 3) & 0x1)80#define C_0000F0_SOFT_RESET_RE 0xFFFFFFF781#define S_0000F0_SOFT_RESET_PP(x) (((x) & 0x1) << 4)82#define G_0000F0_SOFT_RESET_PP(x) (((x) >> 4) & 0x1)83#define C_0000F0_SOFT_RESET_PP 0xFFFFFFEF84#define S_0000F0_SOFT_RESET_E2(x) (((x) & 0x1) << 5)85#define G_0000F0_SOFT_RESET_E2(x) (((x) >> 5) & 0x1)86#define C_0000F0_SOFT_RESET_E2 0xFFFFFFDF87#define S_0000F0_SOFT_RESET_RB(x) (((x) & 0x1) << 6)88#define G_0000F0_SOFT_RESET_RB(x) (((x) >> 6) & 0x1)89#define C_0000F0_SOFT_RESET_RB 0xFFFFFFBF90#define S_0000F0_SOFT_RESET_HDP(x) (((x) & 0x1) << 7)91#define G_0000F0_SOFT_RESET_HDP(x) (((x) >> 7) & 0x1)92#define C_0000F0_SOFT_RESET_HDP 0xFFFFFF7F93#define S_0000F0_SOFT_RESET_MC(x) (((x) & 0x1) << 8)94#define G_0000F0_SOFT_RESET_MC(x) (((x) >> 8) & 0x1)95#define C_0000F0_SOFT_RESET_MC 0xFFFFFEFF96#define S_0000F0_SOFT_RESET_AIC(x) (((x) & 0x1) << 9)97#define G_0000F0_SOFT_RESET_AIC(x) (((x) >> 9) & 0x1)98#define C_0000F0_SOFT_RESET_AIC 0xFFFFFDFF99#define S_0000F0_SOFT_RESET_VIP(x) (((x) & 0x1) << 10)100#define G_0000F0_SOFT_RESET_VIP(x) (((x) >> 10) & 0x1)101#define C_0000F0_SOFT_RESET_VIP 0xFFFFFBFF102#define S_0000F0_SOFT_RESET_DISP(x) (((x) & 0x1) << 11)103#define G_0000F0_SOFT_RESET_DISP(x) (((x) >> 11) & 0x1)104#define C_0000F0_SOFT_RESET_DISP 0xFFFFF7FF105#define S_0000F0_SOFT_RESET_CG(x) (((x) & 0x1) << 12)106#define G_0000F0_SOFT_RESET_CG(x) (((x) >> 12) & 0x1)107#define C_0000F0_SOFT_RESET_CG 0xFFFFEFFF108#define R_000030_BUS_CNTL 0x000030109#define S_000030_BUS_DBL_RESYNC(x) (((x) & 0x1) << 0)110#define G_000030_BUS_DBL_RESYNC(x) (((x) >> 0) & 0x1)111#define C_000030_BUS_DBL_RESYNC 0xFFFFFFFE112#define S_000030_BUS_MSTR_RESET(x) (((x) & 0x1) << 1)113#define G_000030_BUS_MSTR_RESET(x) (((x) >> 1) & 0x1)114#define C_000030_BUS_MSTR_RESET 0xFFFFFFFD115#define S_000030_BUS_FLUSH_BUF(x) (((x) & 0x1) << 2)116#define G_000030_BUS_FLUSH_BUF(x) (((x) >> 2) & 0x1)117#define C_000030_BUS_FLUSH_BUF 0xFFFFFFFB118#define S_000030_BUS_STOP_REQ_DIS(x) (((x) & 0x1) << 3)119#define G_000030_BUS_STOP_REQ_DIS(x) (((x) >> 3) & 0x1)120#define C_000030_BUS_STOP_REQ_DIS 0xFFFFFFF7121#define S_000030_BUS_PM4_READ_COMBINE_EN(x) (((x) & 0x1) << 4)122#define G_000030_BUS_PM4_READ_COMBINE_EN(x) (((x) >> 4) & 0x1)123#define C_000030_BUS_PM4_READ_COMBINE_EN 0xFFFFFFEF124#define S_000030_BUS_WRT_COMBINE_EN(x) (((x) & 0x1) << 5)125#define G_000030_BUS_WRT_COMBINE_EN(x) (((x) >> 5) & 0x1)126#define C_000030_BUS_WRT_COMBINE_EN 0xFFFFFFDF127#define S_000030_BUS_MASTER_DIS(x) (((x) & 0x1) << 6)128#define G_000030_BUS_MASTER_DIS(x) (((x) >> 6) & 0x1)129#define C_000030_BUS_MASTER_DIS 0xFFFFFFBF130#define S_000030_BIOS_ROM_WRT_EN(x) (((x) & 0x1) << 7)131#define G_000030_BIOS_ROM_WRT_EN(x) (((x) >> 7) & 0x1)132#define C_000030_BIOS_ROM_WRT_EN 0xFFFFFF7F133#define S_000030_BM_DAC_CRIPPLE(x) (((x) & 0x1) << 8)134#define G_000030_BM_DAC_CRIPPLE(x) (((x) >> 8) & 0x1)135#define C_000030_BM_DAC_CRIPPLE 0xFFFFFEFF136#define S_000030_BUS_NON_PM4_READ_COMBINE_EN(x) (((x) & 0x1) << 9)137#define G_000030_BUS_NON_PM4_READ_COMBINE_EN(x) (((x) >> 9) & 0x1)138#define C_000030_BUS_NON_PM4_READ_COMBINE_EN 0xFFFFFDFF139#define S_000030_BUS_XFERD_DISCARD_EN(x) (((x) & 0x1) << 10)140#define G_000030_BUS_XFERD_DISCARD_EN(x) (((x) >> 10) & 0x1)141#define C_000030_BUS_XFERD_DISCARD_EN 0xFFFFFBFF142#define S_000030_BUS_SGL_READ_DISABLE(x) (((x) & 0x1) << 11)143#define G_000030_BUS_SGL_READ_DISABLE(x) (((x) >> 11) & 0x1)144#define C_000030_BUS_SGL_READ_DISABLE 0xFFFFF7FF145#define S_000030_BIOS_DIS_ROM(x) (((x) & 0x1) << 12)146#define G_000030_BIOS_DIS_ROM(x) (((x) >> 12) & 0x1)147#define C_000030_BIOS_DIS_ROM 0xFFFFEFFF148#define S_000030_BUS_PCI_READ_RETRY_EN(x) (((x) & 0x1) << 13)149#define G_000030_BUS_PCI_READ_RETRY_EN(x) (((x) >> 13) & 0x1)150#define C_000030_BUS_PCI_READ_RETRY_EN 0xFFFFDFFF151#define S_000030_BUS_AGP_AD_STEPPING_EN(x) (((x) & 0x1) << 14)152#define G_000030_BUS_AGP_AD_STEPPING_EN(x) (((x) >> 14) & 0x1)153#define C_000030_BUS_AGP_AD_STEPPING_EN 0xFFFFBFFF154#define S_000030_BUS_PCI_WRT_RETRY_EN(x) (((x) & 0x1) << 15)155#define G_000030_BUS_PCI_WRT_RETRY_EN(x) (((x) >> 15) & 0x1)156#define C_000030_BUS_PCI_WRT_RETRY_EN 0xFFFF7FFF157#define S_000030_BUS_RETRY_WS(x) (((x) & 0xF) << 16)158#define G_000030_BUS_RETRY_WS(x) (((x) >> 16) & 0xF)159#define C_000030_BUS_RETRY_WS 0xFFF0FFFF160#define S_000030_BUS_MSTR_RD_MULT(x) (((x) & 0x1) << 20)161#define G_000030_BUS_MSTR_RD_MULT(x) (((x) >> 20) & 0x1)162#define C_000030_BUS_MSTR_RD_MULT 0xFFEFFFFF163#define S_000030_BUS_MSTR_RD_LINE(x) (((x) & 0x1) << 21)164#define G_000030_BUS_MSTR_RD_LINE(x) (((x) >> 21) & 0x1)165#define C_000030_BUS_MSTR_RD_LINE 0xFFDFFFFF166#define S_000030_BUS_SUSPEND(x) (((x) & 0x1) << 22)167#define G_000030_BUS_SUSPEND(x) (((x) >> 22) & 0x1)168#define C_000030_BUS_SUSPEND 0xFFBFFFFF169#define S_000030_LAT_16X(x) (((x) & 0x1) << 23)170#define G_000030_LAT_16X(x) (((x) >> 23) & 0x1)171#define C_000030_LAT_16X 0xFF7FFFFF172#define S_000030_BUS_RD_DISCARD_EN(x) (((x) & 0x1) << 24)173#define G_000030_BUS_RD_DISCARD_EN(x) (((x) >> 24) & 0x1)174#define C_000030_BUS_RD_DISCARD_EN 0xFEFFFFFF175#define S_000030_ENFRCWRDY(x) (((x) & 0x1) << 25)176#define G_000030_ENFRCWRDY(x) (((x) >> 25) & 0x1)177#define C_000030_ENFRCWRDY 0xFDFFFFFF178#define S_000030_BUS_MSTR_WS(x) (((x) & 0x1) << 26)179#define G_000030_BUS_MSTR_WS(x) (((x) >> 26) & 0x1)180#define C_000030_BUS_MSTR_WS 0xFBFFFFFF181#define S_000030_BUS_PARKING_DIS(x) (((x) & 0x1) << 27)182#define G_000030_BUS_PARKING_DIS(x) (((x) >> 27) & 0x1)183#define C_000030_BUS_PARKING_DIS 0xF7FFFFFF184#define S_000030_BUS_MSTR_DISCONNECT_EN(x) (((x) & 0x1) << 28)185#define G_000030_BUS_MSTR_DISCONNECT_EN(x) (((x) >> 28) & 0x1)186#define C_000030_BUS_MSTR_DISCONNECT_EN 0xEFFFFFFF187#define S_000030_SERR_EN(x) (((x) & 0x1) << 29)188#define G_000030_SERR_EN(x) (((x) >> 29) & 0x1)189#define C_000030_SERR_EN 0xDFFFFFFF190#define S_000030_BUS_READ_BURST(x) (((x) & 0x1) << 30)191#define G_000030_BUS_READ_BURST(x) (((x) >> 30) & 0x1)192#define C_000030_BUS_READ_BURST 0xBFFFFFFF193#define S_000030_BUS_RDY_READ_DLY(x) (((x) & 0x1) << 31)194#define G_000030_BUS_RDY_READ_DLY(x) (((x) >> 31) & 0x1)195#define C_000030_BUS_RDY_READ_DLY 0x7FFFFFFF196#define R_000040_GEN_INT_CNTL 0x000040197#define S_000040_CRTC_VBLANK(x) (((x) & 0x1) << 0)198#define G_000040_CRTC_VBLANK(x) (((x) >> 0) & 0x1)199#define C_000040_CRTC_VBLANK 0xFFFFFFFE200#define S_000040_CRTC_VLINE(x) (((x) & 0x1) << 1)201#define G_000040_CRTC_VLINE(x) (((x) >> 1) & 0x1)202#define C_000040_CRTC_VLINE 0xFFFFFFFD203#define S_000040_CRTC_VSYNC(x) (((x) & 0x1) << 2)204#define G_000040_CRTC_VSYNC(x) (((x) >> 2) & 0x1)205#define C_000040_CRTC_VSYNC 0xFFFFFFFB206#define S_000040_SNAPSHOT(x) (((x) & 0x1) << 3)207#define G_000040_SNAPSHOT(x) (((x) >> 3) & 0x1)208#define C_000040_SNAPSHOT 0xFFFFFFF7209#define S_000040_FP_DETECT(x) (((x) & 0x1) << 4)210#define G_000040_FP_DETECT(x) (((x) >> 4) & 0x1)211#define C_000040_FP_DETECT 0xFFFFFFEF212#define S_000040_CRTC2_VLINE(x) (((x) & 0x1) << 5)213#define G_000040_CRTC2_VLINE(x) (((x) >> 5) & 0x1)214#define C_000040_CRTC2_VLINE 0xFFFFFFDF215#define S_000040_DMA_VIPH0_INT_EN(x) (((x) & 0x1) << 12)216#define G_000040_DMA_VIPH0_INT_EN(x) (((x) >> 12) & 0x1)217#define C_000040_DMA_VIPH0_INT_EN 0xFFFFEFFF218#define S_000040_CRTC2_VSYNC(x) (((x) & 0x1) << 6)219#define G_000040_CRTC2_VSYNC(x) (((x) >> 6) & 0x1)220#define C_000040_CRTC2_VSYNC 0xFFFFFFBF221#define S_000040_SNAPSHOT2(x) (((x) & 0x1) << 7)222#define G_000040_SNAPSHOT2(x) (((x) >> 7) & 0x1)223#define C_000040_SNAPSHOT2 0xFFFFFF7F224#define S_000040_CRTC2_VBLANK(x) (((x) & 0x1) << 9)225#define G_000040_CRTC2_VBLANK(x) (((x) >> 9) & 0x1)226#define C_000040_CRTC2_VBLANK 0xFFFFFDFF227#define S_000040_FP2_DETECT(x) (((x) & 0x1) << 10)228#define G_000040_FP2_DETECT(x) (((x) >> 10) & 0x1)229#define C_000040_FP2_DETECT 0xFFFFFBFF230#define S_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) & 0x1) << 11)231#define G_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) >> 11) & 0x1)232#define C_000040_VSYNC_DIFF_OVER_LIMIT 0xFFFFF7FF233#define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13)234#define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1)235#define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF236#define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14)237#define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1)238#define C_000040_DMA_VIPH2_INT_EN 0xFFFFBFFF239#define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15)240#define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1)241#define C_000040_DMA_VIPH3_INT_EN 0xFFFF7FFF242#define S_000040_I2C_INT_EN(x) (((x) & 0x1) << 17)243#define G_000040_I2C_INT_EN(x) (((x) >> 17) & 0x1)244#define C_000040_I2C_INT_EN 0xFFFDFFFF245#define S_000040_GUI_IDLE(x) (((x) & 0x1) << 19)246#define G_000040_GUI_IDLE(x) (((x) >> 19) & 0x1)247#define C_000040_GUI_IDLE 0xFFF7FFFF248#define S_000040_VIPH_INT_EN(x) (((x) & 0x1) << 24)249#define G_000040_VIPH_INT_EN(x) (((x) >> 24) & 0x1)250#define C_000040_VIPH_INT_EN 0xFEFFFFFF251#define S_000040_SW_INT_EN(x) (((x) & 0x1) << 25)252#define G_000040_SW_INT_EN(x) (((x) >> 25) & 0x1)253#define C_000040_SW_INT_EN 0xFDFFFFFF254#define S_000040_GEYSERVILLE(x) (((x) & 0x1) << 27)255#define G_000040_GEYSERVILLE(x) (((x) >> 27) & 0x1)256#define C_000040_GEYSERVILLE 0xF7FFFFFF257#define S_000040_HDCP_AUTHORIZED_INT(x) (((x) & 0x1) << 28)258#define G_000040_HDCP_AUTHORIZED_INT(x) (((x) >> 28) & 0x1)259#define C_000040_HDCP_AUTHORIZED_INT 0xEFFFFFFF260#define S_000040_DVI_I2C_INT(x) (((x) & 0x1) << 29)261#define G_000040_DVI_I2C_INT(x) (((x) >> 29) & 0x1)262#define C_000040_DVI_I2C_INT 0xDFFFFFFF263#define S_000040_GUIDMA(x) (((x) & 0x1) << 30)264#define G_000040_GUIDMA(x) (((x) >> 30) & 0x1)265#define C_000040_GUIDMA 0xBFFFFFFF266#define S_000040_VIDDMA(x) (((x) & 0x1) << 31)267#define G_000040_VIDDMA(x) (((x) >> 31) & 0x1)268#define C_000040_VIDDMA 0x7FFFFFFF269#define R_000044_GEN_INT_STATUS 0x000044270#define S_000044_CRTC_VBLANK_STAT(x) (((x) & 0x1) << 0)271#define G_000044_CRTC_VBLANK_STAT(x) (((x) >> 0) & 0x1)272#define C_000044_CRTC_VBLANK_STAT 0xFFFFFFFE273#define S_000044_CRTC_VBLANK_STAT_AK(x) (((x) & 0x1) << 0)274#define G_000044_CRTC_VBLANK_STAT_AK(x) (((x) >> 0) & 0x1)275#define C_000044_CRTC_VBLANK_STAT_AK 0xFFFFFFFE276#define S_000044_CRTC_VLINE_STAT(x) (((x) & 0x1) << 1)277#define G_000044_CRTC_VLINE_STAT(x) (((x) >> 1) & 0x1)278#define C_000044_CRTC_VLINE_STAT 0xFFFFFFFD279#define S_000044_CRTC_VLINE_STAT_AK(x) (((x) & 0x1) << 1)280#define G_000044_CRTC_VLINE_STAT_AK(x) (((x) >> 1) & 0x1)281#define C_000044_CRTC_VLINE_STAT_AK 0xFFFFFFFD282#define S_000044_CRTC_VSYNC_STAT(x) (((x) & 0x1) << 2)283#define G_000044_CRTC_VSYNC_STAT(x) (((x) >> 2) & 0x1)284#define C_000044_CRTC_VSYNC_STAT 0xFFFFFFFB285#define S_000044_CRTC_VSYNC_STAT_AK(x) (((x) & 0x1) << 2)286#define G_000044_CRTC_VSYNC_STAT_AK(x) (((x) >> 2) & 0x1)287#define C_000044_CRTC_VSYNC_STAT_AK 0xFFFFFFFB288#define S_000044_SNAPSHOT_STAT(x) (((x) & 0x1) << 3)289#define G_000044_SNAPSHOT_STAT(x) (((x) >> 3) & 0x1)290#define C_000044_SNAPSHOT_STAT 0xFFFFFFF7291#define S_000044_SNAPSHOT_STAT_AK(x) (((x) & 0x1) << 3)292#define G_000044_SNAPSHOT_STAT_AK(x) (((x) >> 3) & 0x1)293#define C_000044_SNAPSHOT_STAT_AK 0xFFFFFFF7294#define S_000044_FP_DETECT_STAT(x) (((x) & 0x1) << 4)295#define G_000044_FP_DETECT_STAT(x) (((x) >> 4) & 0x1)296#define C_000044_FP_DETECT_STAT 0xFFFFFFEF297#define S_000044_FP_DETECT_STAT_AK(x) (((x) & 0x1) << 4)298#define G_000044_FP_DETECT_STAT_AK(x) (((x) >> 4) & 0x1)299#define C_000044_FP_DETECT_STAT_AK 0xFFFFFFEF300#define S_000044_CRTC2_VLINE_STAT(x) (((x) & 0x1) << 5)301#define G_000044_CRTC2_VLINE_STAT(x) (((x) >> 5) & 0x1)302#define C_000044_CRTC2_VLINE_STAT 0xFFFFFFDF303#define S_000044_CRTC2_VLINE_STAT_AK(x) (((x) & 0x1) << 5)304#define G_000044_CRTC2_VLINE_STAT_AK(x) (((x) >> 5) & 0x1)305#define C_000044_CRTC2_VLINE_STAT_AK 0xFFFFFFDF306#define S_000044_CRTC2_VSYNC_STAT(x) (((x) & 0x1) << 6)307#define G_000044_CRTC2_VSYNC_STAT(x) (((x) >> 6) & 0x1)308#define C_000044_CRTC2_VSYNC_STAT 0xFFFFFFBF309#define S_000044_CRTC2_VSYNC_STAT_AK(x) (((x) & 0x1) << 6)310#define G_000044_CRTC2_VSYNC_STAT_AK(x) (((x) >> 6) & 0x1)311#define C_000044_CRTC2_VSYNC_STAT_AK 0xFFFFFFBF312#define S_000044_SNAPSHOT2_STAT(x) (((x) & 0x1) << 7)313#define G_000044_SNAPSHOT2_STAT(x) (((x) >> 7) & 0x1)314#define C_000044_SNAPSHOT2_STAT 0xFFFFFF7F315#define S_000044_SNAPSHOT2_STAT_AK(x) (((x) & 0x1) << 7)316#define G_000044_SNAPSHOT2_STAT_AK(x) (((x) >> 7) & 0x1)317#define C_000044_SNAPSHOT2_STAT_AK 0xFFFFFF7F318#define S_000044_CAP0_INT_ACTIVE(x) (((x) & 0x1) << 8)319#define G_000044_CAP0_INT_ACTIVE(x) (((x) >> 8) & 0x1)320#define C_000044_CAP0_INT_ACTIVE 0xFFFFFEFF321#define S_000044_CRTC2_VBLANK_STAT(x) (((x) & 0x1) << 9)322#define G_000044_CRTC2_VBLANK_STAT(x) (((x) >> 9) & 0x1)323#define C_000044_CRTC2_VBLANK_STAT 0xFFFFFDFF324#define S_000044_CRTC2_VBLANK_STAT_AK(x) (((x) & 0x1) << 9)325#define G_000044_CRTC2_VBLANK_STAT_AK(x) (((x) >> 9) & 0x1)326#define C_000044_CRTC2_VBLANK_STAT_AK 0xFFFFFDFF327#define S_000044_FP2_DETECT_STAT(x) (((x) & 0x1) << 10)328#define G_000044_FP2_DETECT_STAT(x) (((x) >> 10) & 0x1)329#define C_000044_FP2_DETECT_STAT 0xFFFFFBFF330#define S_000044_FP2_DETECT_STAT_AK(x) (((x) & 0x1) << 10)331#define G_000044_FP2_DETECT_STAT_AK(x) (((x) >> 10) & 0x1)332#define C_000044_FP2_DETECT_STAT_AK 0xFFFFFBFF333#define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) & 0x1) << 11)334#define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT(x) (((x) >> 11) & 0x1)335#define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT 0xFFFFF7FF336#define S_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) & 0x1) << 11)337#define G_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK(x) (((x) >> 11) & 0x1)338#define C_000044_VSYNC_DIFF_OVER_LIMIT_STAT_AK 0xFFFFF7FF339#define S_000044_DMA_VIPH0_INT(x) (((x) & 0x1) << 12)340#define G_000044_DMA_VIPH0_INT(x) (((x) >> 12) & 0x1)341#define C_000044_DMA_VIPH0_INT 0xFFFFEFFF342#define S_000044_DMA_VIPH0_INT_AK(x) (((x) & 0x1) << 12)343#define G_000044_DMA_VIPH0_INT_AK(x) (((x) >> 12) & 0x1)344#define C_000044_DMA_VIPH0_INT_AK 0xFFFFEFFF345#define S_000044_DMA_VIPH1_INT(x) (((x) & 0x1) << 13)346#define G_000044_DMA_VIPH1_INT(x) (((x) >> 13) & 0x1)347#define C_000044_DMA_VIPH1_INT 0xFFFFDFFF348#define S_000044_DMA_VIPH1_INT_AK(x) (((x) & 0x1) << 13)349#define G_000044_DMA_VIPH1_INT_AK(x) (((x) >> 13) & 0x1)350#define C_000044_DMA_VIPH1_INT_AK 0xFFFFDFFF351#define S_000044_DMA_VIPH2_INT(x) (((x) & 0x1) << 14)352#define G_000044_DMA_VIPH2_INT(x) (((x) >> 14) & 0x1)353#define C_000044_DMA_VIPH2_INT 0xFFFFBFFF354#define S_000044_DMA_VIPH2_INT_AK(x) (((x) & 0x1) << 14)355#define G_000044_DMA_VIPH2_INT_AK(x) (((x) >> 14) & 0x1)356#define C_000044_DMA_VIPH2_INT_AK 0xFFFFBFFF357#define S_000044_DMA_VIPH3_INT(x) (((x) & 0x1) << 15)358#define G_000044_DMA_VIPH3_INT(x) (((x) >> 15) & 0x1)359#define C_000044_DMA_VIPH3_INT 0xFFFF7FFF360#define S_000044_DMA_VIPH3_INT_AK(x) (((x) & 0x1) << 15)361#define G_000044_DMA_VIPH3_INT_AK(x) (((x) >> 15) & 0x1)362#define C_000044_DMA_VIPH3_INT_AK 0xFFFF7FFF363#define S_000044_I2C_INT(x) (((x) & 0x1) << 17)364#define G_000044_I2C_INT(x) (((x) >> 17) & 0x1)365#define C_000044_I2C_INT 0xFFFDFFFF366#define S_000044_I2C_INT_AK(x) (((x) & 0x1) << 17)367#define G_000044_I2C_INT_AK(x) (((x) >> 17) & 0x1)368#define C_000044_I2C_INT_AK 0xFFFDFFFF369#define S_000044_GUI_IDLE_STAT(x) (((x) & 0x1) << 19)370#define G_000044_GUI_IDLE_STAT(x) (((x) >> 19) & 0x1)371#define C_000044_GUI_IDLE_STAT 0xFFF7FFFF372#define S_000044_GUI_IDLE_STAT_AK(x) (((x) & 0x1) << 19)373#define G_000044_GUI_IDLE_STAT_AK(x) (((x) >> 19) & 0x1)374#define C_000044_GUI_IDLE_STAT_AK 0xFFF7FFFF375#define S_000044_VIPH_INT(x) (((x) & 0x1) << 24)376#define G_000044_VIPH_INT(x) (((x) >> 24) & 0x1)377#define C_000044_VIPH_INT 0xFEFFFFFF378#define S_000044_SW_INT(x) (((x) & 0x1) << 25)379#define G_000044_SW_INT(x) (((x) >> 25) & 0x1)380#define C_000044_SW_INT 0xFDFFFFFF381#define S_000044_SW_INT_AK(x) (((x) & 0x1) << 25)382#define G_000044_SW_INT_AK(x) (((x) >> 25) & 0x1)383#define C_000044_SW_INT_AK 0xFDFFFFFF384#define S_000044_SW_INT_SET(x) (((x) & 0x1) << 26)385#define G_000044_SW_INT_SET(x) (((x) >> 26) & 0x1)386#define C_000044_SW_INT_SET 0xFBFFFFFF387#define S_000044_GEYSERVILLE_STAT(x) (((x) & 0x1) << 27)388#define G_000044_GEYSERVILLE_STAT(x) (((x) >> 27) & 0x1)389#define C_000044_GEYSERVILLE_STAT 0xF7FFFFFF390#define S_000044_GEYSERVILLE_STAT_AK(x) (((x) & 0x1) << 27)391#define G_000044_GEYSERVILLE_STAT_AK(x) (((x) >> 27) & 0x1)392#define C_000044_GEYSERVILLE_STAT_AK 0xF7FFFFFF393#define S_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) & 0x1) << 28)394#define G_000044_HDCP_AUTHORIZED_INT_STAT(x) (((x) >> 28) & 0x1)395#define C_000044_HDCP_AUTHORIZED_INT_STAT 0xEFFFFFFF396#define S_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) & 0x1) << 28)397#define G_000044_HDCP_AUTHORIZED_INT_AK(x) (((x) >> 28) & 0x1)398#define C_000044_HDCP_AUTHORIZED_INT_AK 0xEFFFFFFF399#define S_000044_DVI_I2C_INT_STAT(x) (((x) & 0x1) << 29)400#define G_000044_DVI_I2C_INT_STAT(x) (((x) >> 29) & 0x1)401#define C_000044_DVI_I2C_INT_STAT 0xDFFFFFFF402#define S_000044_DVI_I2C_INT_AK(x) (((x) & 0x1) << 29)403#define G_000044_DVI_I2C_INT_AK(x) (((x) >> 29) & 0x1)404#define C_000044_DVI_I2C_INT_AK 0xDFFFFFFF405#define S_000044_GUIDMA_STAT(x) (((x) & 0x1) << 30)406#define G_000044_GUIDMA_STAT(x) (((x) >> 30) & 0x1)407#define C_000044_GUIDMA_STAT 0xBFFFFFFF408#define S_000044_GUIDMA_AK(x) (((x) & 0x1) << 30)409#define G_000044_GUIDMA_AK(x) (((x) >> 30) & 0x1)410#define C_000044_GUIDMA_AK 0xBFFFFFFF411#define S_000044_VIDDMA_STAT(x) (((x) & 0x1) << 31)412#define G_000044_VIDDMA_STAT(x) (((x) >> 31) & 0x1)413#define C_000044_VIDDMA_STAT 0x7FFFFFFF414#define S_000044_VIDDMA_AK(x) (((x) & 0x1) << 31)415#define G_000044_VIDDMA_AK(x) (((x) >> 31) & 0x1)416#define C_000044_VIDDMA_AK 0x7FFFFFFF417#define R_000050_CRTC_GEN_CNTL 0x000050418#define S_000050_CRTC_DBL_SCAN_EN(x) (((x) & 0x1) << 0)419#define G_000050_CRTC_DBL_SCAN_EN(x) (((x) >> 0) & 0x1)420#define C_000050_CRTC_DBL_SCAN_EN 0xFFFFFFFE421#define S_000050_CRTC_INTERLACE_EN(x) (((x) & 0x1) << 1)422#define G_000050_CRTC_INTERLACE_EN(x) (((x) >> 1) & 0x1)423#define C_000050_CRTC_INTERLACE_EN 0xFFFFFFFD424#define S_000050_CRTC_C_SYNC_EN(x) (((x) & 0x1) << 4)425#define G_000050_CRTC_C_SYNC_EN(x) (((x) >> 4) & 0x1)426#define C_000050_CRTC_C_SYNC_EN 0xFFFFFFEF427#define S_000050_CRTC_PIX_WIDTH(x) (((x) & 0xF) << 8)428#define G_000050_CRTC_PIX_WIDTH(x) (((x) >> 8) & 0xF)429#define C_000050_CRTC_PIX_WIDTH 0xFFFFF0FF430#define S_000050_CRTC_ICON_EN(x) (((x) & 0x1) << 15)431#define G_000050_CRTC_ICON_EN(x) (((x) >> 15) & 0x1)432#define C_000050_CRTC_ICON_EN 0xFFFF7FFF433#define S_000050_CRTC_CUR_EN(x) (((x) & 0x1) << 16)434#define G_000050_CRTC_CUR_EN(x) (((x) >> 16) & 0x1)435#define C_000050_CRTC_CUR_EN 0xFFFEFFFF436#define S_000050_CRTC_VSTAT_MODE(x) (((x) & 0x3) << 17)437#define G_000050_CRTC_VSTAT_MODE(x) (((x) >> 17) & 0x3)438#define C_000050_CRTC_VSTAT_MODE 0xFFF9FFFF439#define S_000050_CRTC_CUR_MODE(x) (((x) & 0x7) << 20)440#define G_000050_CRTC_CUR_MODE(x) (((x) >> 20) & 0x7)441#define C_000050_CRTC_CUR_MODE 0xFF8FFFFF442#define S_000050_CRTC_EXT_DISP_EN(x) (((x) & 0x1) << 24)443#define G_000050_CRTC_EXT_DISP_EN(x) (((x) >> 24) & 0x1)444#define C_000050_CRTC_EXT_DISP_EN 0xFEFFFFFF445#define S_000050_CRTC_EN(x) (((x) & 0x1) << 25)446#define G_000050_CRTC_EN(x) (((x) >> 25) & 0x1)447#define C_000050_CRTC_EN 0xFDFFFFFF448#define S_000050_CRTC_DISP_REQ_EN_B(x) (((x) & 0x1) << 26)449#define G_000050_CRTC_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1)450#define C_000050_CRTC_DISP_REQ_EN_B 0xFBFFFFFF451#define R_000054_CRTC_EXT_CNTL 0x000054452#define S_000054_CRTC_VGA_XOVERSCAN(x) (((x) & 0x1) << 0)453#define G_000054_CRTC_VGA_XOVERSCAN(x) (((x) >> 0) & 0x1)454#define C_000054_CRTC_VGA_XOVERSCAN 0xFFFFFFFE455#define S_000054_VGA_BLINK_RATE(x) (((x) & 0x3) << 1)456#define G_000054_VGA_BLINK_RATE(x) (((x) >> 1) & 0x3)457#define C_000054_VGA_BLINK_RATE 0xFFFFFFF9458#define S_000054_VGA_ATI_LINEAR(x) (((x) & 0x1) << 3)459#define G_000054_VGA_ATI_LINEAR(x) (((x) >> 3) & 0x1)460#define C_000054_VGA_ATI_LINEAR 0xFFFFFFF7461#define S_000054_VGA_128KAP_PAGING(x) (((x) & 0x1) << 4)462#define G_000054_VGA_128KAP_PAGING(x) (((x) >> 4) & 0x1)463#define C_000054_VGA_128KAP_PAGING 0xFFFFFFEF464#define S_000054_VGA_TEXT_132(x) (((x) & 0x1) << 5)465#define G_000054_VGA_TEXT_132(x) (((x) >> 5) & 0x1)466#define C_000054_VGA_TEXT_132 0xFFFFFFDF467#define S_000054_VGA_XCRT_CNT_EN(x) (((x) & 0x1) << 6)468#define G_000054_VGA_XCRT_CNT_EN(x) (((x) >> 6) & 0x1)469#define C_000054_VGA_XCRT_CNT_EN 0xFFFFFFBF470#define S_000054_CRTC_HSYNC_DIS(x) (((x) & 0x1) << 8)471#define G_000054_CRTC_HSYNC_DIS(x) (((x) >> 8) & 0x1)472#define C_000054_CRTC_HSYNC_DIS 0xFFFFFEFF473#define S_000054_CRTC_VSYNC_DIS(x) (((x) & 0x1) << 9)474#define G_000054_CRTC_VSYNC_DIS(x) (((x) >> 9) & 0x1)475#define C_000054_CRTC_VSYNC_DIS 0xFFFFFDFF476#define S_000054_CRTC_DISPLAY_DIS(x) (((x) & 0x1) << 10)477#define G_000054_CRTC_DISPLAY_DIS(x) (((x) >> 10) & 0x1)478#define C_000054_CRTC_DISPLAY_DIS 0xFFFFFBFF479#define S_000054_CRTC_SYNC_TRISTATE(x) (((x) & 0x1) << 11)480#define G_000054_CRTC_SYNC_TRISTATE(x) (((x) >> 11) & 0x1)481#define C_000054_CRTC_SYNC_TRISTATE 0xFFFFF7FF482#define S_000054_CRTC_HSYNC_TRISTATE(x) (((x) & 0x1) << 12)483#define G_000054_CRTC_HSYNC_TRISTATE(x) (((x) >> 12) & 0x1)484#define C_000054_CRTC_HSYNC_TRISTATE 0xFFFFEFFF485#define S_000054_CRTC_VSYNC_TRISTATE(x) (((x) & 0x1) << 13)486#define G_000054_CRTC_VSYNC_TRISTATE(x) (((x) >> 13) & 0x1)487#define C_000054_CRTC_VSYNC_TRISTATE 0xFFFFDFFF488#define S_000054_CRT_ON(x) (((x) & 0x1) << 15)489#define G_000054_CRT_ON(x) (((x) >> 15) & 0x1)490#define C_000054_CRT_ON 0xFFFF7FFF491#define S_000054_VGA_CUR_B_TEST(x) (((x) & 0x1) << 17)492#define G_000054_VGA_CUR_B_TEST(x) (((x) >> 17) & 0x1)493#define C_000054_VGA_CUR_B_TEST 0xFFFDFFFF494#define S_000054_VGA_PACK_DIS(x) (((x) & 0x1) << 18)495#define G_000054_VGA_PACK_DIS(x) (((x) >> 18) & 0x1)496#define C_000054_VGA_PACK_DIS 0xFFFBFFFF497#define S_000054_VGA_MEM_PS_EN(x) (((x) & 0x1) << 19)498#define G_000054_VGA_MEM_PS_EN(x) (((x) >> 19) & 0x1)499#define C_000054_VGA_MEM_PS_EN 0xFFF7FFFF500#define S_000054_VCRTC_IDX_MASTER(x) (((x) & 0x7F) << 24)501#define G_000054_VCRTC_IDX_MASTER(x) (((x) >> 24) & 0x7F)502#define C_000054_VCRTC_IDX_MASTER 0x80FFFFFF503#define R_000148_MC_FB_LOCATION 0x000148504#define S_000148_MC_FB_START(x) (((x) & 0xFFFF) << 0)505#define G_000148_MC_FB_START(x) (((x) >> 0) & 0xFFFF)506#define C_000148_MC_FB_START 0xFFFF0000507#define S_000148_MC_FB_TOP(x) (((x) & 0xFFFF) << 16)508#define G_000148_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF)509#define C_000148_MC_FB_TOP 0x0000FFFF510#define R_00014C_MC_AGP_LOCATION 0x00014C511#define S_00014C_MC_AGP_START(x) (((x) & 0xFFFF) << 0)512#define G_00014C_MC_AGP_START(x) (((x) >> 0) & 0xFFFF)513#define C_00014C_MC_AGP_START 0xFFFF0000514#define S_00014C_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16)515#define G_00014C_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF)516#define C_00014C_MC_AGP_TOP 0x0000FFFF517#define R_000170_AGP_BASE 0x000170518#define S_000170_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)519#define G_000170_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)520#define C_000170_AGP_BASE_ADDR 0x00000000521#define R_00023C_DISPLAY_BASE_ADDR 0x00023C522#define S_00023C_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)523#define G_00023C_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)524#define C_00023C_DISPLAY_BASE_ADDR 0x00000000525#define R_000260_CUR_OFFSET 0x000260526#define S_000260_CUR_OFFSET(x) (((x) & 0x7FFFFFF) << 0)527#define G_000260_CUR_OFFSET(x) (((x) >> 0) & 0x7FFFFFF)528#define C_000260_CUR_OFFSET 0xF8000000529#define S_000260_CUR_LOCK(x) (((x) & 0x1) << 31)530#define G_000260_CUR_LOCK(x) (((x) >> 31) & 0x1)531#define C_000260_CUR_LOCK 0x7FFFFFFF532#define R_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00033C533#define S_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)534#define G_00033C_CRTC2_DISPLAY_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)535#define C_00033C_CRTC2_DISPLAY_BASE_ADDR 0x00000000536#define R_000360_CUR2_OFFSET 0x000360537#define S_000360_CUR2_OFFSET(x) (((x) & 0x7FFFFFF) << 0)538#define G_000360_CUR2_OFFSET(x) (((x) >> 0) & 0x7FFFFFF)539#define C_000360_CUR2_OFFSET 0xF8000000540#define S_000360_CUR2_LOCK(x) (((x) & 0x1) << 31)541#define G_000360_CUR2_LOCK(x) (((x) >> 31) & 0x1)542#define C_000360_CUR2_LOCK 0x7FFFFFFF543#define R_0003C2_GENMO_WT 0x0003C2544#define S_0003C2_GENMO_MONO_ADDRESS_B(x) (((x) & 0x1) << 0)545#define G_0003C2_GENMO_MONO_ADDRESS_B(x) (((x) >> 0) & 0x1)546#define C_0003C2_GENMO_MONO_ADDRESS_B 0xFE547#define S_0003C2_VGA_RAM_EN(x) (((x) & 0x1) << 1)548#define G_0003C2_VGA_RAM_EN(x) (((x) >> 1) & 0x1)549#define C_0003C2_VGA_RAM_EN 0xFD550#define S_0003C2_VGA_CKSEL(x) (((x) & 0x3) << 2)551#define G_0003C2_VGA_CKSEL(x) (((x) >> 2) & 0x3)552#define C_0003C2_VGA_CKSEL 0xF3553#define S_0003C2_ODD_EVEN_MD_PGSEL(x) (((x) & 0x1) << 5)554#define G_0003C2_ODD_EVEN_MD_PGSEL(x) (((x) >> 5) & 0x1)555#define C_0003C2_ODD_EVEN_MD_PGSEL 0xDF556#define S_0003C2_VGA_HSYNC_POL(x) (((x) & 0x1) << 6)557#define G_0003C2_VGA_HSYNC_POL(x) (((x) >> 6) & 0x1)558#define C_0003C2_VGA_HSYNC_POL 0xBF559#define S_0003C2_VGA_VSYNC_POL(x) (((x) & 0x1) << 7)560#define G_0003C2_VGA_VSYNC_POL(x) (((x) >> 7) & 0x1)561#define C_0003C2_VGA_VSYNC_POL 0x7F562#define R_0003F8_CRTC2_GEN_CNTL 0x0003F8563#define S_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) & 0x1) << 0)564#define G_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) >> 0) & 0x1)565#define C_0003F8_CRTC2_DBL_SCAN_EN 0xFFFFFFFE566#define S_0003F8_CRTC2_INTERLACE_EN(x) (((x) & 0x1) << 1)567#define G_0003F8_CRTC2_INTERLACE_EN(x) (((x) >> 1) & 0x1)568#define C_0003F8_CRTC2_INTERLACE_EN 0xFFFFFFFD569#define S_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) & 0x1) << 4)570#define G_0003F8_CRTC2_SYNC_TRISTATE(x) (((x) >> 4) & 0x1)571#define C_0003F8_CRTC2_SYNC_TRISTATE 0xFFFFFFEF572#define S_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) & 0x1) << 5)573#define G_0003F8_CRTC2_HSYNC_TRISTATE(x) (((x) >> 5) & 0x1)574#define C_0003F8_CRTC2_HSYNC_TRISTATE 0xFFFFFFDF575#define S_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) & 0x1) << 6)576#define G_0003F8_CRTC2_VSYNC_TRISTATE(x) (((x) >> 6) & 0x1)577#define C_0003F8_CRTC2_VSYNC_TRISTATE 0xFFFFFFBF578#define S_0003F8_CRT2_ON(x) (((x) & 0x1) << 7)579#define G_0003F8_CRT2_ON(x) (((x) >> 7) & 0x1)580#define C_0003F8_CRT2_ON 0xFFFFFF7F581#define S_0003F8_CRTC2_PIX_WIDTH(x) (((x) & 0xF) << 8)582#define G_0003F8_CRTC2_PIX_WIDTH(x) (((x) >> 8) & 0xF)583#define C_0003F8_CRTC2_PIX_WIDTH 0xFFFFF0FF584#define S_0003F8_CRTC2_ICON_EN(x) (((x) & 0x1) << 15)585#define G_0003F8_CRTC2_ICON_EN(x) (((x) >> 15) & 0x1)586#define C_0003F8_CRTC2_ICON_EN 0xFFFF7FFF587#define S_0003F8_CRTC2_CUR_EN(x) (((x) & 0x1) << 16)588#define G_0003F8_CRTC2_CUR_EN(x) (((x) >> 16) & 0x1)589#define C_0003F8_CRTC2_CUR_EN 0xFFFEFFFF590#define S_0003F8_CRTC2_CUR_MODE(x) (((x) & 0x7) << 20)591#define G_0003F8_CRTC2_CUR_MODE(x) (((x) >> 20) & 0x7)592#define C_0003F8_CRTC2_CUR_MODE 0xFF8FFFFF593#define S_0003F8_CRTC2_DISPLAY_DIS(x) (((x) & 0x1) << 23)594#define G_0003F8_CRTC2_DISPLAY_DIS(x) (((x) >> 23) & 0x1)595#define C_0003F8_CRTC2_DISPLAY_DIS 0xFF7FFFFF596#define S_0003F8_CRTC2_EN(x) (((x) & 0x1) << 25)597#define G_0003F8_CRTC2_EN(x) (((x) >> 25) & 0x1)598#define C_0003F8_CRTC2_EN 0xFDFFFFFF599#define S_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) & 0x1) << 26)600#define G_0003F8_CRTC2_DISP_REQ_EN_B(x) (((x) >> 26) & 0x1)601#define C_0003F8_CRTC2_DISP_REQ_EN_B 0xFBFFFFFF602#define S_0003F8_CRTC2_C_SYNC_EN(x) (((x) & 0x1) << 27)603#define G_0003F8_CRTC2_C_SYNC_EN(x) (((x) >> 27) & 0x1)604#define C_0003F8_CRTC2_C_SYNC_EN 0xF7FFFFFF605#define S_0003F8_CRTC2_HSYNC_DIS(x) (((x) & 0x1) << 28)606#define G_0003F8_CRTC2_HSYNC_DIS(x) (((x) >> 28) & 0x1)607#define C_0003F8_CRTC2_HSYNC_DIS 0xEFFFFFFF608#define S_0003F8_CRTC2_VSYNC_DIS(x) (((x) & 0x1) << 29)609#define G_0003F8_CRTC2_VSYNC_DIS(x) (((x) >> 29) & 0x1)610#define C_0003F8_CRTC2_VSYNC_DIS 0xDFFFFFFF611#define R_000420_OV0_SCALE_CNTL 0x000420612#define S_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) & 0x1) << 1)613#define G_000420_OV0_NO_READ_BEHIND_SCAN(x) (((x) >> 1) & 0x1)614#define C_000420_OV0_NO_READ_BEHIND_SCAN 0xFFFFFFFD615#define S_000420_OV0_HORZ_PICK_NEAREST(x) (((x) & 0x1) << 2)616#define G_000420_OV0_HORZ_PICK_NEAREST(x) (((x) >> 2) & 0x1)617#define C_000420_OV0_HORZ_PICK_NEAREST 0xFFFFFFFB618#define S_000420_OV0_VERT_PICK_NEAREST(x) (((x) & 0x1) << 3)619#define G_000420_OV0_VERT_PICK_NEAREST(x) (((x) >> 3) & 0x1)620#define C_000420_OV0_VERT_PICK_NEAREST 0xFFFFFFF7621#define S_000420_OV0_SIGNED_UV(x) (((x) & 0x1) << 4)622#define G_000420_OV0_SIGNED_UV(x) (((x) >> 4) & 0x1)623#define C_000420_OV0_SIGNED_UV 0xFFFFFFEF624#define S_000420_OV0_GAMMA_SEL(x) (((x) & 0x7) << 5)625#define G_000420_OV0_GAMMA_SEL(x) (((x) >> 5) & 0x7)626#define C_000420_OV0_GAMMA_SEL 0xFFFFFF1F627#define S_000420_OV0_SURFACE_FORMAT(x) (((x) & 0xF) << 8)628#define G_000420_OV0_SURFACE_FORMAT(x) (((x) >> 8) & 0xF)629#define C_000420_OV0_SURFACE_FORMAT 0xFFFFF0FF630#define S_000420_OV0_ADAPTIVE_DEINT(x) (((x) & 0x1) << 12)631#define G_000420_OV0_ADAPTIVE_DEINT(x) (((x) >> 12) & 0x1)632#define C_000420_OV0_ADAPTIVE_DEINT 0xFFFFEFFF633#define S_000420_OV0_CRTC_SEL(x) (((x) & 0x1) << 14)634#define G_000420_OV0_CRTC_SEL(x) (((x) >> 14) & 0x1)635#define C_000420_OV0_CRTC_SEL 0xFFFFBFFF636#define S_000420_OV0_BURST_PER_PLANE(x) (((x) & 0x7F) << 16)637#define G_000420_OV0_BURST_PER_PLANE(x) (((x) >> 16) & 0x7F)638#define C_000420_OV0_BURST_PER_PLANE 0xFF80FFFF639#define S_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) & 0x1) << 24)640#define G_000420_OV0_DOUBLE_BUFFER_REGS(x) (((x) >> 24) & 0x1)641#define C_000420_OV0_DOUBLE_BUFFER_REGS 0xFEFFFFFF642#define S_000420_OV0_BANDWIDTH(x) (((x) & 0x1) << 26)643#define G_000420_OV0_BANDWIDTH(x) (((x) >> 26) & 0x1)644#define C_000420_OV0_BANDWIDTH 0xFBFFFFFF645#define S_000420_OV0_LIN_TRANS_BYPASS(x) (((x) & 0x1) << 28)646#define G_000420_OV0_LIN_TRANS_BYPASS(x) (((x) >> 28) & 0x1)647#define C_000420_OV0_LIN_TRANS_BYPASS 0xEFFFFFFF648#define S_000420_OV0_INT_EMU(x) (((x) & 0x1) << 29)649#define G_000420_OV0_INT_EMU(x) (((x) >> 29) & 0x1)650#define C_000420_OV0_INT_EMU 0xDFFFFFFF651#define S_000420_OV0_OVERLAY_EN(x) (((x) & 0x1) << 30)652#define G_000420_OV0_OVERLAY_EN(x) (((x) >> 30) & 0x1)653#define C_000420_OV0_OVERLAY_EN 0xBFFFFFFF654#define S_000420_OV0_SOFT_RESET(x) (((x) & 0x1) << 31)655#define G_000420_OV0_SOFT_RESET(x) (((x) >> 31) & 0x1)656#define C_000420_OV0_SOFT_RESET 0x7FFFFFFF657#define R_00070C_CP_RB_RPTR_ADDR 0x00070C658#define S_00070C_RB_RPTR_SWAP(x) (((x) & 0x3) << 0)659#define G_00070C_RB_RPTR_SWAP(x) (((x) >> 0) & 0x3)660#define C_00070C_RB_RPTR_SWAP 0xFFFFFFFC661#define S_00070C_RB_RPTR_ADDR(x) (((x) & 0x3FFFFFFF) << 2)662#define G_00070C_RB_RPTR_ADDR(x) (((x) >> 2) & 0x3FFFFFFF)663#define C_00070C_RB_RPTR_ADDR 0x00000003664#define R_000740_CP_CSQ_CNTL 0x000740665#define S_000740_CSQ_CNT_PRIMARY(x) (((x) & 0xFF) << 0)666#define G_000740_CSQ_CNT_PRIMARY(x) (((x) >> 0) & 0xFF)667#define C_000740_CSQ_CNT_PRIMARY 0xFFFFFF00668#define S_000740_CSQ_CNT_INDIRECT(x) (((x) & 0xFF) << 8)669#define G_000740_CSQ_CNT_INDIRECT(x) (((x) >> 8) & 0xFF)670#define C_000740_CSQ_CNT_INDIRECT 0xFFFF00FF671#define S_000740_CSQ_MODE(x) (((x) & 0xF) << 28)672#define G_000740_CSQ_MODE(x) (((x) >> 28) & 0xF)673#define C_000740_CSQ_MODE 0x0FFFFFFF674#define R_000770_SCRATCH_UMSK 0x000770675#define S_000770_SCRATCH_UMSK(x) (((x) & 0x3F) << 0)676#define G_000770_SCRATCH_UMSK(x) (((x) >> 0) & 0x3F)677#define C_000770_SCRATCH_UMSK 0xFFFFFFC0678#define S_000770_SCRATCH_SWAP(x) (((x) & 0x3) << 16)679#define G_000770_SCRATCH_SWAP(x) (((x) >> 16) & 0x3)680#define C_000770_SCRATCH_SWAP 0xFFFCFFFF681#define R_000774_SCRATCH_ADDR 0x000774682#define S_000774_SCRATCH_ADDR(x) (((x) & 0x7FFFFFF) << 5)683#define G_000774_SCRATCH_ADDR(x) (((x) >> 5) & 0x7FFFFFF)684#define C_000774_SCRATCH_ADDR 0x0000001F685#define R_0007C0_CP_STAT 0x0007C0686#define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0)687#define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1)688#define C_0007C0_MRU_BUSY 0xFFFFFFFE689#define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1)690#define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1)691#define C_0007C0_MWU_BUSY 0xFFFFFFFD692#define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2)693#define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1)694#define C_0007C0_RSIU_BUSY 0xFFFFFFFB695#define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3)696#define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1)697#define C_0007C0_RCIU_BUSY 0xFFFFFFF7698#define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9)699#define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1)700#define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF701#define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10)702#define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1)703#define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF704#define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11)705#define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1)706#define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF707#define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12)708#define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1)709#define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF710#define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13)711#define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1)712#define C_0007C0_CSI_BUSY 0xFFFFDFFF713#define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28)714#define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1)715#define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF716#define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29)717#define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1)718#define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF719#define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30)720#define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1)721#define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF722#define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31)723#define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1)724#define C_0007C0_CP_BUSY 0x7FFFFFFF725#define R_000E40_RBBM_STATUS 0x000E40726#define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0)727#define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F)728#define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80729#define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8)730#define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1)731#define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF732#define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9)733#define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1)734#define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF735#define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10)736#define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1)737#define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF738#define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11)739#define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1)740#define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF741#define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12)742#define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1)743#define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF744#define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13)745#define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1)746#define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF747#define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14)748#define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1)749#define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF750#define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15)751#define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1)752#define C_000E40_ENG_EV_BUSY 0xFFFF7FFF753#define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16)754#define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1)755#define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF756#define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17)757#define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1)758#define C_000E40_E2_BUSY 0xFFFDFFFF759#define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18)760#define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1)761#define C_000E40_RB2D_BUSY 0xFFFBFFFF762#define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19)763#define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1)764#define C_000E40_RB3D_BUSY 0xFFF7FFFF765#define S_000E40_SE_BUSY(x) (((x) & 0x1) << 20)766#define G_000E40_SE_BUSY(x) (((x) >> 20) & 0x1)767#define C_000E40_SE_BUSY 0xFFEFFFFF768#define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21)769#define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1)770#define C_000E40_RE_BUSY 0xFFDFFFFF771#define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22)772#define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1)773#define C_000E40_TAM_BUSY 0xFFBFFFFF774#define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23)775#define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1)776#define C_000E40_TDM_BUSY 0xFF7FFFFF777#define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24)778#define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1)779#define C_000E40_PB_BUSY 0xFEFFFFFF780#define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31)781#define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1)782#define C_000E40_GUI_ACTIVE 0x7FFFFFFF783 784 785#define R_00000D_SCLK_CNTL 0x00000D786#define S_00000D_SCLK_SRC_SEL(x) (((x) & 0x7) << 0)787#define G_00000D_SCLK_SRC_SEL(x) (((x) >> 0) & 0x7)788#define C_00000D_SCLK_SRC_SEL 0xFFFFFFF8789#define S_00000D_TCLK_SRC_SEL(x) (((x) & 0x7) << 8)790#define G_00000D_TCLK_SRC_SEL(x) (((x) >> 8) & 0x7)791#define C_00000D_TCLK_SRC_SEL 0xFFFFF8FF792#define S_00000D_FORCE_CP(x) (((x) & 0x1) << 16)793#define G_00000D_FORCE_CP(x) (((x) >> 16) & 0x1)794#define C_00000D_FORCE_CP 0xFFFEFFFF795#define S_00000D_FORCE_HDP(x) (((x) & 0x1) << 17)796#define G_00000D_FORCE_HDP(x) (((x) >> 17) & 0x1)797#define C_00000D_FORCE_HDP 0xFFFDFFFF798#define S_00000D_FORCE_DISP(x) (((x) & 0x1) << 18)799#define G_00000D_FORCE_DISP(x) (((x) >> 18) & 0x1)800#define C_00000D_FORCE_DISP 0xFFFBFFFF801#define S_00000D_FORCE_TOP(x) (((x) & 0x1) << 19)802#define G_00000D_FORCE_TOP(x) (((x) >> 19) & 0x1)803#define C_00000D_FORCE_TOP 0xFFF7FFFF804#define S_00000D_FORCE_E2(x) (((x) & 0x1) << 20)805#define G_00000D_FORCE_E2(x) (((x) >> 20) & 0x1)806#define C_00000D_FORCE_E2 0xFFEFFFFF807#define S_00000D_FORCE_SE(x) (((x) & 0x1) << 21)808#define G_00000D_FORCE_SE(x) (((x) >> 21) & 0x1)809#define C_00000D_FORCE_SE 0xFFDFFFFF810#define S_00000D_FORCE_IDCT(x) (((x) & 0x1) << 22)811#define G_00000D_FORCE_IDCT(x) (((x) >> 22) & 0x1)812#define C_00000D_FORCE_IDCT 0xFFBFFFFF813#define S_00000D_FORCE_VIP(x) (((x) & 0x1) << 23)814#define G_00000D_FORCE_VIP(x) (((x) >> 23) & 0x1)815#define C_00000D_FORCE_VIP 0xFF7FFFFF816#define S_00000D_FORCE_RE(x) (((x) & 0x1) << 24)817#define G_00000D_FORCE_RE(x) (((x) >> 24) & 0x1)818#define C_00000D_FORCE_RE 0xFEFFFFFF819#define S_00000D_FORCE_PB(x) (((x) & 0x1) << 25)820#define G_00000D_FORCE_PB(x) (((x) >> 25) & 0x1)821#define C_00000D_FORCE_PB 0xFDFFFFFF822#define S_00000D_FORCE_TAM(x) (((x) & 0x1) << 26)823#define G_00000D_FORCE_TAM(x) (((x) >> 26) & 0x1)824#define C_00000D_FORCE_TAM 0xFBFFFFFF825#define S_00000D_FORCE_TDM(x) (((x) & 0x1) << 27)826#define G_00000D_FORCE_TDM(x) (((x) >> 27) & 0x1)827#define C_00000D_FORCE_TDM 0xF7FFFFFF828#define S_00000D_FORCE_RB(x) (((x) & 0x1) << 28)829#define G_00000D_FORCE_RB(x) (((x) >> 28) & 0x1)830#define C_00000D_FORCE_RB 0xEFFFFFFF831 832/* PLL regs */833#define SCLK_CNTL 0xd834#define FORCE_HDP (1 << 17)835#define CLK_PWRMGT_CNTL 0x14836#define GLOBAL_PMAN_EN (1 << 10)837#define DISP_PM (1 << 20)838#define PLL_PWRMGT_CNTL 0x15839#define MPLL_TURNOFF (1 << 0)840#define SPLL_TURNOFF (1 << 1)841#define PPLL_TURNOFF (1 << 2)842#define P2PLL_TURNOFF (1 << 3)843#define TVPLL_TURNOFF (1 << 4)844#define MOBILE_SU (1 << 16)845#define SU_SCLK_USE_BCLK (1 << 17)846#define SCLK_CNTL2 0x1e847#define REDUCED_SPEED_SCLK_MODE (1 << 16)848#define REDUCED_SPEED_SCLK_SEL(x) ((x) << 17)849#define MCLK_MISC 0x1f850#define EN_MCLK_TRISTATE_IN_SUSPEND (1 << 18)851#define SCLK_MORE_CNTL 0x35852#define REDUCED_SPEED_SCLK_EN (1 << 16)853#define IO_CG_VOLTAGE_DROP (1 << 17)854#define VOLTAGE_DELAY_SEL(x) ((x) << 20)855#define VOLTAGE_DROP_SYNC (1 << 19)856 857/* mmreg */858#define DISP_PWR_MAN 0xd08859#define DISP_D3_GRPH_RST (1 << 18)860#define DISP_D3_SUBPIC_RST (1 << 19)861#define DISP_D3_OV0_RST (1 << 20)862#define DISP_D1D2_GRPH_RST (1 << 21)863#define DISP_D1D2_SUBPIC_RST (1 << 22)864#define DISP_D1D2_OV0_RST (1 << 23)865#define DISP_DVO_ENABLE_RST (1 << 24)866#define TV_ENABLE_RST (1 << 25)867#define AUTO_PWRUP_EN (1 << 26)868 869#endif870