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1/*2 * Copyright 2005 Nicolai Haehnle et al.3 * Copyright 2008 Advanced Micro Devices, Inc.4 * Copyright 2009 Jerome Glisse.5 *6 * Permission is hereby granted, free of charge, to any person obtaining a7 * copy of this software and associated documentation files (the "Software"),8 * to deal in the Software without restriction, including without limitation9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,10 * and/or sell copies of the Software, and to permit persons to whom the11 * Software is furnished to do so, subject to the following conditions:12 *13 * The above copyright notice and this permission notice shall be included in14 * all copies or substantial portions of the Software.15 *16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR22 * OTHER DEALINGS IN THE SOFTWARE.23 *24 * Authors: Nicolai Haehnle25 * Jerome Glisse26 */27#ifndef _R300_REG_H_28#define _R300_REG_H_29 30#define R300_SURF_TILE_MACRO (1<<16)31#define R300_SURF_TILE_MICRO (2<<16)32#define R300_SURF_TILE_BOTH (3<<16)33 34 35#define R300_MC_INIT_MISC_LAT_TIMER 0x18036# define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT 037# define R300_MC_MISC__MC_VF_INIT_LAT_SHIFT 438# define R300_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT 839# define R300_MC_MISC__MC_DISP1R_INIT_LAT_SHIFT 1240# define R300_MC_MISC__MC_FIXED_INIT_LAT_SHIFT 1641# define R300_MC_MISC__MC_E2R_INIT_LAT_SHIFT 2042# define R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT 2443# define R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT 2844 45#define R300_MC_INIT_GFX_LAT_TIMER 0x15446# define R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT 047# define R300_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT 448# define R300_MC_MISC__MC_G3D2R_INIT_LAT_SHIFT 849# define R300_MC_MISC__MC_G3D3R_INIT_LAT_SHIFT 1250# define R300_MC_MISC__MC_TX0R_INIT_LAT_SHIFT 1651# define R300_MC_MISC__MC_TX1R_INIT_LAT_SHIFT 2052# define R300_MC_MISC__MC_GLOBR_INIT_LAT_SHIFT 2453# define R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT 2854 55/*56 * This file contains registers and constants for the R300. They have been57 * found mostly by examining command buffers captured using glxtest, as well58 * as by extrapolating some known registers and constants from the R200.59 * I am fairly certain that they are correct unless stated otherwise60 * in comments.61 */62 63#define R300_SE_VPORT_XSCALE 0x1D9864#define R300_SE_VPORT_XOFFSET 0x1D9C65#define R300_SE_VPORT_YSCALE 0x1DA066#define R300_SE_VPORT_YOFFSET 0x1DA467#define R300_SE_VPORT_ZSCALE 0x1DA868#define R300_SE_VPORT_ZOFFSET 0x1DAC69 70 71/*72 * Vertex Array Processing (VAP) Control73 * Stolen from r200 code from Christoph Brill (It's a guess!)74 */75#define R300_VAP_CNTL 0x208076 77/* This register is written directly and also starts data section78 * in many 3d CP_PACKET3's79 */80#define R300_VAP_VF_CNTL 0x208481# define R300_VAP_VF_CNTL__PRIM_TYPE__SHIFT 082# define R300_VAP_VF_CNTL__PRIM_NONE (0<<0)83# define R300_VAP_VF_CNTL__PRIM_POINTS (1<<0)84# define R300_VAP_VF_CNTL__PRIM_LINES (2<<0)85# define R300_VAP_VF_CNTL__PRIM_LINE_STRIP (3<<0)86# define R300_VAP_VF_CNTL__PRIM_TRIANGLES (4<<0)87# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_FAN (5<<0)88# define R300_VAP_VF_CNTL__PRIM_TRIANGLE_STRIP (6<<0)89# define R300_VAP_VF_CNTL__PRIM_LINE_LOOP (12<<0)90# define R300_VAP_VF_CNTL__PRIM_QUADS (13<<0)91# define R300_VAP_VF_CNTL__PRIM_QUAD_STRIP (14<<0)92# define R300_VAP_VF_CNTL__PRIM_POLYGON (15<<0)93 94# define R300_VAP_VF_CNTL__PRIM_WALK__SHIFT 495 /* State based - direct writes to registers trigger vertex96 generation */97# define R300_VAP_VF_CNTL__PRIM_WALK_STATE_BASED (0<<4)98# define R300_VAP_VF_CNTL__PRIM_WALK_INDICES (1<<4)99# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_LIST (2<<4)100# define R300_VAP_VF_CNTL__PRIM_WALK_VERTEX_EMBEDDED (3<<4)101 102 /* I don't think I saw these three used.. */103# define R300_VAP_VF_CNTL__COLOR_ORDER__SHIFT 6104# define R300_VAP_VF_CNTL__TCL_OUTPUT_CTL_ENA__SHIFT 9105# define R300_VAP_VF_CNTL__PROG_STREAM_ENA__SHIFT 10106 107 /* index size - when not set the indices are assumed to be 16 bit */108# define R300_VAP_VF_CNTL__INDEX_SIZE_32bit (1<<11)109 /* number of vertices */110# define R300_VAP_VF_CNTL__NUM_VERTICES__SHIFT 16111 112/* BEGIN: Wild guesses */113#define R300_VAP_OUTPUT_VTX_FMT_0 0x2090114# define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0)115# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT (1<<1)116# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) /* GUESS */117# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) /* GUESS */118# define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) /* GUESS */119# define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) /* GUESS */120 121#define R300_VAP_OUTPUT_VTX_FMT_1 0x2094122 /* each of the following is 3 bits wide, specifies number123 of components */124# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0125# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3126# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6127# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9128# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12129# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15130# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18131# define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21132/* END: Wild guesses */133 134#define R300_SE_VTE_CNTL 0x20b0135# define R300_VPORT_X_SCALE_ENA 0x00000001136# define R300_VPORT_X_OFFSET_ENA 0x00000002137# define R300_VPORT_Y_SCALE_ENA 0x00000004138# define R300_VPORT_Y_OFFSET_ENA 0x00000008139# define R300_VPORT_Z_SCALE_ENA 0x00000010140# define R300_VPORT_Z_OFFSET_ENA 0x00000020141# define R300_VTX_XY_FMT 0x00000100142# define R300_VTX_Z_FMT 0x00000200143# define R300_VTX_W0_FMT 0x00000400144# define R300_VTX_W0_NORMALIZE 0x00000800145# define R300_VTX_ST_DENORMALIZED 0x00001000146 147/* BEGIN: Vertex data assembly - lots of uncertainties */148 149/* gap */150 151#define R300_VAP_CNTL_STATUS 0x2140152# define R300_VC_NO_SWAP (0 << 0)153# define R300_VC_16BIT_SWAP (1 << 0)154# define R300_VC_32BIT_SWAP (2 << 0)155# define R300_VAP_TCL_BYPASS (1 << 8)156 157/* gap */158 159/* Where do we get our vertex data?160 *161 * Vertex data either comes either from immediate mode registers or from162 * vertex arrays.163 * There appears to be no mixed mode (though we can force the pitch of164 * vertex arrays to 0, effectively reusing the same element over and over165 * again).166 *167 * Immediate mode is controlled by the INPUT_CNTL registers. I am not sure168 * if these registers influence vertex array processing.169 *170 * Vertex arrays are controlled via the 3D_LOAD_VBPNTR packet3.171 *172 * In both cases, vertex attributes are then passed through INPUT_ROUTE.173 *174 * Beginning with INPUT_ROUTE_0_0 is a list of WORDs that route vertex data175 * into the vertex processor's input registers.176 * The first word routes the first input, the second word the second, etc.177 * The corresponding input is routed into the register with the given index.178 * The list is ended by a word with INPUT_ROUTE_END set.179 *180 * Always set COMPONENTS_4 in immediate mode.181 */182 183#define R300_VAP_INPUT_ROUTE_0_0 0x2150184# define R300_INPUT_ROUTE_COMPONENTS_1 (0 << 0)185# define R300_INPUT_ROUTE_COMPONENTS_2 (1 << 0)186# define R300_INPUT_ROUTE_COMPONENTS_3 (2 << 0)187# define R300_INPUT_ROUTE_COMPONENTS_4 (3 << 0)188# define R300_INPUT_ROUTE_COMPONENTS_RGBA (4 << 0) /* GUESS */189# define R300_VAP_INPUT_ROUTE_IDX_SHIFT 8190# define R300_VAP_INPUT_ROUTE_IDX_MASK (31 << 8) /* GUESS */191# define R300_VAP_INPUT_ROUTE_END (1 << 13)192# define R300_INPUT_ROUTE_IMMEDIATE_MODE (0 << 14) /* GUESS */193# define R300_INPUT_ROUTE_FLOAT (1 << 14) /* GUESS */194# define R300_INPUT_ROUTE_UNSIGNED_BYTE (2 << 14) /* GUESS */195# define R300_INPUT_ROUTE_FLOAT_COLOR (3 << 14) /* GUESS */196#define R300_VAP_INPUT_ROUTE_0_1 0x2154197#define R300_VAP_INPUT_ROUTE_0_2 0x2158198#define R300_VAP_INPUT_ROUTE_0_3 0x215C199#define R300_VAP_INPUT_ROUTE_0_4 0x2160200#define R300_VAP_INPUT_ROUTE_0_5 0x2164201#define R300_VAP_INPUT_ROUTE_0_6 0x2168202#define R300_VAP_INPUT_ROUTE_0_7 0x216C203 204/* gap */205 206/* Notes:207 * - always set up to produce at least two attributes:208 * if vertex program uses only position, fglrx will set normal, too209 * - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal.210 */211#define R300_VAP_INPUT_CNTL_0 0x2180212# define R300_INPUT_CNTL_0_COLOR 0x00000001213#define R300_VAP_INPUT_CNTL_1 0x2184214# define R300_INPUT_CNTL_POS 0x00000001215# define R300_INPUT_CNTL_NORMAL 0x00000002216# define R300_INPUT_CNTL_COLOR 0x00000004217# define R300_INPUT_CNTL_TC0 0x00000400218# define R300_INPUT_CNTL_TC1 0x00000800219# define R300_INPUT_CNTL_TC2 0x00001000 /* GUESS */220# define R300_INPUT_CNTL_TC3 0x00002000 /* GUESS */221# define R300_INPUT_CNTL_TC4 0x00004000 /* GUESS */222# define R300_INPUT_CNTL_TC5 0x00008000 /* GUESS */223# define R300_INPUT_CNTL_TC6 0x00010000 /* GUESS */224# define R300_INPUT_CNTL_TC7 0x00020000 /* GUESS */225 226/* gap */227 228/* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0229 * are set to a swizzling bit pattern, other words are 0.230 *231 * In immediate mode, the pattern is always set to xyzw. In vertex array232 * mode, the swizzling pattern is e.g. used to set zw components in texture233 * coordinates with only tweo components.234 */235#define R300_VAP_INPUT_ROUTE_1_0 0x21E0236# define R300_INPUT_ROUTE_SELECT_X 0237# define R300_INPUT_ROUTE_SELECT_Y 1238# define R300_INPUT_ROUTE_SELECT_Z 2239# define R300_INPUT_ROUTE_SELECT_W 3240# define R300_INPUT_ROUTE_SELECT_ZERO 4241# define R300_INPUT_ROUTE_SELECT_ONE 5242# define R300_INPUT_ROUTE_SELECT_MASK 7243# define R300_INPUT_ROUTE_X_SHIFT 0244# define R300_INPUT_ROUTE_Y_SHIFT 3245# define R300_INPUT_ROUTE_Z_SHIFT 6246# define R300_INPUT_ROUTE_W_SHIFT 9247# define R300_INPUT_ROUTE_ENABLE (15 << 12)248#define R300_VAP_INPUT_ROUTE_1_1 0x21E4249#define R300_VAP_INPUT_ROUTE_1_2 0x21E8250#define R300_VAP_INPUT_ROUTE_1_3 0x21EC251#define R300_VAP_INPUT_ROUTE_1_4 0x21F0252#define R300_VAP_INPUT_ROUTE_1_5 0x21F4253#define R300_VAP_INPUT_ROUTE_1_6 0x21F8254#define R300_VAP_INPUT_ROUTE_1_7 0x21FC255 256/* END: Vertex data assembly */257 258/* gap */259 260/* BEGIN: Upload vertex program and data */261 262/*263 * The programmable vertex shader unit has a memory bank of unknown size264 * that can be written to in 16 byte units by writing the address into265 * UPLOAD_ADDRESS, followed by data in UPLOAD_DATA (multiples of 4 DWORDs).266 *267 * Pointers into the memory bank are always in multiples of 16 bytes.268 *269 * The memory bank is divided into areas with fixed meaning.270 *271 * Starting at address UPLOAD_PROGRAM: Vertex program instructions.272 * Native limits reported by drivers from ATI suggest size 256 (i.e. 4KB),273 * whereas the difference between known addresses suggests size 512.274 *275 * Starting at address UPLOAD_PARAMETERS: Vertex program parameters.276 * Native reported limits and the VPI layout suggest size 256, whereas277 * difference between known addresses suggests size 512.278 *279 * At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the280 * floating point pointsize. The exact purpose of this state is uncertain,281 * as there is also the R300_RE_POINTSIZE register.282 *283 * Multiple vertex programs and parameter sets can be loaded at once,284 * which could explain the size discrepancy.285 */286#define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200287# define R300_PVS_UPLOAD_PROGRAM 0x00000000288# define R300_PVS_UPLOAD_PARAMETERS 0x00000200289# define R300_PVS_UPLOAD_POINTSIZE 0x00000406290 291/* gap */292 293#define R300_VAP_PVS_UPLOAD_DATA 0x2208294 295/* END: Upload vertex program and data */296 297/* gap */298 299/* I do not know the purpose of this register. However, I do know that300 * it is set to 221C_CLEAR for clear operations and to 221C_NORMAL301 * for normal rendering.302 */303#define R300_VAP_UNKNOWN_221C 0x221C304# define R300_221C_NORMAL 0x00000000305# define R300_221C_CLEAR 0x0001C000306 307/* These seem to be per-pixel and per-vertex X and Y clipping planes. The first308 * plane is per-pixel and the second plane is per-vertex.309 *310 * This was determined by experimentation alone but I believe it is correct.311 *312 * These registers are called X_QUAD0_1_FL to X_QUAD0_4_FL by glxtest.313 */314#define R300_VAP_CLIP_X_0 0x2220315#define R300_VAP_CLIP_X_1 0x2224316#define R300_VAP_CLIP_Y_0 0x2228317#define R300_VAP_CLIP_Y_1 0x2230318 319/* gap */320 321/* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between322 * rendering commands and overwriting vertex program parameters.323 * Therefore, I suspect writing zero to 0x2284 synchronizes the engine and324 * avoids bugs caused by still running shaders reading bad data from memory.325 */326#define R300_VAP_PVS_STATE_FLUSH_REG 0x2284327 328/* Absolutely no clue what this register is about. */329#define R300_VAP_UNKNOWN_2288 0x2288330# define R300_2288_R300 0x00750000 /* -- nh */331# define R300_2288_RV350 0x0000FFFF /* -- Vladimir */332 333/* gap */334 335/* Addresses are relative to the vertex program instruction area of the336 * memory bank. PROGRAM_END points to the last instruction of the active337 * program338 *339 * The meaning of the two UNKNOWN fields is obviously not known. However,340 * experiments so far have shown that both *must* point to an instruction341 * inside the vertex program, otherwise the GPU locks up.342 *343 * fglrx usually sets CNTL_3_UNKNOWN to the end of the program and344 * R300_PVS_CNTL_1_POS_END_SHIFT points to instruction where last write to345 * position takes place.346 *347 * Most likely this is used to ignore rest of the program in cases348 * where group of verts arent visible. For some reason this "section"349 * is sometimes accepted other instruction that have no relationship with350 * position calculations.351 */352#define R300_VAP_PVS_CNTL_1 0x22D0353# define R300_PVS_CNTL_1_PROGRAM_START_SHIFT 0354# define R300_PVS_CNTL_1_POS_END_SHIFT 10355# define R300_PVS_CNTL_1_PROGRAM_END_SHIFT 20356/* Addresses are relative the vertex program parameters area. */357#define R300_VAP_PVS_CNTL_2 0x22D4358# define R300_PVS_CNTL_2_PARAM_OFFSET_SHIFT 0359# define R300_PVS_CNTL_2_PARAM_COUNT_SHIFT 16360#define R300_VAP_PVS_CNTL_3 0x22D8361# define R300_PVS_CNTL_3_PROGRAM_UNKNOWN_SHIFT 10362# define R300_PVS_CNTL_3_PROGRAM_UNKNOWN2_SHIFT 0363 364/* The entire range from 0x2300 to 0x2AC inclusive seems to be used for365 * immediate vertices366 */367#define R300_VAP_VTX_COLOR_R 0x2464368#define R300_VAP_VTX_COLOR_G 0x2468369#define R300_VAP_VTX_COLOR_B 0x246C370#define R300_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */371#define R300_VAP_VTX_POS_0_Y_1 0x2494372#define R300_VAP_VTX_COLOR_PKD 0x249C /* RGBA */373#define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */374#define R300_VAP_VTX_POS_0_Y_2 0x24A4375#define R300_VAP_VTX_POS_0_Z_2 0x24A8376/* write 0 to indicate end of packet? */377#define R300_VAP_VTX_END_OF_PKT 0x24AC378 379/* gap */380 381/* These are values from r300_reg/r300_reg.h - they are known to be correct382 * and are here so we can use one register file instead of several383 * - Vladimir384 */385#define R300_GB_VAP_RASTER_VTX_FMT_0 0x4000386# define R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT (1<<0)387# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT (1<<1)388# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_1_PRESENT (1<<2)389# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_2_PRESENT (1<<3)390# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_3_PRESENT (1<<4)391# define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_SPACE (0xf<<5)392# define R300_GB_VAP_RASTER_VTX_FMT_0__PT_SIZE_PRESENT (0x1<<16)393 394#define R300_GB_VAP_RASTER_VTX_FMT_1 0x4004395 /* each of the following is 3 bits wide, specifies number396 of components */397# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0398# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3399# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6400# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9401# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12402# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15403# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18404# define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21405 406/* UNK30 seems to enables point to quad transformation on textures407 * (or something closely related to that).408 * This bit is rather fatal at the time being due to lackings at pixel409 * shader side410 */411#define R300_GB_ENABLE 0x4008412# define R300_GB_POINT_STUFF_ENABLE (1<<0)413# define R300_GB_LINE_STUFF_ENABLE (1<<1)414# define R300_GB_TRIANGLE_STUFF_ENABLE (1<<2)415# define R300_GB_STENCIL_AUTO_ENABLE (1<<4)416# define R300_GB_UNK31 (1<<31)417 /* each of the following is 2 bits wide */418#define R300_GB_TEX_REPLICATE 0419#define R300_GB_TEX_ST 1420#define R300_GB_TEX_STR 2421# define R300_GB_TEX0_SOURCE_SHIFT 16422# define R300_GB_TEX1_SOURCE_SHIFT 18423# define R300_GB_TEX2_SOURCE_SHIFT 20424# define R300_GB_TEX3_SOURCE_SHIFT 22425# define R300_GB_TEX4_SOURCE_SHIFT 24426# define R300_GB_TEX5_SOURCE_SHIFT 26427# define R300_GB_TEX6_SOURCE_SHIFT 28428# define R300_GB_TEX7_SOURCE_SHIFT 30429 430/* MSPOS - positions for multisample antialiasing (?) */431#define R300_GB_MSPOS0 0x4010432 /* shifts - each of the fields is 4 bits */433# define R300_GB_MSPOS0__MS_X0_SHIFT 0434# define R300_GB_MSPOS0__MS_Y0_SHIFT 4435# define R300_GB_MSPOS0__MS_X1_SHIFT 8436# define R300_GB_MSPOS0__MS_Y1_SHIFT 12437# define R300_GB_MSPOS0__MS_X2_SHIFT 16438# define R300_GB_MSPOS0__MS_Y2_SHIFT 20439# define R300_GB_MSPOS0__MSBD0_Y 24440# define R300_GB_MSPOS0__MSBD0_X 28441 442#define R300_GB_MSPOS1 0x4014443# define R300_GB_MSPOS1__MS_X3_SHIFT 0444# define R300_GB_MSPOS1__MS_Y3_SHIFT 4445# define R300_GB_MSPOS1__MS_X4_SHIFT 8446# define R300_GB_MSPOS1__MS_Y4_SHIFT 12447# define R300_GB_MSPOS1__MS_X5_SHIFT 16448# define R300_GB_MSPOS1__MS_Y5_SHIFT 20449# define R300_GB_MSPOS1__MSBD1 24450 451 452#define R300_GB_TILE_CONFIG 0x4018453# define R300_GB_TILE_ENABLE (1<<0)454# define R300_GB_TILE_PIPE_COUNT_RV300 0455# define R300_GB_TILE_PIPE_COUNT_R300 (3<<1)456# define R300_GB_TILE_PIPE_COUNT_R420 (7<<1)457# define R300_GB_TILE_PIPE_COUNT_RV410 (3<<1)458# define R300_GB_TILE_SIZE_8 0459# define R300_GB_TILE_SIZE_16 (1<<4)460# define R300_GB_TILE_SIZE_32 (2<<4)461# define R300_GB_SUPER_SIZE_1 (0<<6)462# define R300_GB_SUPER_SIZE_2 (1<<6)463# define R300_GB_SUPER_SIZE_4 (2<<6)464# define R300_GB_SUPER_SIZE_8 (3<<6)465# define R300_GB_SUPER_SIZE_16 (4<<6)466# define R300_GB_SUPER_SIZE_32 (5<<6)467# define R300_GB_SUPER_SIZE_64 (6<<6)468# define R300_GB_SUPER_SIZE_128 (7<<6)469# define R300_GB_SUPER_X_SHIFT 9 /* 3 bits wide */470# define R300_GB_SUPER_Y_SHIFT 12 /* 3 bits wide */471# define R300_GB_SUPER_TILE_A 0472# define R300_GB_SUPER_TILE_B (1<<15)473# define R300_GB_SUBPIXEL_1_12 0474# define R300_GB_SUBPIXEL_1_16 (1<<16)475 476#define R300_GB_FIFO_SIZE 0x4024477 /* each of the following is 2 bits wide */478#define R300_GB_FIFO_SIZE_32 0479#define R300_GB_FIFO_SIZE_64 1480#define R300_GB_FIFO_SIZE_128 2481#define R300_GB_FIFO_SIZE_256 3482# define R300_SC_IFIFO_SIZE_SHIFT 0483# define R300_SC_TZFIFO_SIZE_SHIFT 2484# define R300_SC_BFIFO_SIZE_SHIFT 4485 486# define R300_US_OFIFO_SIZE_SHIFT 12487# define R300_US_WFIFO_SIZE_SHIFT 14488 /* the following use the same constants as above, but meaning is489 is times 2 (i.e. instead of 32 words it means 64 */490# define R300_RS_TFIFO_SIZE_SHIFT 6491# define R300_RS_CFIFO_SIZE_SHIFT 8492# define R300_US_RAM_SIZE_SHIFT 10493 /* watermarks, 3 bits wide */494# define R300_RS_HIGHWATER_COL_SHIFT 16495# define R300_RS_HIGHWATER_TEX_SHIFT 19496# define R300_OFIFO_HIGHWATER_SHIFT 22 /* two bits only */497# define R300_CUBE_FIFO_HIGHWATER_COL_SHIFT 24498 499#define R300_GB_SELECT 0x401C500# define R300_GB_FOG_SELECT_C0A 0501# define R300_GB_FOG_SELECT_C1A 1502# define R300_GB_FOG_SELECT_C2A 2503# define R300_GB_FOG_SELECT_C3A 3504# define R300_GB_FOG_SELECT_1_1_W 4505# define R300_GB_FOG_SELECT_Z 5506# define R300_GB_DEPTH_SELECT_Z 0507# define R300_GB_DEPTH_SELECT_1_1_W (1<<3)508# define R300_GB_W_SELECT_1_W 0509# define R300_GB_W_SELECT_1 (1<<4)510 511#define R300_GB_AA_CONFIG 0x4020512# define R300_AA_DISABLE 0x00513# define R300_AA_ENABLE 0x01514# define R300_AA_SUBSAMPLES_2 0515# define R300_AA_SUBSAMPLES_3 (1<<1)516# define R300_AA_SUBSAMPLES_4 (2<<1)517# define R300_AA_SUBSAMPLES_6 (3<<1)518 519/* gap */520 521/* Zero to flush caches. */522#define R300_TX_INVALTAGS 0x4100523#define R300_TX_FLUSH 0x0524 525/* The upper enable bits are guessed, based on fglrx reported limits. */526#define R300_TX_ENABLE 0x4104527# define R300_TX_ENABLE_0 (1 << 0)528# define R300_TX_ENABLE_1 (1 << 1)529# define R300_TX_ENABLE_2 (1 << 2)530# define R300_TX_ENABLE_3 (1 << 3)531# define R300_TX_ENABLE_4 (1 << 4)532# define R300_TX_ENABLE_5 (1 << 5)533# define R300_TX_ENABLE_6 (1 << 6)534# define R300_TX_ENABLE_7 (1 << 7)535# define R300_TX_ENABLE_8 (1 << 8)536# define R300_TX_ENABLE_9 (1 << 9)537# define R300_TX_ENABLE_10 (1 << 10)538# define R300_TX_ENABLE_11 (1 << 11)539# define R300_TX_ENABLE_12 (1 << 12)540# define R300_TX_ENABLE_13 (1 << 13)541# define R300_TX_ENABLE_14 (1 << 14)542# define R300_TX_ENABLE_15 (1 << 15)543 544/* The pointsize is given in multiples of 6. The pointsize can be545 * enormous: Clear() renders a single point that fills the entire546 * framebuffer.547 */548#define R300_RE_POINTSIZE 0x421C549# define R300_POINTSIZE_Y_SHIFT 0550# define R300_POINTSIZE_Y_MASK (0xFFFF << 0) /* GUESS */551# define R300_POINTSIZE_X_SHIFT 16552# define R300_POINTSIZE_X_MASK (0xFFFF << 16) /* GUESS */553# define R300_POINTSIZE_MAX (R300_POINTSIZE_Y_MASK / 6)554 555/* The line width is given in multiples of 6.556 * In default mode lines are classified as vertical lines.557 * HO: horizontal558 * VE: vertical or horizontal559 * HO & VE: no classification560 */561#define R300_RE_LINE_CNT 0x4234562# define R300_LINESIZE_SHIFT 0563# define R300_LINESIZE_MASK (0xFFFF << 0) /* GUESS */564# define R300_LINESIZE_MAX (R300_LINESIZE_MASK / 6)565# define R300_LINE_CNT_HO (1 << 16)566# define R300_LINE_CNT_VE (1 << 17)567 568/* Some sort of scale or clamp value for texcoordless textures. */569#define R300_RE_UNK4238 0x4238570 571/* Something shade related */572#define R300_RE_SHADE 0x4274573 574#define R300_RE_SHADE_MODEL 0x4278575# define R300_RE_SHADE_MODEL_SMOOTH 0x3aaaa576# define R300_RE_SHADE_MODEL_FLAT 0x39595577 578/* Dangerous */579#define R300_RE_POLYGON_MODE 0x4288580# define R300_PM_ENABLED (1 << 0)581# define R300_PM_FRONT_POINT (0 << 0)582# define R300_PM_BACK_POINT (0 << 0)583# define R300_PM_FRONT_LINE (1 << 4)584# define R300_PM_FRONT_FILL (1 << 5)585# define R300_PM_BACK_LINE (1 << 7)586# define R300_PM_BACK_FILL (1 << 8)587 588/* Fog parameters */589#define R300_RE_FOG_SCALE 0x4294590#define R300_RE_FOG_START 0x4298591 592/* Not sure why there are duplicate of factor and constant values.593 * My best guess so far is that there are separate zbiases for test and write.594 * Ordering might be wrong.595 * Some of the tests indicate that fgl has a fallback implementation of zbias596 * via pixel shaders.597 */598#define R300_RE_ZBIAS_CNTL 0x42A0 /* GUESS */599#define R300_RE_ZBIAS_T_FACTOR 0x42A4600#define R300_RE_ZBIAS_T_CONSTANT 0x42A8601#define R300_RE_ZBIAS_W_FACTOR 0x42AC602#define R300_RE_ZBIAS_W_CONSTANT 0x42B0603 604/* This register needs to be set to (1<<1) for RV350 to correctly605 * perform depth test (see --vb-triangles in r300_demo)606 * Don't know about other chips. - Vladimir607 * This is set to 3 when GL_POLYGON_OFFSET_FILL is on.608 * My guess is that there are two bits for each zbias primitive609 * (FILL, LINE, POINT).610 * One to enable depth test and one for depth write.611 * Yet this doesn't explain why depth writes work ...612 */613#define R300_RE_OCCLUSION_CNTL 0x42B4614# define R300_OCCLUSION_ON (1<<1)615 616#define R300_RE_CULL_CNTL 0x42B8617# define R300_CULL_FRONT (1 << 0)618# define R300_CULL_BACK (1 << 1)619# define R300_FRONT_FACE_CCW (0 << 2)620# define R300_FRONT_FACE_CW (1 << 2)621 622 623/* BEGIN: Rasterization / Interpolators - many guesses */624 625/* 0_UNKNOWN_18 has always been set except for clear operations.626 * TC_CNT is the number of incoming texture coordinate sets (i.e. it depends627 * on the vertex program, *not* the fragment program)628 */629#define R300_RS_CNTL_0 0x4300630# define R300_RS_CNTL_TC_CNT_SHIFT 2631# define R300_RS_CNTL_TC_CNT_MASK (7 << 2)632 /* number of color interpolators used */633# define R300_RS_CNTL_CI_CNT_SHIFT 7634# define R300_RS_CNTL_0_UNKNOWN_18 (1 << 18)635 /* Guess: RS_CNTL_1 holds the index of the highest used RS_ROUTE_n636 register. */637#define R300_RS_CNTL_1 0x4304638 639/* gap */640 641/* Only used for texture coordinates.642 * Use the source field to route texture coordinate input from the643 * vertex program to the desired interpolator. Note that the source644 * field is relative to the outputs the vertex program *actually*645 * writes. If a vertex program only writes texcoord[1], this will646 * be source index 0.647 * Set INTERP_USED on all interpolators that produce data used by648 * the fragment program. INTERP_USED looks like a swizzling mask,649 * but I haven't seen it used that way.650 *651 * Note: The _UNKNOWN constants are always set in their respective652 * register. I don't know if this is necessary.653 */654#define R300_RS_INTERP_0 0x4310655#define R300_RS_INTERP_1 0x4314656# define R300_RS_INTERP_1_UNKNOWN 0x40657#define R300_RS_INTERP_2 0x4318658# define R300_RS_INTERP_2_UNKNOWN 0x80659#define R300_RS_INTERP_3 0x431C660# define R300_RS_INTERP_3_UNKNOWN 0xC0661#define R300_RS_INTERP_4 0x4320662#define R300_RS_INTERP_5 0x4324663#define R300_RS_INTERP_6 0x4328664#define R300_RS_INTERP_7 0x432C665# define R300_RS_INTERP_SRC_SHIFT 2666# define R300_RS_INTERP_SRC_MASK (7 << 2)667# define R300_RS_INTERP_USED 0x00D10000668 669/* These DWORDs control how vertex data is routed into fragment program670 * registers, after interpolators.671 */672#define R300_RS_ROUTE_0 0x4330673#define R300_RS_ROUTE_1 0x4334674#define R300_RS_ROUTE_2 0x4338675#define R300_RS_ROUTE_3 0x433C /* GUESS */676#define R300_RS_ROUTE_4 0x4340 /* GUESS */677#define R300_RS_ROUTE_5 0x4344 /* GUESS */678#define R300_RS_ROUTE_6 0x4348 /* GUESS */679#define R300_RS_ROUTE_7 0x434C /* GUESS */680# define R300_RS_ROUTE_SOURCE_INTERP_0 0681# define R300_RS_ROUTE_SOURCE_INTERP_1 1682# define R300_RS_ROUTE_SOURCE_INTERP_2 2683# define R300_RS_ROUTE_SOURCE_INTERP_3 3684# define R300_RS_ROUTE_SOURCE_INTERP_4 4685# define R300_RS_ROUTE_SOURCE_INTERP_5 5 /* GUESS */686# define R300_RS_ROUTE_SOURCE_INTERP_6 6 /* GUESS */687# define R300_RS_ROUTE_SOURCE_INTERP_7 7 /* GUESS */688# define R300_RS_ROUTE_ENABLE (1 << 3) /* GUESS */689# define R300_RS_ROUTE_DEST_SHIFT 6690# define R300_RS_ROUTE_DEST_MASK (31 << 6) /* GUESS */691 692/* Special handling for color: When the fragment program uses color,693 * the ROUTE_0_COLOR bit is set and ROUTE_0_COLOR_DEST contains the694 * color register index.695 *696 * Apperently you may set the R300_RS_ROUTE_0_COLOR bit, but not provide any697 * R300_RS_ROUTE_0_COLOR_DEST value; this setup is used for clearing the state.698 * See r300_ioctl.c:r300EmitClearState. I'm not sure if this setup is strictly699 * correct or not. - Oliver.700 */701# define R300_RS_ROUTE_0_COLOR (1 << 14)702# define R300_RS_ROUTE_0_COLOR_DEST_SHIFT 17703# define R300_RS_ROUTE_0_COLOR_DEST_MASK (31 << 17) /* GUESS */704/* As above, but for secondary color */705# define R300_RS_ROUTE_1_COLOR1 (1 << 14)706# define R300_RS_ROUTE_1_COLOR1_DEST_SHIFT 17707# define R300_RS_ROUTE_1_COLOR1_DEST_MASK (31 << 17)708# define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11)709/* END: Rasterization / Interpolators - many guesses */710 711/* Hierarchical Z Enable */712#define R300_SC_HYPERZ 0x43a4713# define R300_SC_HYPERZ_DISABLE (0 << 0)714# define R300_SC_HYPERZ_ENABLE (1 << 0)715# define R300_SC_HYPERZ_MIN (0 << 1)716# define R300_SC_HYPERZ_MAX (1 << 1)717# define R300_SC_HYPERZ_ADJ_256 (0 << 2)718# define R300_SC_HYPERZ_ADJ_128 (1 << 2)719# define R300_SC_HYPERZ_ADJ_64 (2 << 2)720# define R300_SC_HYPERZ_ADJ_32 (3 << 2)721# define R300_SC_HYPERZ_ADJ_16 (4 << 2)722# define R300_SC_HYPERZ_ADJ_8 (5 << 2)723# define R300_SC_HYPERZ_ADJ_4 (6 << 2)724# define R300_SC_HYPERZ_ADJ_2 (7 << 2)725# define R300_SC_HYPERZ_HZ_Z0MIN_NO (0 << 5)726# define R300_SC_HYPERZ_HZ_Z0MIN (1 << 5)727# define R300_SC_HYPERZ_HZ_Z0MAX_NO (0 << 6)728# define R300_SC_HYPERZ_HZ_Z0MAX (1 << 6)729 730#define R300_SC_EDGERULE 0x43a8731 732/* BEGIN: Scissors and cliprects */733 734/* There are four clipping rectangles. Their corner coordinates are inclusive.735 * Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending736 * on whether the pixel is inside cliprects 0-3, respectively. For example,737 * if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned738 * the number 3 (binary 0011).739 * Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set,740 * the pixel is rasterized.741 *742 * In addition to this, there is a scissors rectangle. Only pixels inside the743 * scissors rectangle are drawn. (coordinates are inclusive)744 *745 * For some reason, the top-left corner of the framebuffer is at (1440, 1440)746 * for the purpose of clipping and scissors.747 */748#define R300_RE_CLIPRECT_TL_0 0x43B0749#define R300_RE_CLIPRECT_BR_0 0x43B4750#define R300_RE_CLIPRECT_TL_1 0x43B8751#define R300_RE_CLIPRECT_BR_1 0x43BC752#define R300_RE_CLIPRECT_TL_2 0x43C0753#define R300_RE_CLIPRECT_BR_2 0x43C4754#define R300_RE_CLIPRECT_TL_3 0x43C8755#define R300_RE_CLIPRECT_BR_3 0x43CC756# define R300_CLIPRECT_OFFSET 1440757# define R300_CLIPRECT_MASK 0x1FFF758# define R300_CLIPRECT_X_SHIFT 0759# define R300_CLIPRECT_X_MASK (0x1FFF << 0)760# define R300_CLIPRECT_Y_SHIFT 13761# define R300_CLIPRECT_Y_MASK (0x1FFF << 13)762#define R300_RE_CLIPRECT_CNTL 0x43D0763# define R300_CLIP_OUT (1 << 0)764# define R300_CLIP_0 (1 << 1)765# define R300_CLIP_1 (1 << 2)766# define R300_CLIP_10 (1 << 3)767# define R300_CLIP_2 (1 << 4)768# define R300_CLIP_20 (1 << 5)769# define R300_CLIP_21 (1 << 6)770# define R300_CLIP_210 (1 << 7)771# define R300_CLIP_3 (1 << 8)772# define R300_CLIP_30 (1 << 9)773# define R300_CLIP_31 (1 << 10)774# define R300_CLIP_310 (1 << 11)775# define R300_CLIP_32 (1 << 12)776# define R300_CLIP_320 (1 << 13)777# define R300_CLIP_321 (1 << 14)778# define R300_CLIP_3210 (1 << 15)779 780/* gap */781 782#define R300_RE_SCISSORS_TL 0x43E0783#define R300_RE_SCISSORS_BR 0x43E4784# define R300_SCISSORS_OFFSET 1440785# define R300_SCISSORS_X_SHIFT 0786# define R300_SCISSORS_X_MASK (0x1FFF << 0)787# define R300_SCISSORS_Y_SHIFT 13788# define R300_SCISSORS_Y_MASK (0x1FFF << 13)789/* END: Scissors and cliprects */790 791/* BEGIN: Texture specification */792 793/*794 * The texture specification dwords are grouped by meaning and not by texture795 * unit. This means that e.g. the offset for texture image unit N is found in796 * register TX_OFFSET_0 + (4*N)797 */798#define R300_TX_FILTER_0 0x4400799# define R300_TX_REPEAT 0800# define R300_TX_MIRRORED 1801# define R300_TX_CLAMP 4802# define R300_TX_CLAMP_TO_EDGE 2803# define R300_TX_CLAMP_TO_BORDER 6804# define R300_TX_WRAP_S_SHIFT 0805# define R300_TX_WRAP_S_MASK (7 << 0)806# define R300_TX_WRAP_T_SHIFT 3807# define R300_TX_WRAP_T_MASK (7 << 3)808# define R300_TX_WRAP_Q_SHIFT 6809# define R300_TX_WRAP_Q_MASK (7 << 6)810# define R300_TX_MAG_FILTER_NEAREST (1 << 9)811# define R300_TX_MAG_FILTER_LINEAR (2 << 9)812# define R300_TX_MAG_FILTER_MASK (3 << 9)813# define R300_TX_MIN_FILTER_NEAREST (1 << 11)814# define R300_TX_MIN_FILTER_LINEAR (2 << 11)815# define R300_TX_MIN_FILTER_NEAREST_MIP_NEAREST (5 << 11)816# define R300_TX_MIN_FILTER_NEAREST_MIP_LINEAR (9 << 11)817# define R300_TX_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 11)818# define R300_TX_MIN_FILTER_LINEAR_MIP_LINEAR (10 << 11)819 820/* NOTE: NEAREST doesn't seem to exist.821 * Im not seting MAG_FILTER_MASK and (3 << 11) on for all822 * anisotropy modes because that would void selected mag filter823 */824# define R300_TX_MIN_FILTER_ANISO_NEAREST (0 << 13)825# define R300_TX_MIN_FILTER_ANISO_LINEAR (0 << 13)826# define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (1 << 13)827# define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (2 << 13)828# define R300_TX_MIN_FILTER_MASK ((15 << 11) | (3 << 13))829# define R300_TX_MAX_ANISO_1_TO_1 (0 << 21)830# define R300_TX_MAX_ANISO_2_TO_1 (2 << 21)831# define R300_TX_MAX_ANISO_4_TO_1 (4 << 21)832# define R300_TX_MAX_ANISO_8_TO_1 (6 << 21)833# define R300_TX_MAX_ANISO_16_TO_1 (8 << 21)834# define R300_TX_MAX_ANISO_MASK (14 << 21)835 836#define R300_TX_FILTER1_0 0x4440837# define R300_CHROMA_KEY_MODE_DISABLE 0838# define R300_CHROMA_KEY_FORCE 1839# define R300_CHROMA_KEY_BLEND 2840# define R300_MC_ROUND_NORMAL (0<<2)841# define R300_MC_ROUND_MPEG4 (1<<2)842# define R300_LOD_BIAS_MASK 0x1fff843# define R300_EDGE_ANISO_EDGE_DIAG (0<<13)844# define R300_EDGE_ANISO_EDGE_ONLY (1<<13)845# define R300_MC_COORD_TRUNCATE_DISABLE (0<<14)846# define R300_MC_COORD_TRUNCATE_MPEG (1<<14)847# define R300_TX_TRI_PERF_0_8 (0<<15)848# define R300_TX_TRI_PERF_1_8 (1<<15)849# define R300_TX_TRI_PERF_1_4 (2<<15)850# define R300_TX_TRI_PERF_3_8 (3<<15)851# define R300_ANISO_THRESHOLD_MASK (7<<17)852 853#define R300_TX_SIZE_0 0x4480854# define R300_TX_WIDTHMASK_SHIFT 0855# define R300_TX_WIDTHMASK_MASK (2047 << 0)856# define R300_TX_HEIGHTMASK_SHIFT 11857# define R300_TX_HEIGHTMASK_MASK (2047 << 11)858# define R300_TX_UNK23 (1 << 23)859# define R300_TX_MAX_MIP_LEVEL_SHIFT 26860# define R300_TX_MAX_MIP_LEVEL_MASK (0xf << 26)861# define R300_TX_SIZE_PROJECTED (1<<30)862# define R300_TX_SIZE_TXPITCH_EN (1<<31)863#define R300_TX_FORMAT_0 0x44C0864 /* The interpretation of the format word by Wladimir van der Laan */865 /* The X, Y, Z and W refer to the layout of the components.866 They are given meanings as R, G, B and Alpha by the swizzle867 specification */868# define R300_TX_FORMAT_X8 0x0869# define R300_TX_FORMAT_X16 0x1870# define R300_TX_FORMAT_Y4X4 0x2871# define R300_TX_FORMAT_Y8X8 0x3872# define R300_TX_FORMAT_Y16X16 0x4873# define R300_TX_FORMAT_Z3Y3X2 0x5874# define R300_TX_FORMAT_Z5Y6X5 0x6875# define R300_TX_FORMAT_Z6Y5X5 0x7876# define R300_TX_FORMAT_Z11Y11X10 0x8877# define R300_TX_FORMAT_Z10Y11X11 0x9878# define R300_TX_FORMAT_W4Z4Y4X4 0xA879# define R300_TX_FORMAT_W1Z5Y5X5 0xB880# define R300_TX_FORMAT_W8Z8Y8X8 0xC881# define R300_TX_FORMAT_W2Z10Y10X10 0xD882# define R300_TX_FORMAT_W16Z16Y16X16 0xE883# define R300_TX_FORMAT_DXT1 0xF884# define R300_TX_FORMAT_DXT3 0x10885# define R300_TX_FORMAT_DXT5 0x11886# define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */887# define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */888# define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */889# define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */890 /* 0x16 - some 16 bit green format.. ?? */891# define R300_TX_FORMAT_UNK25 (1 << 25) /* no swizzle */892# define R300_TX_FORMAT_CUBIC_MAP (1 << 26)893 894 /* gap */895 /* Floating point formats */896 /* Note - hardware supports both 16 and 32 bit floating point */897# define R300_TX_FORMAT_FL_I16 0x18898# define R300_TX_FORMAT_FL_I16A16 0x19899# define R300_TX_FORMAT_FL_R16G16B16A16 0x1A900# define R300_TX_FORMAT_FL_I32 0x1B901# define R300_TX_FORMAT_FL_I32A32 0x1C902# define R300_TX_FORMAT_FL_R32G32B32A32 0x1D903# define R300_TX_FORMAT_ATI2N 0x1F904 /* alpha modes, convenience mostly */905 /* if you have alpha, pick constant appropriate to the906 number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */907# define R300_TX_FORMAT_ALPHA_1CH 0x000908# define R300_TX_FORMAT_ALPHA_2CH 0x200909# define R300_TX_FORMAT_ALPHA_4CH 0x600910# define R300_TX_FORMAT_ALPHA_NONE 0xA00911 /* Swizzling */912 /* constants */913# define R300_TX_FORMAT_X 0914# define R300_TX_FORMAT_Y 1915# define R300_TX_FORMAT_Z 2916# define R300_TX_FORMAT_W 3917# define R300_TX_FORMAT_ZERO 4918# define R300_TX_FORMAT_ONE 5919 /* 2.0*Z, everything above 1.0 is set to 0.0 */920# define R300_TX_FORMAT_CUT_Z 6921 /* 2.0*W, everything above 1.0 is set to 0.0 */922# define R300_TX_FORMAT_CUT_W 7923 924# define R300_TX_FORMAT_B_SHIFT 18925# define R300_TX_FORMAT_G_SHIFT 15926# define R300_TX_FORMAT_R_SHIFT 12927# define R300_TX_FORMAT_A_SHIFT 9928 /* Convenience macro to take care of layout and swizzling */929# define R300_EASY_TX_FORMAT(B, G, R, A, FMT) ( \930 ((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT) \931 | ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT) \932 | ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT) \933 | ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT) \934 | (R300_TX_FORMAT_##FMT) \935 )936 /* These can be ORed with result of R300_EASY_TX_FORMAT()937 We don't really know what they do. Take values from a938 constant color ? */939# define R300_TX_FORMAT_CONST_X (1<<5)940# define R300_TX_FORMAT_CONST_Y (2<<5)941# define R300_TX_FORMAT_CONST_Z (4<<5)942# define R300_TX_FORMAT_CONST_W (8<<5)943 944# define R300_TX_FORMAT_YUV_MODE 0x00800000945 946#define R300_TX_PITCH_0 0x4500 /* obvious missing in gap */947#define R300_TX_OFFSET_0 0x4540948 /* BEGIN: Guess from R200 */949# define R300_TXO_ENDIAN_NO_SWAP (0 << 0)950# define R300_TXO_ENDIAN_BYTE_SWAP (1 << 0)951# define R300_TXO_ENDIAN_WORD_SWAP (2 << 0)952# define R300_TXO_ENDIAN_HALFDW_SWAP (3 << 0)953# define R300_TXO_MACRO_TILE (1 << 2)954# define R300_TXO_MICRO_TILE (1 << 3)955# define R300_TXO_MICRO_TILE_SQUARE (2 << 3)956# define R300_TXO_OFFSET_MASK 0xffffffe0957# define R300_TXO_OFFSET_SHIFT 5958 /* END: Guess from R200 */959 960/* 32 bit chroma key */961#define R300_TX_CHROMA_KEY_0 0x4580962/* ff00ff00 == { 0, 1.0, 0, 1.0 } */963#define R300_TX_BORDER_COLOR_0 0x45C0964 965/* END: Texture specification */966 967/* BEGIN: Fragment program instruction set */968 969/* Fragment programs are written directly into register space.970 * There are separate instruction streams for texture instructions and ALU971 * instructions.972 * In order to synchronize these streams, the program is divided into up973 * to 4 nodes. Each node begins with a number of TEX operations, followed974 * by a number of ALU operations.975 * The first node can have zero TEX ops, all subsequent nodes must have at976 * least977 * one TEX ops.978 * All nodes must have at least one ALU op.979 *980 * The index of the last node is stored in PFS_CNTL_0: A value of 0 means981 * 1 node, a value of 3 means 4 nodes.982 * The total amount of instructions is defined in PFS_CNTL_2. The offsets are983 * offsets into the respective instruction streams, while *_END points to the984 * last instruction relative to this offset.985 */986#define R300_PFS_CNTL_0 0x4600987# define R300_PFS_CNTL_LAST_NODES_SHIFT 0988# define R300_PFS_CNTL_LAST_NODES_MASK (3 << 0)989# define R300_PFS_CNTL_FIRST_NODE_HAS_TEX (1 << 3)990#define R300_PFS_CNTL_1 0x4604991/* There is an unshifted value here which has so far always been equal to the992 * index of the highest used temporary register.993 */994#define R300_PFS_CNTL_2 0x4608995# define R300_PFS_CNTL_ALU_OFFSET_SHIFT 0996# define R300_PFS_CNTL_ALU_OFFSET_MASK (63 << 0)997# define R300_PFS_CNTL_ALU_END_SHIFT 6998# define R300_PFS_CNTL_ALU_END_MASK (63 << 6)999# define R300_PFS_CNTL_TEX_OFFSET_SHIFT 121000# define R300_PFS_CNTL_TEX_OFFSET_MASK (31 << 12) /* GUESS */1001# define R300_PFS_CNTL_TEX_END_SHIFT 181002# define R300_PFS_CNTL_TEX_END_MASK (31 << 18) /* GUESS */1003 1004/* gap */1005 1006/* Nodes are stored backwards. The last active node is always stored in1007 * PFS_NODE_3.1008 * Example: In a 2-node program, NODE_0 and NODE_1 are set to 0. The1009 * first node is stored in NODE_2, the second node is stored in NODE_3.1010 *1011 * Offsets are relative to the master offset from PFS_CNTL_2.1012 */1013#define R300_PFS_NODE_0 0x46101014#define R300_PFS_NODE_1 0x46141015#define R300_PFS_NODE_2 0x46181016#define R300_PFS_NODE_3 0x461C1017# define R300_PFS_NODE_ALU_OFFSET_SHIFT 01018# define R300_PFS_NODE_ALU_OFFSET_MASK (63 << 0)1019# define R300_PFS_NODE_ALU_END_SHIFT 61020# define R300_PFS_NODE_ALU_END_MASK (63 << 6)1021# define R300_PFS_NODE_TEX_OFFSET_SHIFT 121022# define R300_PFS_NODE_TEX_OFFSET_MASK (31 << 12)1023# define R300_PFS_NODE_TEX_END_SHIFT 171024# define R300_PFS_NODE_TEX_END_MASK (31 << 17)1025# define R300_PFS_NODE_OUTPUT_COLOR (1 << 22)1026# define R300_PFS_NODE_OUTPUT_DEPTH (1 << 23)1027 1028/* TEX1029 * As far as I can tell, texture instructions cannot write into output1030 * registers directly. A subsequent ALU instruction is always necessary,1031 * even if it's just MAD o0, r0, 1, 01032 */1033#define R300_PFS_TEXI_0 0x46201034# define R300_FPITX_SRC_SHIFT 01035# define R300_FPITX_SRC_MASK (31 << 0)1036 /* GUESS */1037# define R300_FPITX_SRC_CONST (1 << 5)1038# define R300_FPITX_DST_SHIFT 61039# define R300_FPITX_DST_MASK (31 << 6)1040# define R300_FPITX_IMAGE_SHIFT 111041 /* GUESS based on layout and native limits */1042# define R300_FPITX_IMAGE_MASK (15 << 11)1043/* Unsure if these are opcodes, or some kind of bitfield, but this is how1044 * they were set when I checked1045 */1046# define R300_FPITX_OPCODE_SHIFT 151047# define R300_FPITX_OP_TEX 11048# define R300_FPITX_OP_KIL 21049# define R300_FPITX_OP_TXP 31050# define R300_FPITX_OP_TXB 41051# define R300_FPITX_OPCODE_MASK (7 << 15)1052 1053/* ALU1054 * The ALU instructions register blocks are enumerated according to the order1055 * in which fglrx. I assume there is space for 64 instructions, since1056 * each block has space for a maximum of 64 DWORDs, and this matches reported1057 * native limits.1058 *1059 * The basic functional block seems to be one MAD for each color and alpha,1060 * and an adder that adds all components after the MUL.1061 * - ADD, MUL, MAD etc.: use MAD with appropriate neutral operands1062 * - DP4: Use OUTC_DP4, OUTA_DP41063 * - DP3: Use OUTC_DP3, OUTA_DP4, appropriate alpha operands1064 * - DPH: Use OUTC_DP4, OUTA_DP4, appropriate alpha operands1065 * - CMPH: If ARG2 > 0.5, return ARG0, else return ARG11066 * - CMP: If ARG2 < 0, return ARG1, else return ARG01067 * - FLR: use FRC+MAD1068 * - XPD: use MAD+MAD1069 * - SGE, SLT: use MAD+CMP1070 * - RSQ: use ABS modifier for argument1071 * - Use OUTC_REPL_ALPHA to write results of an alpha-only operation1072 * (e.g. RCP) into color register1073 * - apparently, there's no quick DST operation1074 * - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2"1075 * - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0"1076 * - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1"1077 *1078 * Operand selection1079 * First stage selects three sources from the available registers and1080 * constant parameters. This is defined in INSTR1 (color) and INSTR3 (alpha).1081 * fglrx sorts the three source fields: Registers before constants,1082 * lower indices before higher indices; I do not know whether this is1083 * necessary.1084 *1085 * fglrx fills unused sources with "read constant 0"1086 * According to specs, you cannot select more than two different constants.1087 *1088 * Second stage selects the operands from the sources. This is defined in1089 * INSTR0 (color) and INSTR2 (alpha). You can also select the special constants1090 * zero and one.1091 * Swizzling and negation happens in this stage, as well.1092 *1093 * Important: Color and alpha seem to be mostly separate, i.e. their sources1094 * selection appears to be fully independent (the register storage is probably1095 * physically split into a color and an alpha section).1096 * However (because of the apparent physical split), there is some interaction1097 * WRT swizzling. If, for example, you want to load an R component into an1098 * Alpha operand, this R component is taken from a *color* source, not from1099 * an alpha source. The corresponding register doesn't even have to appear in1100 * the alpha sources list. (I hope this all makes sense to you)1101 *1102 * Destination selection1103 * The destination register index is in FPI1 (color) and FPI3 (alpha)1104 * together with enable bits.1105 * There are separate enable bits for writing into temporary registers1106 * (DSTC_REG_* /DSTA_REG) and program output registers (DSTC_OUTPUT_*1107 * /DSTA_OUTPUT). You can write to both at once, or not write at all (the1108 * same index must be used for both).1109 *1110 * Note: There is a special form for LRP1111 * - Argument order is the same as in ARB_fragment_program.1112 * - Operation is MAD1113 * - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP1114 * - Set FPI0/FPI2_SPECIAL_LRP1115 * Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD1116 */1117#define R300_PFS_INSTR1_0 0x46C01118# define R300_FPI1_SRC0C_SHIFT 01119# define R300_FPI1_SRC0C_MASK (31 << 0)1120# define R300_FPI1_SRC0C_CONST (1 << 5)1121# define R300_FPI1_SRC1C_SHIFT 61122# define R300_FPI1_SRC1C_MASK (31 << 6)1123# define R300_FPI1_SRC1C_CONST (1 << 11)1124# define R300_FPI1_SRC2C_SHIFT 121125# define R300_FPI1_SRC2C_MASK (31 << 12)1126# define R300_FPI1_SRC2C_CONST (1 << 17)1127# define R300_FPI1_SRC_MASK 0x0003ffff1128# define R300_FPI1_DSTC_SHIFT 181129# define R300_FPI1_DSTC_MASK (31 << 18)1130# define R300_FPI1_DSTC_REG_MASK_SHIFT 231131# define R300_FPI1_DSTC_REG_X (1 << 23)1132# define R300_FPI1_DSTC_REG_Y (1 << 24)1133# define R300_FPI1_DSTC_REG_Z (1 << 25)1134# define R300_FPI1_DSTC_OUTPUT_MASK_SHIFT 261135# define R300_FPI1_DSTC_OUTPUT_X (1 << 26)1136# define R300_FPI1_DSTC_OUTPUT_Y (1 << 27)1137# define R300_FPI1_DSTC_OUTPUT_Z (1 << 28)1138 1139#define R300_PFS_INSTR3_0 0x47C01140# define R300_FPI3_SRC0A_SHIFT 01141# define R300_FPI3_SRC0A_MASK (31 << 0)1142# define R300_FPI3_SRC0A_CONST (1 << 5)1143# define R300_FPI3_SRC1A_SHIFT 61144# define R300_FPI3_SRC1A_MASK (31 << 6)1145# define R300_FPI3_SRC1A_CONST (1 << 11)1146# define R300_FPI3_SRC2A_SHIFT 121147# define R300_FPI3_SRC2A_MASK (31 << 12)1148# define R300_FPI3_SRC2A_CONST (1 << 17)1149# define R300_FPI3_SRC_MASK 0x0003ffff1150# define R300_FPI3_DSTA_SHIFT 181151# define R300_FPI3_DSTA_MASK (31 << 18)1152# define R300_FPI3_DSTA_REG (1 << 23)1153# define R300_FPI3_DSTA_OUTPUT (1 << 24)1154# define R300_FPI3_DSTA_DEPTH (1 << 27)1155 1156#define R300_PFS_INSTR0_0 0x48C01157# define R300_FPI0_ARGC_SRC0C_XYZ 01158# define R300_FPI0_ARGC_SRC0C_XXX 11159# define R300_FPI0_ARGC_SRC0C_YYY 21160# define R300_FPI0_ARGC_SRC0C_ZZZ 31161# define R300_FPI0_ARGC_SRC1C_XYZ 41162# define R300_FPI0_ARGC_SRC1C_XXX 51163# define R300_FPI0_ARGC_SRC1C_YYY 61164# define R300_FPI0_ARGC_SRC1C_ZZZ 71165# define R300_FPI0_ARGC_SRC2C_XYZ 81166# define R300_FPI0_ARGC_SRC2C_XXX 91167# define R300_FPI0_ARGC_SRC2C_YYY 101168# define R300_FPI0_ARGC_SRC2C_ZZZ 111169# define R300_FPI0_ARGC_SRC0A 121170# define R300_FPI0_ARGC_SRC1A 131171# define R300_FPI0_ARGC_SRC2A 141172# define R300_FPI0_ARGC_SRC1C_LRP 151173# define R300_FPI0_ARGC_ZERO 201174# define R300_FPI0_ARGC_ONE 211175 /* GUESS */1176# define R300_FPI0_ARGC_HALF 221177# define R300_FPI0_ARGC_SRC0C_YZX 231178# define R300_FPI0_ARGC_SRC1C_YZX 241179# define R300_FPI0_ARGC_SRC2C_YZX 251180# define R300_FPI0_ARGC_SRC0C_ZXY 261181# define R300_FPI0_ARGC_SRC1C_ZXY 271182# define R300_FPI0_ARGC_SRC2C_ZXY 281183# define R300_FPI0_ARGC_SRC0CA_WZY 291184# define R300_FPI0_ARGC_SRC1CA_WZY 301185# define R300_FPI0_ARGC_SRC2CA_WZY 311186 1187# define R300_FPI0_ARG0C_SHIFT 01188# define R300_FPI0_ARG0C_MASK (31 << 0)1189# define R300_FPI0_ARG0C_NEG (1 << 5)1190# define R300_FPI0_ARG0C_ABS (1 << 6)1191# define R300_FPI0_ARG1C_SHIFT 71192# define R300_FPI0_ARG1C_MASK (31 << 7)1193# define R300_FPI0_ARG1C_NEG (1 << 12)1194# define R300_FPI0_ARG1C_ABS (1 << 13)1195# define R300_FPI0_ARG2C_SHIFT 141196# define R300_FPI0_ARG2C_MASK (31 << 14)1197# define R300_FPI0_ARG2C_NEG (1 << 19)1198# define R300_FPI0_ARG2C_ABS (1 << 20)1199# define R300_FPI0_SPECIAL_LRP (1 << 21)1200# define R300_FPI0_OUTC_MAD (0 << 23)1201# define R300_FPI0_OUTC_DP3 (1 << 23)1202# define R300_FPI0_OUTC_DP4 (2 << 23)1203# define R300_FPI0_OUTC_MIN (4 << 23)1204# define R300_FPI0_OUTC_MAX (5 << 23)1205# define R300_FPI0_OUTC_CMPH (7 << 23)1206# define R300_FPI0_OUTC_CMP (8 << 23)1207# define R300_FPI0_OUTC_FRC (9 << 23)1208# define R300_FPI0_OUTC_REPL_ALPHA (10 << 23)1209# define R300_FPI0_OUTC_SAT (1 << 30)1210# define R300_FPI0_INSERT_NOP (1 << 31)1211 1212#define R300_PFS_INSTR2_0 0x49C01213# define R300_FPI2_ARGA_SRC0C_X 01214# define R300_FPI2_ARGA_SRC0C_Y 11215# define R300_FPI2_ARGA_SRC0C_Z 21216# define R300_FPI2_ARGA_SRC1C_X 31217# define R300_FPI2_ARGA_SRC1C_Y 41218# define R300_FPI2_ARGA_SRC1C_Z 51219# define R300_FPI2_ARGA_SRC2C_X 61220# define R300_FPI2_ARGA_SRC2C_Y 71221# define R300_FPI2_ARGA_SRC2C_Z 81222# define R300_FPI2_ARGA_SRC0A 91223# define R300_FPI2_ARGA_SRC1A 101224# define R300_FPI2_ARGA_SRC2A 111225# define R300_FPI2_ARGA_SRC1A_LRP 151226# define R300_FPI2_ARGA_ZERO 161227# define R300_FPI2_ARGA_ONE 171228 /* GUESS */1229# define R300_FPI2_ARGA_HALF 181230# define R300_FPI2_ARG0A_SHIFT 01231# define R300_FPI2_ARG0A_MASK (31 << 0)1232# define R300_FPI2_ARG0A_NEG (1 << 5)1233 /* GUESS */1234# define R300_FPI2_ARG0A_ABS (1 << 6)1235# define R300_FPI2_ARG1A_SHIFT 71236# define R300_FPI2_ARG1A_MASK (31 << 7)1237# define R300_FPI2_ARG1A_NEG (1 << 12)1238 /* GUESS */1239# define R300_FPI2_ARG1A_ABS (1 << 13)1240# define R300_FPI2_ARG2A_SHIFT 141241# define R300_FPI2_ARG2A_MASK (31 << 14)1242# define R300_FPI2_ARG2A_NEG (1 << 19)1243 /* GUESS */1244# define R300_FPI2_ARG2A_ABS (1 << 20)1245# define R300_FPI2_SPECIAL_LRP (1 << 21)1246# define R300_FPI2_OUTA_MAD (0 << 23)1247# define R300_FPI2_OUTA_DP4 (1 << 23)1248# define R300_FPI2_OUTA_MIN (2 << 23)1249# define R300_FPI2_OUTA_MAX (3 << 23)1250# define R300_FPI2_OUTA_CMP (6 << 23)1251# define R300_FPI2_OUTA_FRC (7 << 23)1252# define R300_FPI2_OUTA_EX2 (8 << 23)1253# define R300_FPI2_OUTA_LG2 (9 << 23)1254# define R300_FPI2_OUTA_RCP (10 << 23)1255# define R300_FPI2_OUTA_RSQ (11 << 23)1256# define R300_FPI2_OUTA_SAT (1 << 30)1257# define R300_FPI2_UNKNOWN_31 (1 << 31)1258/* END: Fragment program instruction set */1259 1260/* Fog state and color */1261#define R300_RE_FOG_STATE 0x4BC01262# define R300_FOG_ENABLE (1 << 0)1263# define R300_FOG_MODE_LINEAR (0 << 1)1264# define R300_FOG_MODE_EXP (1 << 1)1265# define R300_FOG_MODE_EXP2 (2 << 1)1266# define R300_FOG_MODE_MASK (3 << 1)1267#define R300_FOG_COLOR_R 0x4BC81268#define R300_FOG_COLOR_G 0x4BCC1269#define R300_FOG_COLOR_B 0x4BD01270 1271#define R300_PP_ALPHA_TEST 0x4BD41272# define R300_REF_ALPHA_MASK 0x000000ff1273# define R300_ALPHA_TEST_FAIL (0 << 8)1274# define R300_ALPHA_TEST_LESS (1 << 8)1275# define R300_ALPHA_TEST_LEQUAL (3 << 8)1276# define R300_ALPHA_TEST_EQUAL (2 << 8)1277# define R300_ALPHA_TEST_GEQUAL (6 << 8)1278# define R300_ALPHA_TEST_GREATER (4 << 8)1279# define R300_ALPHA_TEST_NEQUAL (5 << 8)1280# define R300_ALPHA_TEST_PASS (7 << 8)1281# define R300_ALPHA_TEST_OP_MASK (7 << 8)1282# define R300_ALPHA_TEST_ENABLE (1 << 11)1283 1284/* gap */1285 1286/* Fragment program parameters in 7.16 floating point */1287#define R300_PFS_PARAM_0_X 0x4C001288#define R300_PFS_PARAM_0_Y 0x4C041289#define R300_PFS_PARAM_0_Z 0x4C081290#define R300_PFS_PARAM_0_W 0x4C0C1291/* GUESS: PARAM_31 is last, based on native limits reported by fglrx */1292#define R300_PFS_PARAM_31_X 0x4DF01293#define R300_PFS_PARAM_31_Y 0x4DF41294#define R300_PFS_PARAM_31_Z 0x4DF81295#define R300_PFS_PARAM_31_W 0x4DFC1296 1297/* Notes:1298 * - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in1299 * the application1300 * - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND1301 * are set to the same1302 * function (both registers are always set up completely in any case)1303 * - Most blend flags are simply copied from R200 and not tested yet1304 */1305#define R300_RB3D_CBLEND 0x4E041306#define R300_RB3D_ABLEND 0x4E081307/* the following only appear in CBLEND */1308# define R300_BLEND_ENABLE (1 << 0)1309# define R300_BLEND_UNKNOWN (3 << 1)1310# define R300_BLEND_NO_SEPARATE (1 << 3)1311/* the following are shared between CBLEND and ABLEND */1312# define R300_FCN_MASK (3 << 12)1313# define R300_COMB_FCN_ADD_CLAMP (0 << 12)1314# define R300_COMB_FCN_ADD_NOCLAMP (1 << 12)1315# define R300_COMB_FCN_SUB_CLAMP (2 << 12)1316# define R300_COMB_FCN_SUB_NOCLAMP (3 << 12)1317# define R300_COMB_FCN_MIN (4 << 12)1318# define R300_COMB_FCN_MAX (5 << 12)1319# define R300_COMB_FCN_RSUB_CLAMP (6 << 12)1320# define R300_COMB_FCN_RSUB_NOCLAMP (7 << 12)1321# define R300_BLEND_GL_ZERO (32)1322# define R300_BLEND_GL_ONE (33)1323# define R300_BLEND_GL_SRC_COLOR (34)1324# define R300_BLEND_GL_ONE_MINUS_SRC_COLOR (35)1325# define R300_BLEND_GL_DST_COLOR (36)1326# define R300_BLEND_GL_ONE_MINUS_DST_COLOR (37)1327# define R300_BLEND_GL_SRC_ALPHA (38)1328# define R300_BLEND_GL_ONE_MINUS_SRC_ALPHA (39)1329# define R300_BLEND_GL_DST_ALPHA (40)1330# define R300_BLEND_GL_ONE_MINUS_DST_ALPHA (41)1331# define R300_BLEND_GL_SRC_ALPHA_SATURATE (42)1332# define R300_BLEND_GL_CONST_COLOR (43)1333# define R300_BLEND_GL_ONE_MINUS_CONST_COLOR (44)1334# define R300_BLEND_GL_CONST_ALPHA (45)1335# define R300_BLEND_GL_ONE_MINUS_CONST_ALPHA (46)1336# define R300_BLEND_MASK (63)1337# define R300_SRC_BLEND_SHIFT (16)1338# define R300_DST_BLEND_SHIFT (24)1339#define R300_RB3D_BLEND_COLOR 0x4E101340#define R300_RB3D_COLORMASK 0x4E0C1341# define R300_COLORMASK0_B (1<<0)1342# define R300_COLORMASK0_G (1<<1)1343# define R300_COLORMASK0_R (1<<2)1344# define R300_COLORMASK0_A (1<<3)1345 1346/* gap */1347 1348#define R300_RB3D_COLOROFFSET0 0x4E281349# define R300_COLOROFFSET_MASK 0xFFFFFFF0 /* GUESS */1350#define R300_RB3D_COLOROFFSET1 0x4E2C /* GUESS */1351#define R300_RB3D_COLOROFFSET2 0x4E30 /* GUESS */1352#define R300_RB3D_COLOROFFSET3 0x4E34 /* GUESS */1353 1354/* gap */1355 1356/* Bit 16: Larger tiles1357 * Bit 17: 4x2 tiles1358 * Bit 18: Extremely weird tile like, but some pixels duplicated?1359 */1360#define R300_RB3D_COLORPITCH0 0x4E381361# define R300_COLORPITCH_MASK 0x00001FF8 /* GUESS */1362# define R300_COLOR_TILE_ENABLE (1 << 16) /* GUESS */1363# define R300_COLOR_MICROTILE_ENABLE (1 << 17) /* GUESS */1364# define R300_COLOR_MICROTILE_SQUARE_ENABLE (2 << 17)1365# define R300_COLOR_ENDIAN_NO_SWAP (0 << 18) /* GUESS */1366# define R300_COLOR_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */1367# define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */1368# define R300_COLOR_FORMAT_RGB565 (2 << 22)1369# define R300_COLOR_FORMAT_ARGB8888 (3 << 22)1370#define R300_RB3D_COLORPITCH1 0x4E3C /* GUESS */1371#define R300_RB3D_COLORPITCH2 0x4E40 /* GUESS */1372#define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */1373 1374#define R300_RB3D_AARESOLVE_OFFSET 0x4E801375#define R300_RB3D_AARESOLVE_PITCH 0x4E841376#define R300_RB3D_AARESOLVE_CTL 0x4E881377/* gap */1378 1379/* Guess by Vladimir.1380 * Set to 0A before 3D operations, set to 02 afterwards.1381 */1382/*#define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C*/1383# define R300_RB3D_DSTCACHE_UNKNOWN_02 0x000000021384# define R300_RB3D_DSTCACHE_UNKNOWN_0A 0x0000000A1385 1386/* gap */1387/* There seems to be no "write only" setting, so use Z-test = ALWAYS1388 * for this.1389 * Bit (1<<8) is the "test" bit. so plain write is 6 - vd1390 */1391#define R300_ZB_CNTL 0x4F001392# define R300_STENCIL_ENABLE (1 << 0)1393# define R300_Z_ENABLE (1 << 1)1394# define R300_Z_WRITE_ENABLE (1 << 2)1395# define R300_Z_SIGNED_COMPARE (1 << 3)1396# define R300_STENCIL_FRONT_BACK (1 << 4)1397 1398#define R300_ZB_ZSTENCILCNTL 0x4f041399 /* functions */1400# define R300_ZS_NEVER 01401# define R300_ZS_LESS 11402# define R300_ZS_LEQUAL 21403# define R300_ZS_EQUAL 31404# define R300_ZS_GEQUAL 41405# define R300_ZS_GREATER 51406# define R300_ZS_NOTEQUAL 61407# define R300_ZS_ALWAYS 71408# define R300_ZS_MASK 71409 /* operations */1410# define R300_ZS_KEEP 01411# define R300_ZS_ZERO 11412# define R300_ZS_REPLACE 21413# define R300_ZS_INCR 31414# define R300_ZS_DECR 41415# define R300_ZS_INVERT 51416# define R300_ZS_INCR_WRAP 61417# define R300_ZS_DECR_WRAP 71418# define R300_Z_FUNC_SHIFT 01419 /* front and back refer to operations done for front1420 and back faces, i.e. separate stencil function support */1421# define R300_S_FRONT_FUNC_SHIFT 31422# define R300_S_FRONT_SFAIL_OP_SHIFT 61423# define R300_S_FRONT_ZPASS_OP_SHIFT 91424# define R300_S_FRONT_ZFAIL_OP_SHIFT 121425# define R300_S_BACK_FUNC_SHIFT 151426# define R300_S_BACK_SFAIL_OP_SHIFT 181427# define R300_S_BACK_ZPASS_OP_SHIFT 211428# define R300_S_BACK_ZFAIL_OP_SHIFT 241429 1430#define R300_ZB_STENCILREFMASK 0x4f081431# define R300_STENCILREF_SHIFT 01432# define R300_STENCILREF_MASK 0x000000ff1433# define R300_STENCILMASK_SHIFT 81434# define R300_STENCILMASK_MASK 0x0000ff001435# define R300_STENCILWRITEMASK_SHIFT 161436# define R300_STENCILWRITEMASK_MASK 0x00ff00001437 1438/* gap */1439 1440#define R300_ZB_FORMAT 0x4f101441# define R300_DEPTHFORMAT_16BIT_INT_Z (0 << 0)1442# define R300_DEPTHFORMAT_16BIT_13E3 (1 << 0)1443# define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL (2 << 0)1444/* reserved up to (15 << 0) */1445# define R300_INVERT_13E3_LEADING_ONES (0 << 4)1446# define R300_INVERT_13E3_LEADING_ZEROS (1 << 4)1447 1448#define R300_ZB_ZTOP 0x4F141449# define R300_ZTOP_DISABLE (0 << 0)1450# define R300_ZTOP_ENABLE (1 << 0)1451 1452/* gap */1453 1454#define R300_ZB_ZCACHE_CTLSTAT 0x4f181455# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0)1456# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0)1457# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1)1458# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1)1459# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31)1460# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31)1461 1462#define R300_ZB_BW_CNTL 0x4f1c1463# define R300_HIZ_DISABLE (0 << 0)1464# define R300_HIZ_ENABLE (1 << 0)1465# define R300_HIZ_MIN (0 << 1)1466# define R300_HIZ_MAX (1 << 1)1467# define R300_FAST_FILL_DISABLE (0 << 2)1468# define R300_FAST_FILL_ENABLE (1 << 2)1469# define R300_RD_COMP_DISABLE (0 << 3)1470# define R300_RD_COMP_ENABLE (1 << 3)1471# define R300_WR_COMP_DISABLE (0 << 4)1472# define R300_WR_COMP_ENABLE (1 << 4)1473# define R300_ZB_CB_CLEAR_RMW (0 << 5)1474# define R300_ZB_CB_CLEAR_CACHE_LINEAR (1 << 5)1475# define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6)1476# define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6)1477 1478# define R500_ZEQUAL_OPTIMIZE_ENABLE (0 << 7)1479# define R500_ZEQUAL_OPTIMIZE_DISABLE (1 << 7)1480# define R500_SEQUAL_OPTIMIZE_ENABLE (0 << 8)1481# define R500_SEQUAL_OPTIMIZE_DISABLE (1 << 8)1482 1483# define R500_BMASK_ENABLE (0 << 10)1484# define R500_BMASK_DISABLE (1 << 10)1485# define R500_HIZ_EQUAL_REJECT_DISABLE (0 << 11)1486# define R500_HIZ_EQUAL_REJECT_ENABLE (1 << 11)1487# define R500_HIZ_FP_EXP_BITS_DISABLE (0 << 12)1488# define R500_HIZ_FP_EXP_BITS_1 (1 << 12)1489# define R500_HIZ_FP_EXP_BITS_2 (2 << 12)1490# define R500_HIZ_FP_EXP_BITS_3 (3 << 12)1491# define R500_HIZ_FP_EXP_BITS_4 (4 << 12)1492# define R500_HIZ_FP_EXP_BITS_5 (5 << 12)1493# define R500_HIZ_FP_INVERT_LEADING_ONES (0 << 15)1494# define R500_HIZ_FP_INVERT_LEADING_ZEROS (1 << 15)1495# define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16)1496# define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16)1497# define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17)1498# define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17)1499# define R500_PEQ_PACKING_DISABLE (0 << 18)1500# define R500_PEQ_PACKING_ENABLE (1 << 18)1501# define R500_COVERED_PTR_MASKING_DISABLE (0 << 18)1502# define R500_COVERED_PTR_MASKING_ENABLE (1 << 18)1503 1504 1505/* gap */1506 1507/* Z Buffer Address Offset.1508 * Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles.1509 */1510#define R300_ZB_DEPTHOFFSET 0x4f201511 1512/* Z Buffer Pitch and Endian Control */1513#define R300_ZB_DEPTHPITCH 0x4f241514# define R300_DEPTHPITCH_MASK 0x00003FFC1515# define R300_DEPTHMACROTILE_DISABLE (0 << 16)1516# define R300_DEPTHMACROTILE_ENABLE (1 << 16)1517# define R300_DEPTHMICROTILE_LINEAR (0 << 17)1518# define R300_DEPTHMICROTILE_TILED (1 << 17)1519# define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17)1520# define R300_DEPTHENDIAN_NO_SWAP (0 << 18)1521# define R300_DEPTHENDIAN_WORD_SWAP (1 << 18)1522# define R300_DEPTHENDIAN_DWORD_SWAP (2 << 18)1523# define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18)1524 1525/* Z Buffer Clear Value */1526#define R300_ZB_DEPTHCLEARVALUE 0x4f281527 1528#define R300_ZB_ZMASK_OFFSET 0x4f301529#define R300_ZB_ZMASK_PITCH 0x4f341530#define R300_ZB_ZMASK_WRINDEX 0x4f381531#define R300_ZB_ZMASK_DWORD 0x4f3c1532#define R300_ZB_ZMASK_RDINDEX 0x4f401533 1534/* Hierarchical Z Memory Offset */1535#define R300_ZB_HIZ_OFFSET 0x4f441536 1537/* Hierarchical Z Write Index */1538#define R300_ZB_HIZ_WRINDEX 0x4f481539 1540/* Hierarchical Z Data */1541#define R300_ZB_HIZ_DWORD 0x4f4c1542 1543/* Hierarchical Z Read Index */1544#define R300_ZB_HIZ_RDINDEX 0x4f501545 1546/* Hierarchical Z Pitch */1547#define R300_ZB_HIZ_PITCH 0x4f541548 1549/* Z Buffer Z Pass Counter Data */1550#define R300_ZB_ZPASS_DATA 0x4f581551 1552/* Z Buffer Z Pass Counter Address */1553#define R300_ZB_ZPASS_ADDR 0x4f5c1554 1555/* Depth buffer X and Y coordinate offset */1556#define R300_ZB_DEPTHXY_OFFSET 0x4f601557# define R300_DEPTHX_OFFSET_SHIFT 11558# define R300_DEPTHX_OFFSET_MASK 0x000007FE1559# define R300_DEPTHY_OFFSET_SHIFT 171560# define R300_DEPTHY_OFFSET_MASK 0x07FE00001561 1562/* Sets the fifo sizes */1563#define R500_ZB_FIFO_SIZE 0x4fd01564# define R500_OP_FIFO_SIZE_FULL (0 << 0)1565# define R500_OP_FIFO_SIZE_HALF (1 << 0)1566# define R500_OP_FIFO_SIZE_QUATER (2 << 0)1567# define R500_OP_FIFO_SIZE_EIGTHS (4 << 0)1568 1569/* Stencil Reference Value and Mask for backfacing quads */1570/* R300_ZB_STENCILREFMASK handles front face */1571#define R500_ZB_STENCILREFMASK_BF 0x4fd41572# define R500_STENCILREF_SHIFT 01573# define R500_STENCILREF_MASK 0x000000ff1574# define R500_STENCILMASK_SHIFT 81575# define R500_STENCILMASK_MASK 0x0000ff001576# define R500_STENCILWRITEMASK_SHIFT 161577# define R500_STENCILWRITEMASK_MASK 0x00ff00001578 1579/* BEGIN: Vertex program instruction set */1580 1581/* Every instruction is four dwords long:1582 * DWORD 0: output and opcode1583 * DWORD 1: first argument1584 * DWORD 2: second argument1585 * DWORD 3: third argument1586 *1587 * Notes:1588 * - ABS r, a is implemented as MAX r, a, -a1589 * - MOV is implemented as ADD to zero1590 * - XPD is implemented as MUL + MAD1591 * - FLR is implemented as FRC + ADD1592 * - apparently, fglrx tries to schedule instructions so that there is at1593 * least one instruction between the write to a temporary and the first1594 * read from said temporary; however, violations of this scheduling are1595 * allowed1596 * - register indices seem to be unrelated with OpenGL aliasing to1597 * conventional state1598 * - only one attribute and one parameter can be loaded at a time; however,1599 * the same attribute/parameter can be used for more than one argument1600 * - the second software argument for POW is the third hardware argument1601 * (no idea why)1602 * - MAD with only temporaries as input seems to use VPI_OUT_SELECT_MAD_21603 *1604 * There is some magic surrounding LIT:1605 * The single argument is replicated across all three inputs, but swizzled:1606 * First argument: xyzy1607 * Second argument: xyzx1608 * Third argument: xyzw1609 * Whenever the result is used later in the fragment program, fglrx forces1610 * x and w to be 1.0 in the input selection; I don't know whether this is1611 * strictly necessary1612 */1613#define R300_VPI_OUT_OP_DOT (1 << 0)1614#define R300_VPI_OUT_OP_MUL (2 << 0)1615#define R300_VPI_OUT_OP_ADD (3 << 0)1616#define R300_VPI_OUT_OP_MAD (4 << 0)1617#define R300_VPI_OUT_OP_DST (5 << 0)1618#define R300_VPI_OUT_OP_FRC (6 << 0)1619#define R300_VPI_OUT_OP_MAX (7 << 0)1620#define R300_VPI_OUT_OP_MIN (8 << 0)1621#define R300_VPI_OUT_OP_SGE (9 << 0)1622#define R300_VPI_OUT_OP_SLT (10 << 0)1623 /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, vector(scalar, vector) */1624#define R300_VPI_OUT_OP_UNK12 (12 << 0)1625#define R300_VPI_OUT_OP_ARL (13 << 0)1626#define R300_VPI_OUT_OP_EXP (65 << 0)1627#define R300_VPI_OUT_OP_LOG (66 << 0)1628 /* Used in fog computations, scalar(scalar) */1629#define R300_VPI_OUT_OP_UNK67 (67 << 0)1630#define R300_VPI_OUT_OP_LIT (68 << 0)1631#define R300_VPI_OUT_OP_POW (69 << 0)1632#define R300_VPI_OUT_OP_RCP (70 << 0)1633#define R300_VPI_OUT_OP_RSQ (72 << 0)1634 /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, scalar(scalar) */1635#define R300_VPI_OUT_OP_UNK73 (73 << 0)1636#define R300_VPI_OUT_OP_EX2 (75 << 0)1637#define R300_VPI_OUT_OP_LG2 (76 << 0)1638#define R300_VPI_OUT_OP_MAD_2 (128 << 0)1639 /* all temps, vector(scalar, vector, vector) */1640#define R300_VPI_OUT_OP_UNK129 (129 << 0)1641 1642#define R300_VPI_OUT_REG_CLASS_TEMPORARY (0 << 8)1643#define R300_VPI_OUT_REG_CLASS_ADDR (1 << 8)1644#define R300_VPI_OUT_REG_CLASS_RESULT (2 << 8)1645#define R300_VPI_OUT_REG_CLASS_MASK (31 << 8)1646 1647#define R300_VPI_OUT_REG_INDEX_SHIFT 131648 /* GUESS based on fglrx native limits */1649#define R300_VPI_OUT_REG_INDEX_MASK (31 << 13)1650 1651#define R300_VPI_OUT_WRITE_X (1 << 20)1652#define R300_VPI_OUT_WRITE_Y (1 << 21)1653#define R300_VPI_OUT_WRITE_Z (1 << 22)1654#define R300_VPI_OUT_WRITE_W (1 << 23)1655 1656#define R300_VPI_IN_REG_CLASS_TEMPORARY (0 << 0)1657#define R300_VPI_IN_REG_CLASS_ATTRIBUTE (1 << 0)1658#define R300_VPI_IN_REG_CLASS_PARAMETER (2 << 0)1659#define R300_VPI_IN_REG_CLASS_NONE (9 << 0)1660#define R300_VPI_IN_REG_CLASS_MASK (31 << 0)1661 1662#define R300_VPI_IN_REG_INDEX_SHIFT 51663 /* GUESS based on fglrx native limits */1664#define R300_VPI_IN_REG_INDEX_MASK (255 << 5)1665 1666/* The R300 can select components from the input register arbitrarily.1667 * Use the following constants, shifted by the component shift you1668 * want to select1669 */1670#define R300_VPI_IN_SELECT_X 01671#define R300_VPI_IN_SELECT_Y 11672#define R300_VPI_IN_SELECT_Z 21673#define R300_VPI_IN_SELECT_W 31674#define R300_VPI_IN_SELECT_ZERO 41675#define R300_VPI_IN_SELECT_ONE 51676#define R300_VPI_IN_SELECT_MASK 71677 1678#define R300_VPI_IN_X_SHIFT 131679#define R300_VPI_IN_Y_SHIFT 161680#define R300_VPI_IN_Z_SHIFT 191681#define R300_VPI_IN_W_SHIFT 221682 1683#define R300_VPI_IN_NEG_X (1 << 25)1684#define R300_VPI_IN_NEG_Y (1 << 26)1685#define R300_VPI_IN_NEG_Z (1 << 27)1686#define R300_VPI_IN_NEG_W (1 << 28)1687/* END: Vertex program instruction set */1688 1689/* BEGIN: Packet 3 commands */1690 1691/* A primitive emission dword. */1692#define R300_PRIM_TYPE_NONE (0 << 0)1693#define R300_PRIM_TYPE_POINT (1 << 0)1694#define R300_PRIM_TYPE_LINE (2 << 0)1695#define R300_PRIM_TYPE_LINE_STRIP (3 << 0)1696#define R300_PRIM_TYPE_TRI_LIST (4 << 0)1697#define R300_PRIM_TYPE_TRI_FAN (5 << 0)1698#define R300_PRIM_TYPE_TRI_STRIP (6 << 0)1699#define R300_PRIM_TYPE_TRI_TYPE2 (7 << 0)1700#define R300_PRIM_TYPE_RECT_LIST (8 << 0)1701#define R300_PRIM_TYPE_3VRT_POINT_LIST (9 << 0)1702#define R300_PRIM_TYPE_3VRT_LINE_LIST (10 << 0)1703 /* GUESS (based on r200) */1704#define R300_PRIM_TYPE_POINT_SPRITES (11 << 0)1705#define R300_PRIM_TYPE_LINE_LOOP (12 << 0)1706#define R300_PRIM_TYPE_QUADS (13 << 0)1707#define R300_PRIM_TYPE_QUAD_STRIP (14 << 0)1708#define R300_PRIM_TYPE_POLYGON (15 << 0)1709#define R300_PRIM_TYPE_MASK 0xF1710#define R300_PRIM_WALK_IND (1 << 4)1711#define R300_PRIM_WALK_LIST (2 << 4)1712#define R300_PRIM_WALK_RING (3 << 4)1713#define R300_PRIM_WALK_MASK (3 << 4)1714 /* GUESS (based on r200) */1715#define R300_PRIM_COLOR_ORDER_BGRA (0 << 6)1716#define R300_PRIM_COLOR_ORDER_RGBA (1 << 6)1717#define R300_PRIM_NUM_VERTICES_SHIFT 161718#define R300_PRIM_NUM_VERTICES_MASK 0xffff1719 1720/* Draw a primitive from vertex data in arrays loaded via 3D_LOAD_VBPNTR.1721 * Two parameter dwords:1722 * 0. The first parameter appears to be always 01723 * 1. The second parameter is a standard primitive emission dword.1724 */1725#define R300_PACKET3_3D_DRAW_VBUF 0x000028001726 1727/* Specify the full set of vertex arrays as (address, stride).1728 * The first parameter is the number of vertex arrays specified.1729 * The rest of the command is a variable length list of blocks, where1730 * each block is three dwords long and specifies two arrays.1731 * The first dword of a block is split into two words, the lower significant1732 * word refers to the first array, the more significant word to the second1733 * array in the block.1734 * The low byte of each word contains the size of an array entry in dwords,1735 * the high byte contains the stride of the array.1736 * The second dword of a block contains the pointer to the first array,1737 * the third dword of a block contains the pointer to the second array.1738 * Note that if the total number of arrays is odd, the third dword of1739 * the last block is omitted.1740 */1741#define R300_PACKET3_3D_LOAD_VBPNTR 0x00002F001742 1743#define R300_PACKET3_INDX_BUFFER 0x000033001744# define R300_EB_UNK1_SHIFT 241745# define R300_EB_UNK1 (0x80<<24)1746# define R300_EB_UNK2 0x08101747#define R300_PACKET3_3D_DRAW_VBUF_2 0x000034001748#define R300_PACKET3_3D_DRAW_INDX_2 0x000036001749 1750/* END: Packet 3 commands */1751 1752 1753/* Color formats for 2d packets1754 */1755#define R300_CP_COLOR_FORMAT_CI8 21756#define R300_CP_COLOR_FORMAT_ARGB1555 31757#define R300_CP_COLOR_FORMAT_RGB565 41758#define R300_CP_COLOR_FORMAT_ARGB8888 61759#define R300_CP_COLOR_FORMAT_RGB332 71760#define R300_CP_COLOR_FORMAT_RGB8 91761#define R300_CP_COLOR_FORMAT_ARGB4444 151762 1763/*1764 * CP type-3 packets1765 */1766#define R300_CP_CMD_BITBLT_MULTI 0xC0009B001767 1768#define R500_VAP_INDEX_OFFSET 0x208c1769 1770#define R500_GA_US_VECTOR_INDEX 0x42501771#define R500_GA_US_VECTOR_DATA 0x42541772 1773#define R500_RS_IP_0 0x40741774#define R500_RS_INST_0 0x43201775 1776#define R500_US_CONFIG 0x46001777 1778#define R500_US_FC_CTRL 0x46241779#define R500_US_CODE_ADDR 0x46301780 1781#define R500_RB3D_COLOR_CLEAR_VALUE_AR 0x46c01782#define R500_RB3D_CONSTANT_COLOR_AR 0x4ef81783 1784#define R300_SU_REG_DEST 0x42c81785#define RV530_FG_ZBREG_DEST 0x4be81786#define R300_ZB_ZPASS_DATA 0x4f581787#define R300_ZB_ZPASS_ADDR 0x4f5c1788 1789#endif /* _R300_REG_H */1790