2534 lines · c
1/*2 * Copyright 2008 Advanced Micro Devices, Inc.3 * Copyright 2008 Red Hat Inc.4 * Copyright 2009 Jerome Glisse.5 *6 * Permission is hereby granted, free of charge, to any person obtaining a7 * copy of this software and associated documentation files (the "Software"),8 * to deal in the Software without restriction, including without limitation9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,10 * and/or sell copies of the Software, and to permit persons to whom the11 * Software is furnished to do so, subject to the following conditions:12 *13 * The above copyright notice and this permission notice shall be included in14 * all copies or substantial portions of the Software.15 *16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR22 * OTHER DEALINGS IN THE SOFTWARE.23 *24 * Authors: Dave Airlie25 * Alex Deucher26 * Jerome Glisse27 */28#include <linux/kernel.h>29 30#include "radeon.h"31#include "radeon_asic.h"32#include "r600.h"33#include "r600d.h"34#include "r600_reg_safe.h"35 36static int r600_nomm;37 38struct r600_cs_track {39 /* configuration we mirror so that we use same code btw kms/ums */40 u32 group_size;41 u32 nbanks;42 u32 npipes;43 /* value we track */44 u32 sq_config;45 u32 log_nsamples;46 u32 nsamples;47 u32 cb_color_base_last[8];48 struct radeon_bo *cb_color_bo[8];49 u64 cb_color_bo_mc[8];50 u64 cb_color_bo_offset[8];51 struct radeon_bo *cb_color_frag_bo[8];52 u64 cb_color_frag_offset[8];53 struct radeon_bo *cb_color_tile_bo[8];54 u64 cb_color_tile_offset[8];55 u32 cb_color_mask[8];56 u32 cb_color_info[8];57 u32 cb_color_view[8];58 u32 cb_color_size_idx[8]; /* unused */59 u32 cb_target_mask;60 u32 cb_shader_mask; /* unused */61 bool is_resolve;62 u32 cb_color_size[8];63 u32 vgt_strmout_en;64 u32 vgt_strmout_buffer_en;65 struct radeon_bo *vgt_strmout_bo[4];66 u64 vgt_strmout_bo_mc[4]; /* unused */67 u32 vgt_strmout_bo_offset[4];68 u32 vgt_strmout_size[4];69 u32 db_depth_control;70 u32 db_depth_info;71 u32 db_depth_size_idx;72 u32 db_depth_view;73 u32 db_depth_size;74 u32 db_offset;75 struct radeon_bo *db_bo;76 u64 db_bo_mc;77 bool sx_misc_kill_all_prims;78 bool cb_dirty;79 bool db_dirty;80 bool streamout_dirty;81 struct radeon_bo *htile_bo;82 u64 htile_offset;83 u32 htile_surface;84};85 86#define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 }87#define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc, CHIP_R600 }88#define FMT_24_BIT(fmt) [fmt] = { 1, 1, 4, 0, CHIP_R600 }89#define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc, CHIP_R600 }90#define FMT_48_BIT(fmt) [fmt] = { 1, 1, 8, 0, CHIP_R600 }91#define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc, CHIP_R600 }92#define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0, CHIP_R600 }93#define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 }94 95struct gpu_formats {96 unsigned blockwidth;97 unsigned blockheight;98 unsigned blocksize;99 unsigned valid_color;100 enum radeon_family min_family;101};102 103static const struct gpu_formats color_formats_table[] = {104 /* 8 bit */105 FMT_8_BIT(V_038004_COLOR_8, 1),106 FMT_8_BIT(V_038004_COLOR_4_4, 1),107 FMT_8_BIT(V_038004_COLOR_3_3_2, 1),108 FMT_8_BIT(V_038004_FMT_1, 0),109 110 /* 16-bit */111 FMT_16_BIT(V_038004_COLOR_16, 1),112 FMT_16_BIT(V_038004_COLOR_16_FLOAT, 1),113 FMT_16_BIT(V_038004_COLOR_8_8, 1),114 FMT_16_BIT(V_038004_COLOR_5_6_5, 1),115 FMT_16_BIT(V_038004_COLOR_6_5_5, 1),116 FMT_16_BIT(V_038004_COLOR_1_5_5_5, 1),117 FMT_16_BIT(V_038004_COLOR_4_4_4_4, 1),118 FMT_16_BIT(V_038004_COLOR_5_5_5_1, 1),119 120 /* 24-bit */121 FMT_24_BIT(V_038004_FMT_8_8_8),122 123 /* 32-bit */124 FMT_32_BIT(V_038004_COLOR_32, 1),125 FMT_32_BIT(V_038004_COLOR_32_FLOAT, 1),126 FMT_32_BIT(V_038004_COLOR_16_16, 1),127 FMT_32_BIT(V_038004_COLOR_16_16_FLOAT, 1),128 FMT_32_BIT(V_038004_COLOR_8_24, 1),129 FMT_32_BIT(V_038004_COLOR_8_24_FLOAT, 1),130 FMT_32_BIT(V_038004_COLOR_24_8, 1),131 FMT_32_BIT(V_038004_COLOR_24_8_FLOAT, 1),132 FMT_32_BIT(V_038004_COLOR_10_11_11, 1),133 FMT_32_BIT(V_038004_COLOR_10_11_11_FLOAT, 1),134 FMT_32_BIT(V_038004_COLOR_11_11_10, 1),135 FMT_32_BIT(V_038004_COLOR_11_11_10_FLOAT, 1),136 FMT_32_BIT(V_038004_COLOR_2_10_10_10, 1),137 FMT_32_BIT(V_038004_COLOR_8_8_8_8, 1),138 FMT_32_BIT(V_038004_COLOR_10_10_10_2, 1),139 FMT_32_BIT(V_038004_FMT_5_9_9_9_SHAREDEXP, 0),140 FMT_32_BIT(V_038004_FMT_32_AS_8, 0),141 FMT_32_BIT(V_038004_FMT_32_AS_8_8, 0),142 143 /* 48-bit */144 FMT_48_BIT(V_038004_FMT_16_16_16),145 FMT_48_BIT(V_038004_FMT_16_16_16_FLOAT),146 147 /* 64-bit */148 FMT_64_BIT(V_038004_COLOR_X24_8_32_FLOAT, 1),149 FMT_64_BIT(V_038004_COLOR_32_32, 1),150 FMT_64_BIT(V_038004_COLOR_32_32_FLOAT, 1),151 FMT_64_BIT(V_038004_COLOR_16_16_16_16, 1),152 FMT_64_BIT(V_038004_COLOR_16_16_16_16_FLOAT, 1),153 154 FMT_96_BIT(V_038004_FMT_32_32_32),155 FMT_96_BIT(V_038004_FMT_32_32_32_FLOAT),156 157 /* 128-bit */158 FMT_128_BIT(V_038004_COLOR_32_32_32_32, 1),159 FMT_128_BIT(V_038004_COLOR_32_32_32_32_FLOAT, 1),160 161 [V_038004_FMT_GB_GR] = { 2, 1, 4, 0 },162 [V_038004_FMT_BG_RG] = { 2, 1, 4, 0 },163 164 /* block compressed formats */165 [V_038004_FMT_BC1] = { 4, 4, 8, 0 },166 [V_038004_FMT_BC2] = { 4, 4, 16, 0 },167 [V_038004_FMT_BC3] = { 4, 4, 16, 0 },168 [V_038004_FMT_BC4] = { 4, 4, 8, 0 },169 [V_038004_FMT_BC5] = { 4, 4, 16, 0},170 [V_038004_FMT_BC6] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */171 [V_038004_FMT_BC7] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */172 173 /* The other Evergreen formats */174 [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR},175};176 177bool r600_fmt_is_valid_color(u32 format)178{179 if (format >= ARRAY_SIZE(color_formats_table))180 return false;181 182 if (color_formats_table[format].valid_color)183 return true;184 185 return false;186}187 188bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family)189{190 if (format >= ARRAY_SIZE(color_formats_table))191 return false;192 193 if (family < color_formats_table[format].min_family)194 return false;195 196 if (color_formats_table[format].blockwidth > 0)197 return true;198 199 return false;200}201 202int r600_fmt_get_blocksize(u32 format)203{204 if (format >= ARRAY_SIZE(color_formats_table))205 return 0;206 207 return color_formats_table[format].blocksize;208}209 210int r600_fmt_get_nblocksx(u32 format, u32 w)211{212 unsigned bw;213 214 if (format >= ARRAY_SIZE(color_formats_table))215 return 0;216 217 bw = color_formats_table[format].blockwidth;218 if (bw == 0)219 return 0;220 221 return DIV_ROUND_UP(w, bw);222}223 224int r600_fmt_get_nblocksy(u32 format, u32 h)225{226 unsigned bh;227 228 if (format >= ARRAY_SIZE(color_formats_table))229 return 0;230 231 bh = color_formats_table[format].blockheight;232 if (bh == 0)233 return 0;234 235 return DIV_ROUND_UP(h, bh);236}237 238struct array_mode_checker {239 int array_mode;240 u32 group_size;241 u32 nbanks;242 u32 npipes;243 u32 nsamples;244 u32 blocksize;245};246 247/* returns alignment in pixels for pitch/height/depth and bytes for base */248static int r600_get_array_mode_alignment(struct array_mode_checker *values,249 u32 *pitch_align,250 u32 *height_align,251 u32 *depth_align,252 u64 *base_align)253{254 u32 tile_width = 8;255 u32 tile_height = 8;256 u32 macro_tile_width = values->nbanks;257 u32 macro_tile_height = values->npipes;258 u32 tile_bytes = tile_width * tile_height * values->blocksize * values->nsamples;259 u32 macro_tile_bytes = macro_tile_width * macro_tile_height * tile_bytes;260 261 switch (values->array_mode) {262 case ARRAY_LINEAR_GENERAL:263 /* technically tile_width/_height for pitch/height */264 *pitch_align = 1; /* tile_width */265 *height_align = 1; /* tile_height */266 *depth_align = 1;267 *base_align = 1;268 break;269 case ARRAY_LINEAR_ALIGNED:270 *pitch_align = max((u32)64, (u32)(values->group_size / values->blocksize));271 *height_align = 1;272 *depth_align = 1;273 *base_align = values->group_size;274 break;275 case ARRAY_1D_TILED_THIN1:276 *pitch_align = max((u32)tile_width,277 (u32)(values->group_size /278 (tile_height * values->blocksize * values->nsamples)));279 *height_align = tile_height;280 *depth_align = 1;281 *base_align = values->group_size;282 break;283 case ARRAY_2D_TILED_THIN1:284 *pitch_align = max((u32)macro_tile_width * tile_width,285 (u32)((values->group_size * values->nbanks) /286 (values->blocksize * values->nsamples * tile_width)));287 *height_align = macro_tile_height * tile_height;288 *depth_align = 1;289 *base_align = max(macro_tile_bytes,290 (*pitch_align) * values->blocksize * (*height_align) * values->nsamples);291 break;292 default:293 return -EINVAL;294 }295 296 return 0;297}298 299static void r600_cs_track_init(struct r600_cs_track *track)300{301 int i;302 303 /* assume DX9 mode */304 track->sq_config = DX9_CONSTS;305 for (i = 0; i < 8; i++) {306 track->cb_color_base_last[i] = 0;307 track->cb_color_size[i] = 0;308 track->cb_color_size_idx[i] = 0;309 track->cb_color_info[i] = 0;310 track->cb_color_view[i] = 0xFFFFFFFF;311 track->cb_color_bo[i] = NULL;312 track->cb_color_bo_offset[i] = 0xFFFFFFFF;313 track->cb_color_bo_mc[i] = 0xFFFFFFFF;314 track->cb_color_frag_bo[i] = NULL;315 track->cb_color_frag_offset[i] = 0xFFFFFFFF;316 track->cb_color_tile_bo[i] = NULL;317 track->cb_color_tile_offset[i] = 0xFFFFFFFF;318 track->cb_color_mask[i] = 0xFFFFFFFF;319 }320 track->is_resolve = false;321 track->nsamples = 16;322 track->log_nsamples = 4;323 track->cb_target_mask = 0xFFFFFFFF;324 track->cb_shader_mask = 0xFFFFFFFF;325 track->cb_dirty = true;326 track->db_bo = NULL;327 track->db_bo_mc = 0xFFFFFFFF;328 /* assume the biggest format and that htile is enabled */329 track->db_depth_info = 7 | (1 << 25);330 track->db_depth_view = 0xFFFFC000;331 track->db_depth_size = 0xFFFFFFFF;332 track->db_depth_size_idx = 0;333 track->db_depth_control = 0xFFFFFFFF;334 track->db_dirty = true;335 track->htile_bo = NULL;336 track->htile_offset = 0xFFFFFFFF;337 track->htile_surface = 0;338 339 for (i = 0; i < 4; i++) {340 track->vgt_strmout_size[i] = 0;341 track->vgt_strmout_bo[i] = NULL;342 track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;343 track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF;344 }345 track->streamout_dirty = true;346 track->sx_misc_kill_all_prims = false;347}348 349static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)350{351 struct r600_cs_track *track = p->track;352 u32 slice_tile_max, tmp;353 u32 height, height_align, pitch, pitch_align, depth_align;354 u64 base_offset, base_align;355 struct array_mode_checker array_check;356 volatile u32 *ib = p->ib.ptr;357 unsigned array_mode;358 u32 format;359 /* When resolve is used, the second colorbuffer has always 1 sample. */360 unsigned nsamples = track->is_resolve && i == 1 ? 1 : track->nsamples;361 362 format = G_0280A0_FORMAT(track->cb_color_info[i]);363 if (!r600_fmt_is_valid_color(format)) {364 dev_warn(p->dev, "%s:%d cb invalid format %d for %d (0x%08X)\n",365 __func__, __LINE__, format,366 i, track->cb_color_info[i]);367 return -EINVAL;368 }369 /* pitch in pixels */370 pitch = (G_028060_PITCH_TILE_MAX(track->cb_color_size[i]) + 1) * 8;371 slice_tile_max = G_028060_SLICE_TILE_MAX(track->cb_color_size[i]) + 1;372 slice_tile_max *= 64;373 height = slice_tile_max / pitch;374 if (height > 8192)375 height = 8192;376 array_mode = G_0280A0_ARRAY_MODE(track->cb_color_info[i]);377 378 base_offset = track->cb_color_bo_mc[i] + track->cb_color_bo_offset[i];379 array_check.array_mode = array_mode;380 array_check.group_size = track->group_size;381 array_check.nbanks = track->nbanks;382 array_check.npipes = track->npipes;383 array_check.nsamples = nsamples;384 array_check.blocksize = r600_fmt_get_blocksize(format);385 if (r600_get_array_mode_alignment(&array_check,386 &pitch_align, &height_align, &depth_align, &base_align)) {387 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,388 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,389 track->cb_color_info[i]);390 return -EINVAL;391 }392 switch (array_mode) {393 case V_0280A0_ARRAY_LINEAR_GENERAL:394 break;395 case V_0280A0_ARRAY_LINEAR_ALIGNED:396 break;397 case V_0280A0_ARRAY_1D_TILED_THIN1:398 /* avoid breaking userspace */399 if (height > 7)400 height &= ~0x7;401 break;402 case V_0280A0_ARRAY_2D_TILED_THIN1:403 break;404 default:405 dev_warn(p->dev, "%s invalid tiling %d for %d (0x%08X)\n", __func__,406 G_0280A0_ARRAY_MODE(track->cb_color_info[i]), i,407 track->cb_color_info[i]);408 return -EINVAL;409 }410 411 if (!IS_ALIGNED(pitch, pitch_align)) {412 dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n",413 __func__, __LINE__, pitch, pitch_align, array_mode);414 return -EINVAL;415 }416 if (!IS_ALIGNED(height, height_align)) {417 dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n",418 __func__, __LINE__, height, height_align, array_mode);419 return -EINVAL;420 }421 if (!IS_ALIGNED(base_offset, base_align)) {422 dev_warn(p->dev, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__, i,423 base_offset, base_align, array_mode);424 return -EINVAL;425 }426 427 /* check offset */428 tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) *429 r600_fmt_get_blocksize(format) * nsamples;430 switch (array_mode) {431 default:432 case V_0280A0_ARRAY_LINEAR_GENERAL:433 case V_0280A0_ARRAY_LINEAR_ALIGNED:434 tmp += track->cb_color_view[i] & 0xFF;435 break;436 case V_0280A0_ARRAY_1D_TILED_THIN1:437 case V_0280A0_ARRAY_2D_TILED_THIN1:438 tmp += G_028080_SLICE_MAX(track->cb_color_view[i]) * tmp;439 break;440 }441 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) {442 if (array_mode == V_0280A0_ARRAY_LINEAR_GENERAL) {443 /* the initial DDX does bad things with the CB size occasionally */444 /* it rounds up height too far for slice tile max but the BO is smaller */445 /* r600c,g also seem to flush at bad times in some apps resulting in446 * bogus values here. So for linear just allow anything to avoid breaking447 * broken userspace.448 */449 } else {450 dev_warn(p->dev, "%s offset[%d] %d %llu %d %lu too big (%d %d) (%d %d %d)\n",451 __func__, i, array_mode,452 track->cb_color_bo_offset[i], tmp,453 radeon_bo_size(track->cb_color_bo[i]),454 pitch, height, r600_fmt_get_nblocksx(format, pitch),455 r600_fmt_get_nblocksy(format, height),456 r600_fmt_get_blocksize(format));457 return -EINVAL;458 }459 }460 /* limit max tile */461 tmp = (height * pitch) >> 6;462 if (tmp < slice_tile_max)463 slice_tile_max = tmp;464 tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |465 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);466 ib[track->cb_color_size_idx[i]] = tmp;467 468 /* FMASK/CMASK */469 switch (G_0280A0_TILE_MODE(track->cb_color_info[i])) {470 case V_0280A0_TILE_DISABLE:471 break;472 case V_0280A0_FRAG_ENABLE:473 if (track->nsamples > 1) {474 uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]);475 /* the tile size is 8x8, but the size is in units of bits.476 * for bytes, do just * 8. */477 uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1);478 479 if (bytes + track->cb_color_frag_offset[i] >480 radeon_bo_size(track->cb_color_frag_bo[i])) {481 dev_warn(p->dev, "%s FMASK_TILE_MAX too large "482 "(tile_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",483 __func__, tile_max, bytes,484 track->cb_color_frag_offset[i],485 radeon_bo_size(track->cb_color_frag_bo[i]));486 return -EINVAL;487 }488 }489 fallthrough;490 case V_0280A0_CLEAR_ENABLE:491 {492 uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]);493 /* One block = 128x128 pixels, one 8x8 tile has 4 bits..494 * (128*128) / (8*8) / 2 = 128 bytes per block. */495 uint32_t bytes = (block_max + 1) * 128;496 497 if (bytes + track->cb_color_tile_offset[i] >498 radeon_bo_size(track->cb_color_tile_bo[i])) {499 dev_warn(p->dev, "%s CMASK_BLOCK_MAX too large "500 "(block_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",501 __func__, block_max, bytes,502 track->cb_color_tile_offset[i],503 radeon_bo_size(track->cb_color_tile_bo[i]));504 return -EINVAL;505 }506 break;507 }508 default:509 dev_warn(p->dev, "%s invalid tile mode\n", __func__);510 return -EINVAL;511 }512 return 0;513}514 515static int r600_cs_track_validate_db(struct radeon_cs_parser *p)516{517 struct r600_cs_track *track = p->track;518 u32 nviews, bpe, ntiles, slice_tile_max, tmp;519 u32 height_align, pitch_align, depth_align;520 u32 pitch = 8192;521 u32 height = 8192;522 u64 base_offset, base_align;523 struct array_mode_checker array_check;524 int array_mode;525 volatile u32 *ib = p->ib.ptr;526 527 528 if (track->db_bo == NULL) {529 dev_warn(p->dev, "z/stencil with no depth buffer\n");530 return -EINVAL;531 }532 switch (G_028010_FORMAT(track->db_depth_info)) {533 case V_028010_DEPTH_16:534 bpe = 2;535 break;536 case V_028010_DEPTH_X8_24:537 case V_028010_DEPTH_8_24:538 case V_028010_DEPTH_X8_24_FLOAT:539 case V_028010_DEPTH_8_24_FLOAT:540 case V_028010_DEPTH_32_FLOAT:541 bpe = 4;542 break;543 case V_028010_DEPTH_X24_8_32_FLOAT:544 bpe = 8;545 break;546 default:547 dev_warn(p->dev, "z/stencil with invalid format %d\n", G_028010_FORMAT(track->db_depth_info));548 return -EINVAL;549 }550 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {551 if (!track->db_depth_size_idx) {552 dev_warn(p->dev, "z/stencil buffer size not set\n");553 return -EINVAL;554 }555 tmp = radeon_bo_size(track->db_bo) - track->db_offset;556 tmp = (tmp / bpe) >> 6;557 if (!tmp) {558 dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %ld)\n",559 track->db_depth_size, bpe, track->db_offset,560 radeon_bo_size(track->db_bo));561 return -EINVAL;562 }563 ib[track->db_depth_size_idx] = S_028000_SLICE_TILE_MAX(tmp - 1) | (track->db_depth_size & 0x3FF);564 } else {565 /* pitch in pixels */566 pitch = (G_028000_PITCH_TILE_MAX(track->db_depth_size) + 1) * 8;567 slice_tile_max = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;568 slice_tile_max *= 64;569 height = slice_tile_max / pitch;570 if (height > 8192)571 height = 8192;572 base_offset = track->db_bo_mc + track->db_offset;573 array_mode = G_028010_ARRAY_MODE(track->db_depth_info);574 array_check.array_mode = array_mode;575 array_check.group_size = track->group_size;576 array_check.nbanks = track->nbanks;577 array_check.npipes = track->npipes;578 array_check.nsamples = track->nsamples;579 array_check.blocksize = bpe;580 if (r600_get_array_mode_alignment(&array_check,581 &pitch_align, &height_align, &depth_align, &base_align)) {582 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,583 G_028010_ARRAY_MODE(track->db_depth_info),584 track->db_depth_info);585 return -EINVAL;586 }587 switch (array_mode) {588 case V_028010_ARRAY_1D_TILED_THIN1:589 /* don't break userspace */590 height &= ~0x7;591 break;592 case V_028010_ARRAY_2D_TILED_THIN1:593 break;594 default:595 dev_warn(p->dev, "%s invalid tiling %d (0x%08X)\n", __func__,596 G_028010_ARRAY_MODE(track->db_depth_info),597 track->db_depth_info);598 return -EINVAL;599 }600 601 if (!IS_ALIGNED(pitch, pitch_align)) {602 dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n",603 __func__, __LINE__, pitch, pitch_align, array_mode);604 return -EINVAL;605 }606 if (!IS_ALIGNED(height, height_align)) {607 dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n",608 __func__, __LINE__, height, height_align, array_mode);609 return -EINVAL;610 }611 if (!IS_ALIGNED(base_offset, base_align)) {612 dev_warn(p->dev, "%s offset 0x%llx, 0x%llx, %d not aligned\n", __func__,613 base_offset, base_align, array_mode);614 return -EINVAL;615 }616 617 ntiles = G_028000_SLICE_TILE_MAX(track->db_depth_size) + 1;618 nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1;619 tmp = ntiles * bpe * 64 * nviews * track->nsamples;620 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) {621 dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n",622 array_mode,623 track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset,624 radeon_bo_size(track->db_bo));625 return -EINVAL;626 }627 }628 629 /* hyperz */630 if (G_028010_TILE_SURFACE_ENABLE(track->db_depth_info)) {631 unsigned long size;632 unsigned nbx, nby;633 634 if (track->htile_bo == NULL) {635 dev_warn(p->dev, "%s:%d htile enabled without htile surface 0x%08x\n",636 __func__, __LINE__, track->db_depth_info);637 return -EINVAL;638 }639 if ((track->db_depth_size & 0xFFFFFC00) == 0xFFFFFC00) {640 dev_warn(p->dev, "%s:%d htile can't be enabled with bogus db_depth_size 0x%08x\n",641 __func__, __LINE__, track->db_depth_size);642 return -EINVAL;643 }644 645 nbx = pitch;646 nby = height;647 if (G_028D24_LINEAR(track->htile_surface)) {648 /* nbx must be 16 htiles aligned == 16 * 8 pixel aligned */649 nbx = round_up(nbx, 16 * 8);650 /* nby is npipes htiles aligned == npipes * 8 pixel aligned */651 nby = round_up(nby, track->npipes * 8);652 } else {653 /* always assume 8x8 htile */654 /* align is htile align * 8, htile align vary according to655 * number of pipe and tile width and nby656 */657 switch (track->npipes) {658 case 8:659 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/660 nbx = round_up(nbx, 64 * 8);661 nby = round_up(nby, 64 * 8);662 break;663 case 4:664 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/665 nbx = round_up(nbx, 64 * 8);666 nby = round_up(nby, 32 * 8);667 break;668 case 2:669 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/670 nbx = round_up(nbx, 32 * 8);671 nby = round_up(nby, 32 * 8);672 break;673 case 1:674 /* HTILE_WIDTH = 8 & HTILE_HEIGHT = 8*/675 nbx = round_up(nbx, 32 * 8);676 nby = round_up(nby, 16 * 8);677 break;678 default:679 dev_warn(p->dev, "%s:%d invalid num pipes %d\n",680 __func__, __LINE__, track->npipes);681 return -EINVAL;682 }683 }684 /* compute number of htile */685 nbx = nbx >> 3;686 nby = nby >> 3;687 /* size must be aligned on npipes * 2K boundary */688 size = roundup(nbx * nby * 4, track->npipes * (2 << 10));689 size += track->htile_offset;690 691 if (size > radeon_bo_size(track->htile_bo)) {692 dev_warn(p->dev, "%s:%d htile surface too small %ld for %ld (%d %d)\n",693 __func__, __LINE__, radeon_bo_size(track->htile_bo),694 size, nbx, nby);695 return -EINVAL;696 }697 }698 699 track->db_dirty = false;700 return 0;701}702 703static int r600_cs_track_check(struct radeon_cs_parser *p)704{705 struct r600_cs_track *track = p->track;706 u32 tmp;707 int r, i;708 709 /* on legacy kernel we don't perform advanced check */710 if (p->rdev == NULL)711 return 0;712 713 /* check streamout */714 if (track->streamout_dirty && track->vgt_strmout_en) {715 for (i = 0; i < 4; i++) {716 if (track->vgt_strmout_buffer_en & (1 << i)) {717 if (track->vgt_strmout_bo[i]) {718 u64 offset = (u64)track->vgt_strmout_bo_offset[i] +719 (u64)track->vgt_strmout_size[i];720 if (offset > radeon_bo_size(track->vgt_strmout_bo[i])) {721 DRM_ERROR("streamout %d bo too small: 0x%llx, 0x%lx\n",722 i, offset,723 radeon_bo_size(track->vgt_strmout_bo[i]));724 return -EINVAL;725 }726 } else {727 dev_warn(p->dev, "No buffer for streamout %d\n", i);728 return -EINVAL;729 }730 }731 }732 track->streamout_dirty = false;733 }734 735 if (track->sx_misc_kill_all_prims)736 return 0;737 738 /* check that we have a cb for each enabled target, we don't check739 * shader_mask because it seems mesa isn't always setting it :(740 */741 if (track->cb_dirty) {742 tmp = track->cb_target_mask;743 744 /* We must check both colorbuffers for RESOLVE. */745 if (track->is_resolve) {746 tmp |= 0xff;747 }748 749 for (i = 0; i < 8; i++) {750 u32 format = G_0280A0_FORMAT(track->cb_color_info[i]);751 752 if (format != V_0280A0_COLOR_INVALID &&753 (tmp >> (i * 4)) & 0xF) {754 /* at least one component is enabled */755 if (track->cb_color_bo[i] == NULL) {756 dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",757 __func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);758 return -EINVAL;759 }760 /* perform rewrite of CB_COLOR[0-7]_SIZE */761 r = r600_cs_track_validate_cb(p, i);762 if (r)763 return r;764 }765 }766 track->cb_dirty = false;767 }768 769 /* Check depth buffer */770 if (track->db_dirty &&771 G_028010_FORMAT(track->db_depth_info) != V_028010_DEPTH_INVALID &&772 (G_028800_STENCIL_ENABLE(track->db_depth_control) ||773 G_028800_Z_ENABLE(track->db_depth_control))) {774 r = r600_cs_track_validate_db(p);775 if (r)776 return r;777 }778 779 return 0;780}781 782/**783 * r600_cs_packet_parse_vline() - parse userspace VLINE packet784 * @p: parser structure holding parsing context.785 *786 * This is an R600-specific function for parsing VLINE packets.787 * Real work is done by r600_cs_common_vline_parse function.788 * Here we just set up ASIC-specific register table and call789 * the common implementation function.790 */791static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)792{793 static uint32_t vline_start_end[2] = {AVIVO_D1MODE_VLINE_START_END,794 AVIVO_D2MODE_VLINE_START_END};795 static uint32_t vline_status[2] = {AVIVO_D1MODE_VLINE_STATUS,796 AVIVO_D2MODE_VLINE_STATUS};797 798 return r600_cs_common_vline_parse(p, vline_start_end, vline_status);799}800 801/**802 * r600_cs_common_vline_parse() - common vline parser803 * @p: parser structure holding parsing context.804 * @vline_start_end: table of vline_start_end registers805 * @vline_status: table of vline_status registers806 *807 * Userspace sends a special sequence for VLINE waits.808 * PACKET0 - VLINE_START_END + value809 * PACKET3 - WAIT_REG_MEM poll vline status reg810 * RELOC (P3) - crtc_id in reloc.811 *812 * This function parses this and relocates the VLINE START END813 * and WAIT_REG_MEM packets to the correct crtc.814 * It also detects a switched off crtc and nulls out the815 * wait in that case. This function is common for all ASICs that816 * are R600 and newer. The parsing algorithm is the same, and only817 * differs in which registers are used.818 *819 * Caller is the ASIC-specific function which passes the parser820 * context and ASIC-specific register table821 */822int r600_cs_common_vline_parse(struct radeon_cs_parser *p,823 uint32_t *vline_start_end,824 uint32_t *vline_status)825{826 struct drm_crtc *crtc;827 struct radeon_crtc *radeon_crtc;828 struct radeon_cs_packet p3reloc, wait_reg_mem;829 int crtc_id;830 int r;831 uint32_t header, h_idx, reg, wait_reg_mem_info;832 volatile uint32_t *ib;833 834 ib = p->ib.ptr;835 836 /* parse the WAIT_REG_MEM */837 r = radeon_cs_packet_parse(p, &wait_reg_mem, p->idx);838 if (r)839 return r;840 841 /* check its a WAIT_REG_MEM */842 if (wait_reg_mem.type != RADEON_PACKET_TYPE3 ||843 wait_reg_mem.opcode != PACKET3_WAIT_REG_MEM) {844 DRM_ERROR("vline wait missing WAIT_REG_MEM segment\n");845 return -EINVAL;846 }847 848 wait_reg_mem_info = radeon_get_ib_value(p, wait_reg_mem.idx + 1);849 /* bit 4 is reg (0) or mem (1) */850 if (wait_reg_mem_info & 0x10) {851 DRM_ERROR("vline WAIT_REG_MEM waiting on MEM instead of REG\n");852 return -EINVAL;853 }854 /* bit 8 is me (0) or pfp (1) */855 if (wait_reg_mem_info & 0x100) {856 DRM_ERROR("vline WAIT_REG_MEM waiting on PFP instead of ME\n");857 return -EINVAL;858 }859 /* waiting for value to be equal */860 if ((wait_reg_mem_info & 0x7) != 0x3) {861 DRM_ERROR("vline WAIT_REG_MEM function not equal\n");862 return -EINVAL;863 }864 if ((radeon_get_ib_value(p, wait_reg_mem.idx + 2) << 2) != vline_status[0]) {865 DRM_ERROR("vline WAIT_REG_MEM bad reg\n");866 return -EINVAL;867 }868 869 if (radeon_get_ib_value(p, wait_reg_mem.idx + 5) != RADEON_VLINE_STAT) {870 DRM_ERROR("vline WAIT_REG_MEM bad bit mask\n");871 return -EINVAL;872 }873 874 /* jump over the NOP */875 r = radeon_cs_packet_parse(p, &p3reloc, p->idx + wait_reg_mem.count + 2);876 if (r)877 return r;878 879 h_idx = p->idx - 2;880 p->idx += wait_reg_mem.count + 2;881 p->idx += p3reloc.count + 2;882 883 header = radeon_get_ib_value(p, h_idx);884 crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);885 reg = R600_CP_PACKET0_GET_REG(header);886 887 crtc = drm_crtc_find(rdev_to_drm(p->rdev), p->filp, crtc_id);888 if (!crtc) {889 DRM_ERROR("cannot find crtc %d\n", crtc_id);890 return -ENOENT;891 }892 radeon_crtc = to_radeon_crtc(crtc);893 crtc_id = radeon_crtc->crtc_id;894 895 if (!crtc->enabled) {896 /* CRTC isn't enabled - we need to nop out the WAIT_REG_MEM */897 ib[h_idx + 2] = PACKET2(0);898 ib[h_idx + 3] = PACKET2(0);899 ib[h_idx + 4] = PACKET2(0);900 ib[h_idx + 5] = PACKET2(0);901 ib[h_idx + 6] = PACKET2(0);902 ib[h_idx + 7] = PACKET2(0);903 ib[h_idx + 8] = PACKET2(0);904 } else if (reg == vline_start_end[0]) {905 header &= ~R600_CP_PACKET0_REG_MASK;906 header |= vline_start_end[crtc_id] >> 2;907 ib[h_idx] = header;908 ib[h_idx + 4] = vline_status[crtc_id] >> 2;909 } else {910 DRM_ERROR("unknown crtc reloc\n");911 return -EINVAL;912 }913 return 0;914}915 916static int r600_packet0_check(struct radeon_cs_parser *p,917 struct radeon_cs_packet *pkt,918 unsigned idx, unsigned reg)919{920 int r;921 922 switch (reg) {923 case AVIVO_D1MODE_VLINE_START_END:924 r = r600_cs_packet_parse_vline(p);925 if (r) {926 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",927 idx, reg);928 return r;929 }930 break;931 default:932 pr_err("Forbidden register 0x%04X in cs at %d\n", reg, idx);933 return -EINVAL;934 }935 return 0;936}937 938static int r600_cs_parse_packet0(struct radeon_cs_parser *p,939 struct radeon_cs_packet *pkt)940{941 unsigned reg, i;942 unsigned idx;943 int r;944 945 idx = pkt->idx + 1;946 reg = pkt->reg;947 for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {948 r = r600_packet0_check(p, pkt, idx, reg);949 if (r) {950 return r;951 }952 }953 return 0;954}955 956/**957 * r600_cs_check_reg() - check if register is authorized or not958 * @p: parser structure holding parsing context959 * @reg: register we are testing960 * @idx: index into the cs buffer961 *962 * This function will test against r600_reg_safe_bm and return 0963 * if register is safe. If register is not flag as safe this function964 * will test it against a list of register needing special handling.965 */966static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)967{968 struct r600_cs_track *track = (struct r600_cs_track *)p->track;969 struct radeon_bo_list *reloc;970 u32 m, i, tmp, *ib;971 int r;972 973 i = (reg >> 7);974 if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {975 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);976 return -EINVAL;977 }978 m = 1 << ((reg >> 2) & 31);979 if (!(r600_reg_safe_bm[i] & m))980 return 0;981 ib = p->ib.ptr;982 switch (reg) {983 /* force following reg to 0 in an attempt to disable out buffer984 * which will need us to better understand how it works to perform985 * security check on it (Jerome)986 */987 case R_0288A8_SQ_ESGS_RING_ITEMSIZE:988 case R_008C44_SQ_ESGS_RING_SIZE:989 case R_0288B0_SQ_ESTMP_RING_ITEMSIZE:990 case R_008C54_SQ_ESTMP_RING_SIZE:991 case R_0288C0_SQ_FBUF_RING_ITEMSIZE:992 case R_008C74_SQ_FBUF_RING_SIZE:993 case R_0288B4_SQ_GSTMP_RING_ITEMSIZE:994 case R_008C5C_SQ_GSTMP_RING_SIZE:995 case R_0288AC_SQ_GSVS_RING_ITEMSIZE:996 case R_008C4C_SQ_GSVS_RING_SIZE:997 case R_0288BC_SQ_PSTMP_RING_ITEMSIZE:998 case R_008C6C_SQ_PSTMP_RING_SIZE:999 case R_0288C4_SQ_REDUC_RING_ITEMSIZE:1000 case R_008C7C_SQ_REDUC_RING_SIZE:1001 case R_0288B8_SQ_VSTMP_RING_ITEMSIZE:1002 case R_008C64_SQ_VSTMP_RING_SIZE:1003 case R_0288C8_SQ_GS_VERT_ITEMSIZE:1004 /* get value to populate the IB don't remove */1005 /*tmp =radeon_get_ib_value(p, idx);1006 ib[idx] = 0;*/1007 break;1008 case SQ_ESGS_RING_BASE:1009 case SQ_GSVS_RING_BASE:1010 case SQ_ESTMP_RING_BASE:1011 case SQ_GSTMP_RING_BASE:1012 case SQ_PSTMP_RING_BASE:1013 case SQ_VSTMP_RING_BASE:1014 r = radeon_cs_packet_next_reloc(p, &reloc, 0);1015 if (r) {1016 dev_warn(p->dev, "bad SET_CONTEXT_REG "1017 "0x%04X\n", reg);1018 return -EINVAL;1019 }1020 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);1021 break;1022 case SQ_CONFIG:1023 track->sq_config = radeon_get_ib_value(p, idx);1024 break;1025 case R_028800_DB_DEPTH_CONTROL:1026 track->db_depth_control = radeon_get_ib_value(p, idx);1027 track->db_dirty = true;1028 break;1029 case R_028010_DB_DEPTH_INFO:1030 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&1031 radeon_cs_packet_next_is_pkt3_nop(p)) {1032 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);1033 if (r) {1034 dev_warn(p->dev, "bad SET_CONTEXT_REG "1035 "0x%04X\n", reg);1036 return -EINVAL;1037 }1038 track->db_depth_info = radeon_get_ib_value(p, idx);1039 ib[idx] &= C_028010_ARRAY_MODE;1040 track->db_depth_info &= C_028010_ARRAY_MODE;1041 if (reloc->tiling_flags & RADEON_TILING_MACRO) {1042 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);1043 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_2D_TILED_THIN1);1044 } else {1045 ib[idx] |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);1046 track->db_depth_info |= S_028010_ARRAY_MODE(V_028010_ARRAY_1D_TILED_THIN1);1047 }1048 } else {1049 track->db_depth_info = radeon_get_ib_value(p, idx);1050 }1051 track->db_dirty = true;1052 break;1053 case R_028004_DB_DEPTH_VIEW:1054 track->db_depth_view = radeon_get_ib_value(p, idx);1055 track->db_dirty = true;1056 break;1057 case R_028000_DB_DEPTH_SIZE:1058 track->db_depth_size = radeon_get_ib_value(p, idx);1059 track->db_depth_size_idx = idx;1060 track->db_dirty = true;1061 break;1062 case R_028AB0_VGT_STRMOUT_EN:1063 track->vgt_strmout_en = radeon_get_ib_value(p, idx);1064 track->streamout_dirty = true;1065 break;1066 case R_028B20_VGT_STRMOUT_BUFFER_EN:1067 track->vgt_strmout_buffer_en = radeon_get_ib_value(p, idx);1068 track->streamout_dirty = true;1069 break;1070 case VGT_STRMOUT_BUFFER_BASE_0:1071 case VGT_STRMOUT_BUFFER_BASE_1:1072 case VGT_STRMOUT_BUFFER_BASE_2:1073 case VGT_STRMOUT_BUFFER_BASE_3:1074 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);1075 if (r) {1076 dev_warn(p->dev, "bad SET_CONTEXT_REG "1077 "0x%04X\n", reg);1078 return -EINVAL;1079 }1080 tmp = (reg - VGT_STRMOUT_BUFFER_BASE_0) / 16;1081 track->vgt_strmout_bo_offset[tmp] = radeon_get_ib_value(p, idx) << 8;1082 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);1083 track->vgt_strmout_bo[tmp] = reloc->robj;1084 track->vgt_strmout_bo_mc[tmp] = reloc->gpu_offset;1085 track->streamout_dirty = true;1086 break;1087 case VGT_STRMOUT_BUFFER_SIZE_0:1088 case VGT_STRMOUT_BUFFER_SIZE_1:1089 case VGT_STRMOUT_BUFFER_SIZE_2:1090 case VGT_STRMOUT_BUFFER_SIZE_3:1091 tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;1092 /* size in register is DWs, convert to bytes */1093 track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;1094 track->streamout_dirty = true;1095 break;1096 case CP_COHER_BASE:1097 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);1098 if (r) {1099 dev_warn(p->dev, "missing reloc for CP_COHER_BASE "1100 "0x%04X\n", reg);1101 return -EINVAL;1102 }1103 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);1104 break;1105 case R_028238_CB_TARGET_MASK:1106 track->cb_target_mask = radeon_get_ib_value(p, idx);1107 track->cb_dirty = true;1108 break;1109 case R_02823C_CB_SHADER_MASK:1110 track->cb_shader_mask = radeon_get_ib_value(p, idx);1111 break;1112 case R_028C04_PA_SC_AA_CONFIG:1113 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));1114 track->log_nsamples = tmp;1115 track->nsamples = 1 << tmp;1116 track->cb_dirty = true;1117 break;1118 case R_028808_CB_COLOR_CONTROL:1119 tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx));1120 track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX;1121 track->cb_dirty = true;1122 break;1123 case R_0280A0_CB_COLOR0_INFO:1124 case R_0280A4_CB_COLOR1_INFO:1125 case R_0280A8_CB_COLOR2_INFO:1126 case R_0280AC_CB_COLOR3_INFO:1127 case R_0280B0_CB_COLOR4_INFO:1128 case R_0280B4_CB_COLOR5_INFO:1129 case R_0280B8_CB_COLOR6_INFO:1130 case R_0280BC_CB_COLOR7_INFO:1131 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS) &&1132 radeon_cs_packet_next_is_pkt3_nop(p)) {1133 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);1134 if (r) {1135 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);1136 return -EINVAL;1137 }1138 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;1139 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);1140 if (reloc->tiling_flags & RADEON_TILING_MACRO) {1141 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);1142 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_2D_TILED_THIN1);1143 } else if (reloc->tiling_flags & RADEON_TILING_MICRO) {1144 ib[idx] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);1145 track->cb_color_info[tmp] |= S_0280A0_ARRAY_MODE(V_0280A0_ARRAY_1D_TILED_THIN1);1146 }1147 } else {1148 tmp = (reg - R_0280A0_CB_COLOR0_INFO) / 4;1149 track->cb_color_info[tmp] = radeon_get_ib_value(p, idx);1150 }1151 track->cb_dirty = true;1152 break;1153 case R_028080_CB_COLOR0_VIEW:1154 case R_028084_CB_COLOR1_VIEW:1155 case R_028088_CB_COLOR2_VIEW:1156 case R_02808C_CB_COLOR3_VIEW:1157 case R_028090_CB_COLOR4_VIEW:1158 case R_028094_CB_COLOR5_VIEW:1159 case R_028098_CB_COLOR6_VIEW:1160 case R_02809C_CB_COLOR7_VIEW:1161 tmp = (reg - R_028080_CB_COLOR0_VIEW) / 4;1162 track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);1163 track->cb_dirty = true;1164 break;1165 case R_028060_CB_COLOR0_SIZE:1166 case R_028064_CB_COLOR1_SIZE:1167 case R_028068_CB_COLOR2_SIZE:1168 case R_02806C_CB_COLOR3_SIZE:1169 case R_028070_CB_COLOR4_SIZE:1170 case R_028074_CB_COLOR5_SIZE:1171 case R_028078_CB_COLOR6_SIZE:1172 case R_02807C_CB_COLOR7_SIZE:1173 tmp = (reg - R_028060_CB_COLOR0_SIZE) / 4;1174 track->cb_color_size[tmp] = radeon_get_ib_value(p, idx);1175 track->cb_color_size_idx[tmp] = idx;1176 track->cb_dirty = true;1177 break;1178 /* This register were added late, there is userspace1179 * which does provide relocation for those but set1180 * 0 offset. In order to avoid breaking old userspace1181 * we detect this and set address to point to last1182 * CB_COLOR0_BASE, note that if userspace doesn't set1183 * CB_COLOR0_BASE before this register we will report1184 * error. Old userspace always set CB_COLOR0_BASE1185 * before any of this.1186 */1187 case R_0280E0_CB_COLOR0_FRAG:1188 case R_0280E4_CB_COLOR1_FRAG:1189 case R_0280E8_CB_COLOR2_FRAG:1190 case R_0280EC_CB_COLOR3_FRAG:1191 case R_0280F0_CB_COLOR4_FRAG:1192 case R_0280F4_CB_COLOR5_FRAG:1193 case R_0280F8_CB_COLOR6_FRAG:1194 case R_0280FC_CB_COLOR7_FRAG:1195 tmp = (reg - R_0280E0_CB_COLOR0_FRAG) / 4;1196 if (!radeon_cs_packet_next_is_pkt3_nop(p)) {1197 if (!track->cb_color_base_last[tmp]) {1198 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);1199 return -EINVAL;1200 }1201 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];1202 track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp];1203 ib[idx] = track->cb_color_base_last[tmp];1204 } else {1205 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);1206 if (r) {1207 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);1208 return -EINVAL;1209 }1210 track->cb_color_frag_bo[tmp] = reloc->robj;1211 track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8;1212 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);1213 }1214 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {1215 track->cb_dirty = true;1216 }1217 break;1218 case R_0280C0_CB_COLOR0_TILE:1219 case R_0280C4_CB_COLOR1_TILE:1220 case R_0280C8_CB_COLOR2_TILE:1221 case R_0280CC_CB_COLOR3_TILE:1222 case R_0280D0_CB_COLOR4_TILE:1223 case R_0280D4_CB_COLOR5_TILE:1224 case R_0280D8_CB_COLOR6_TILE:1225 case R_0280DC_CB_COLOR7_TILE:1226 tmp = (reg - R_0280C0_CB_COLOR0_TILE) / 4;1227 if (!radeon_cs_packet_next_is_pkt3_nop(p)) {1228 if (!track->cb_color_base_last[tmp]) {1229 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);1230 return -EINVAL;1231 }1232 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];1233 track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp];1234 ib[idx] = track->cb_color_base_last[tmp];1235 } else {1236 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);1237 if (r) {1238 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);1239 return -EINVAL;1240 }1241 track->cb_color_tile_bo[tmp] = reloc->robj;1242 track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8;1243 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);1244 }1245 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {1246 track->cb_dirty = true;1247 }1248 break;1249 case R_028100_CB_COLOR0_MASK:1250 case R_028104_CB_COLOR1_MASK:1251 case R_028108_CB_COLOR2_MASK:1252 case R_02810C_CB_COLOR3_MASK:1253 case R_028110_CB_COLOR4_MASK:1254 case R_028114_CB_COLOR5_MASK:1255 case R_028118_CB_COLOR6_MASK:1256 case R_02811C_CB_COLOR7_MASK:1257 tmp = (reg - R_028100_CB_COLOR0_MASK) / 4;1258 track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx);1259 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {1260 track->cb_dirty = true;1261 }1262 break;1263 case CB_COLOR0_BASE:1264 case CB_COLOR1_BASE:1265 case CB_COLOR2_BASE:1266 case CB_COLOR3_BASE:1267 case CB_COLOR4_BASE:1268 case CB_COLOR5_BASE:1269 case CB_COLOR6_BASE:1270 case CB_COLOR7_BASE:1271 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);1272 if (r) {1273 dev_warn(p->dev, "bad SET_CONTEXT_REG "1274 "0x%04X\n", reg);1275 return -EINVAL;1276 }1277 tmp = (reg - CB_COLOR0_BASE) / 4;1278 track->cb_color_bo_offset[tmp] = (u64)radeon_get_ib_value(p, idx) << 8;1279 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);1280 track->cb_color_base_last[tmp] = ib[idx];1281 track->cb_color_bo[tmp] = reloc->robj;1282 track->cb_color_bo_mc[tmp] = reloc->gpu_offset;1283 track->cb_dirty = true;1284 break;1285 case DB_DEPTH_BASE:1286 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);1287 if (r) {1288 dev_warn(p->dev, "bad SET_CONTEXT_REG "1289 "0x%04X\n", reg);1290 return -EINVAL;1291 }1292 track->db_offset = radeon_get_ib_value(p, idx) << 8;1293 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);1294 track->db_bo = reloc->robj;1295 track->db_bo_mc = reloc->gpu_offset;1296 track->db_dirty = true;1297 break;1298 case DB_HTILE_DATA_BASE:1299 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);1300 if (r) {1301 dev_warn(p->dev, "bad SET_CONTEXT_REG "1302 "0x%04X\n", reg);1303 return -EINVAL;1304 }1305 track->htile_offset = (u64)radeon_get_ib_value(p, idx) << 8;1306 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);1307 track->htile_bo = reloc->robj;1308 track->db_dirty = true;1309 break;1310 case DB_HTILE_SURFACE:1311 track->htile_surface = radeon_get_ib_value(p, idx);1312 /* force 8x8 htile width and height */1313 ib[idx] |= 3;1314 track->db_dirty = true;1315 break;1316 case SQ_PGM_START_FS:1317 case SQ_PGM_START_ES:1318 case SQ_PGM_START_VS:1319 case SQ_PGM_START_GS:1320 case SQ_PGM_START_PS:1321 case SQ_ALU_CONST_CACHE_GS_0:1322 case SQ_ALU_CONST_CACHE_GS_1:1323 case SQ_ALU_CONST_CACHE_GS_2:1324 case SQ_ALU_CONST_CACHE_GS_3:1325 case SQ_ALU_CONST_CACHE_GS_4:1326 case SQ_ALU_CONST_CACHE_GS_5:1327 case SQ_ALU_CONST_CACHE_GS_6:1328 case SQ_ALU_CONST_CACHE_GS_7:1329 case SQ_ALU_CONST_CACHE_GS_8:1330 case SQ_ALU_CONST_CACHE_GS_9:1331 case SQ_ALU_CONST_CACHE_GS_10:1332 case SQ_ALU_CONST_CACHE_GS_11:1333 case SQ_ALU_CONST_CACHE_GS_12:1334 case SQ_ALU_CONST_CACHE_GS_13:1335 case SQ_ALU_CONST_CACHE_GS_14:1336 case SQ_ALU_CONST_CACHE_GS_15:1337 case SQ_ALU_CONST_CACHE_PS_0:1338 case SQ_ALU_CONST_CACHE_PS_1:1339 case SQ_ALU_CONST_CACHE_PS_2:1340 case SQ_ALU_CONST_CACHE_PS_3:1341 case SQ_ALU_CONST_CACHE_PS_4:1342 case SQ_ALU_CONST_CACHE_PS_5:1343 case SQ_ALU_CONST_CACHE_PS_6:1344 case SQ_ALU_CONST_CACHE_PS_7:1345 case SQ_ALU_CONST_CACHE_PS_8:1346 case SQ_ALU_CONST_CACHE_PS_9:1347 case SQ_ALU_CONST_CACHE_PS_10:1348 case SQ_ALU_CONST_CACHE_PS_11:1349 case SQ_ALU_CONST_CACHE_PS_12:1350 case SQ_ALU_CONST_CACHE_PS_13:1351 case SQ_ALU_CONST_CACHE_PS_14:1352 case SQ_ALU_CONST_CACHE_PS_15:1353 case SQ_ALU_CONST_CACHE_VS_0:1354 case SQ_ALU_CONST_CACHE_VS_1:1355 case SQ_ALU_CONST_CACHE_VS_2:1356 case SQ_ALU_CONST_CACHE_VS_3:1357 case SQ_ALU_CONST_CACHE_VS_4:1358 case SQ_ALU_CONST_CACHE_VS_5:1359 case SQ_ALU_CONST_CACHE_VS_6:1360 case SQ_ALU_CONST_CACHE_VS_7:1361 case SQ_ALU_CONST_CACHE_VS_8:1362 case SQ_ALU_CONST_CACHE_VS_9:1363 case SQ_ALU_CONST_CACHE_VS_10:1364 case SQ_ALU_CONST_CACHE_VS_11:1365 case SQ_ALU_CONST_CACHE_VS_12:1366 case SQ_ALU_CONST_CACHE_VS_13:1367 case SQ_ALU_CONST_CACHE_VS_14:1368 case SQ_ALU_CONST_CACHE_VS_15:1369 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);1370 if (r) {1371 dev_warn(p->dev, "bad SET_CONTEXT_REG "1372 "0x%04X\n", reg);1373 return -EINVAL;1374 }1375 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);1376 break;1377 case SX_MEMORY_EXPORT_BASE:1378 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);1379 if (r) {1380 dev_warn(p->dev, "bad SET_CONFIG_REG "1381 "0x%04X\n", reg);1382 return -EINVAL;1383 }1384 ib[idx] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);1385 break;1386 case SX_MISC:1387 track->sx_misc_kill_all_prims = (radeon_get_ib_value(p, idx) & 0x1) != 0;1388 break;1389 default:1390 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);1391 return -EINVAL;1392 }1393 return 0;1394}1395 1396unsigned r600_mip_minify(unsigned size, unsigned level)1397{1398 unsigned val;1399 1400 val = max(1U, size >> level);1401 if (level > 0)1402 val = roundup_pow_of_two(val);1403 return val;1404}1405 1406static void r600_texture_size(unsigned nfaces, unsigned blevel, unsigned llevel,1407 unsigned w0, unsigned h0, unsigned d0, unsigned nsamples, unsigned format,1408 unsigned block_align, unsigned height_align, unsigned base_align,1409 unsigned *l0_size, unsigned *mipmap_size)1410{1411 unsigned offset, i, level;1412 unsigned width, height, depth, size;1413 unsigned blocksize;1414 unsigned nbx, nby;1415 unsigned nlevels = llevel - blevel + 1;1416 1417 *l0_size = -1;1418 blocksize = r600_fmt_get_blocksize(format);1419 1420 w0 = r600_mip_minify(w0, 0);1421 h0 = r600_mip_minify(h0, 0);1422 d0 = r600_mip_minify(d0, 0);1423 for(i = 0, offset = 0, level = blevel; i < nlevels; i++, level++) {1424 width = r600_mip_minify(w0, i);1425 nbx = r600_fmt_get_nblocksx(format, width);1426 1427 nbx = round_up(nbx, block_align);1428 1429 height = r600_mip_minify(h0, i);1430 nby = r600_fmt_get_nblocksy(format, height);1431 nby = round_up(nby, height_align);1432 1433 depth = r600_mip_minify(d0, i);1434 1435 size = nbx * nby * blocksize * nsamples;1436 if (nfaces)1437 size *= nfaces;1438 else1439 size *= depth;1440 1441 if (i == 0)1442 *l0_size = size;1443 1444 if (i == 0 || i == 1)1445 offset = round_up(offset, base_align);1446 1447 offset += size;1448 }1449 *mipmap_size = offset;1450 if (llevel == 0)1451 *mipmap_size = *l0_size;1452 if (!blevel)1453 *mipmap_size -= *l0_size;1454}1455 1456/**1457 * r600_check_texture_resource() - check if register is authorized or not1458 * @p: parser structure holding parsing context1459 * @idx: index into the cs buffer1460 * @texture: texture's bo structure1461 * @mipmap: mipmap's bo structure1462 * @base_offset: base offset (used for error checking)1463 * @mip_offset: mip offset (used for error checking)1464 * @tiling_flags: tiling flags1465 *1466 * This function will check that the resource has valid field and that1467 * the texture and mipmap bo object are big enough to cover this resource.1468 */1469static int r600_check_texture_resource(struct radeon_cs_parser *p, u32 idx,1470 struct radeon_bo *texture,1471 struct radeon_bo *mipmap,1472 u64 base_offset,1473 u64 mip_offset,1474 u32 tiling_flags)1475{1476 struct r600_cs_track *track = p->track;1477 u32 dim, nfaces, llevel, blevel, w0, h0, d0;1478 u32 word0, word1, l0_size, mipmap_size, word2, word3, word4, word5;1479 u32 height_align, pitch, pitch_align, depth_align;1480 u32 barray, larray;1481 u64 base_align;1482 struct array_mode_checker array_check;1483 u32 format;1484 bool is_array;1485 1486 /* on legacy kernel we don't perform advanced check */1487 if (p->rdev == NULL)1488 return 0;1489 1490 /* convert to bytes */1491 base_offset <<= 8;1492 mip_offset <<= 8;1493 1494 word0 = radeon_get_ib_value(p, idx + 0);1495 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {1496 if (tiling_flags & RADEON_TILING_MACRO)1497 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);1498 else if (tiling_flags & RADEON_TILING_MICRO)1499 word0 |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);1500 }1501 word1 = radeon_get_ib_value(p, idx + 1);1502 word2 = radeon_get_ib_value(p, idx + 2) << 8;1503 word3 = radeon_get_ib_value(p, idx + 3) << 8;1504 word4 = radeon_get_ib_value(p, idx + 4);1505 word5 = radeon_get_ib_value(p, idx + 5);1506 dim = G_038000_DIM(word0);1507 w0 = G_038000_TEX_WIDTH(word0) + 1;1508 pitch = (G_038000_PITCH(word0) + 1) * 8;1509 h0 = G_038004_TEX_HEIGHT(word1) + 1;1510 d0 = G_038004_TEX_DEPTH(word1);1511 format = G_038004_DATA_FORMAT(word1);1512 blevel = G_038010_BASE_LEVEL(word4);1513 llevel = G_038014_LAST_LEVEL(word5);1514 /* pitch in texels */1515 array_check.array_mode = G_038000_TILE_MODE(word0);1516 array_check.group_size = track->group_size;1517 array_check.nbanks = track->nbanks;1518 array_check.npipes = track->npipes;1519 array_check.nsamples = 1;1520 array_check.blocksize = r600_fmt_get_blocksize(format);1521 nfaces = 1;1522 is_array = false;1523 switch (dim) {1524 case V_038000_SQ_TEX_DIM_1D:1525 case V_038000_SQ_TEX_DIM_2D:1526 case V_038000_SQ_TEX_DIM_3D:1527 break;1528 case V_038000_SQ_TEX_DIM_CUBEMAP:1529 if (p->family >= CHIP_RV770)1530 nfaces = 8;1531 else1532 nfaces = 6;1533 break;1534 case V_038000_SQ_TEX_DIM_1D_ARRAY:1535 case V_038000_SQ_TEX_DIM_2D_ARRAY:1536 is_array = true;1537 break;1538 case V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA:1539 is_array = true;1540 fallthrough;1541 case V_038000_SQ_TEX_DIM_2D_MSAA:1542 array_check.nsamples = 1 << llevel;1543 llevel = 0;1544 break;1545 default:1546 dev_warn(p->dev, "this kernel doesn't support %d texture dim\n", G_038000_DIM(word0));1547 return -EINVAL;1548 }1549 if (!r600_fmt_is_valid_texture(format, p->family)) {1550 dev_warn(p->dev, "%s:%d texture invalid format %d\n",1551 __func__, __LINE__, format);1552 return -EINVAL;1553 }1554 1555 if (r600_get_array_mode_alignment(&array_check,1556 &pitch_align, &height_align, &depth_align, &base_align)) {1557 dev_warn(p->dev, "%s:%d tex array mode (%d) invalid\n",1558 __func__, __LINE__, G_038000_TILE_MODE(word0));1559 return -EINVAL;1560 }1561 1562 /* XXX check height as well... */1563 1564 if (!IS_ALIGNED(pitch, pitch_align)) {1565 dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n",1566 __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0));1567 return -EINVAL;1568 }1569 if (!IS_ALIGNED(base_offset, base_align)) {1570 dev_warn(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n",1571 __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0));1572 return -EINVAL;1573 }1574 if (!IS_ALIGNED(mip_offset, base_align)) {1575 dev_warn(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n",1576 __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0));1577 return -EINVAL;1578 }1579 1580 if (blevel > llevel) {1581 dev_warn(p->dev, "texture blevel %d > llevel %d\n",1582 blevel, llevel);1583 }1584 if (is_array) {1585 barray = G_038014_BASE_ARRAY(word5);1586 larray = G_038014_LAST_ARRAY(word5);1587 1588 nfaces = larray - barray + 1;1589 }1590 r600_texture_size(nfaces, blevel, llevel, w0, h0, d0, array_check.nsamples, format,1591 pitch_align, height_align, base_align,1592 &l0_size, &mipmap_size);1593 /* using get ib will give us the offset into the texture bo */1594 if ((l0_size + word2) > radeon_bo_size(texture)) {1595 dev_warn(p->dev, "texture bo too small ((%d %d) (%d %d) %d %d %d -> %d have %ld)\n",1596 w0, h0, pitch_align, height_align,1597 array_check.array_mode, format, word2,1598 l0_size, radeon_bo_size(texture));1599 dev_warn(p->dev, "alignments %d %d %d %lld\n", pitch, pitch_align, height_align, base_align);1600 return -EINVAL;1601 }1602 /* using get ib will give us the offset into the mipmap bo */1603 if ((mipmap_size + word3) > radeon_bo_size(mipmap)) {1604 /*dev_warn(p->dev, "mipmap bo too small (%d %d %d %d %d %d -> %d have %ld)\n",1605 w0, h0, format, blevel, nlevels, word3, mipmap_size, radeon_bo_size(texture));*/1606 }1607 return 0;1608}1609 1610static bool r600_is_safe_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)1611{1612 u32 m, i;1613 1614 i = (reg >> 7);1615 if (i >= ARRAY_SIZE(r600_reg_safe_bm)) {1616 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);1617 return false;1618 }1619 m = 1 << ((reg >> 2) & 31);1620 if (!(r600_reg_safe_bm[i] & m))1621 return true;1622 dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);1623 return false;1624}1625 1626static int r600_packet3_check(struct radeon_cs_parser *p,1627 struct radeon_cs_packet *pkt)1628{1629 struct radeon_bo_list *reloc;1630 struct r600_cs_track *track;1631 volatile u32 *ib;1632 unsigned idx;1633 unsigned i;1634 unsigned start_reg, end_reg, reg;1635 int r;1636 u32 idx_value;1637 1638 track = (struct r600_cs_track *)p->track;1639 ib = p->ib.ptr;1640 idx = pkt->idx + 1;1641 idx_value = radeon_get_ib_value(p, idx);1642 1643 switch (pkt->opcode) {1644 case PACKET3_SET_PREDICATION:1645 {1646 int pred_op;1647 int tmp;1648 uint64_t offset;1649 1650 if (pkt->count != 1) {1651 DRM_ERROR("bad SET PREDICATION\n");1652 return -EINVAL;1653 }1654 1655 tmp = radeon_get_ib_value(p, idx + 1);1656 pred_op = (tmp >> 16) & 0x7;1657 1658 /* for the clear predicate operation */1659 if (pred_op == 0)1660 return 0;1661 1662 if (pred_op > 2) {1663 DRM_ERROR("bad SET PREDICATION operation %d\n", pred_op);1664 return -EINVAL;1665 }1666 1667 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);1668 if (r) {1669 DRM_ERROR("bad SET PREDICATION\n");1670 return -EINVAL;1671 }1672 1673 offset = reloc->gpu_offset +1674 (idx_value & 0xfffffff0) +1675 ((u64)(tmp & 0xff) << 32);1676 1677 ib[idx + 0] = offset;1678 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff);1679 }1680 break;1681 1682 case PACKET3_START_3D_CMDBUF:1683 if (p->family >= CHIP_RV770 || pkt->count) {1684 DRM_ERROR("bad START_3D\n");1685 return -EINVAL;1686 }1687 break;1688 case PACKET3_CONTEXT_CONTROL:1689 if (pkt->count != 1) {1690 DRM_ERROR("bad CONTEXT_CONTROL\n");1691 return -EINVAL;1692 }1693 break;1694 case PACKET3_INDEX_TYPE:1695 case PACKET3_NUM_INSTANCES:1696 if (pkt->count) {1697 DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES\n");1698 return -EINVAL;1699 }1700 break;1701 case PACKET3_DRAW_INDEX:1702 {1703 uint64_t offset;1704 if (pkt->count != 3) {1705 DRM_ERROR("bad DRAW_INDEX\n");1706 return -EINVAL;1707 }1708 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);1709 if (r) {1710 DRM_ERROR("bad DRAW_INDEX\n");1711 return -EINVAL;1712 }1713 1714 offset = reloc->gpu_offset +1715 idx_value +1716 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);1717 1718 ib[idx+0] = offset;1719 ib[idx+1] = upper_32_bits(offset) & 0xff;1720 1721 r = r600_cs_track_check(p);1722 if (r) {1723 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);1724 return r;1725 }1726 break;1727 }1728 case PACKET3_DRAW_INDEX_AUTO:1729 if (pkt->count != 1) {1730 DRM_ERROR("bad DRAW_INDEX_AUTO\n");1731 return -EINVAL;1732 }1733 r = r600_cs_track_check(p);1734 if (r) {1735 dev_warn(p->dev, "%s:%d invalid cmd stream %d\n", __func__, __LINE__, idx);1736 return r;1737 }1738 break;1739 case PACKET3_DRAW_INDEX_IMMD_BE:1740 case PACKET3_DRAW_INDEX_IMMD:1741 if (pkt->count < 2) {1742 DRM_ERROR("bad DRAW_INDEX_IMMD\n");1743 return -EINVAL;1744 }1745 r = r600_cs_track_check(p);1746 if (r) {1747 dev_warn(p->dev, "%s:%d invalid cmd stream\n", __func__, __LINE__);1748 return r;1749 }1750 break;1751 case PACKET3_WAIT_REG_MEM:1752 if (pkt->count != 5) {1753 DRM_ERROR("bad WAIT_REG_MEM\n");1754 return -EINVAL;1755 }1756 /* bit 4 is reg (0) or mem (1) */1757 if (idx_value & 0x10) {1758 uint64_t offset;1759 1760 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);1761 if (r) {1762 DRM_ERROR("bad WAIT_REG_MEM\n");1763 return -EINVAL;1764 }1765 1766 offset = reloc->gpu_offset +1767 (radeon_get_ib_value(p, idx+1) & 0xfffffff0) +1768 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);1769 1770 ib[idx+1] = (ib[idx+1] & 0x3) | (offset & 0xfffffff0);1771 ib[idx+2] = upper_32_bits(offset) & 0xff;1772 } else if (idx_value & 0x100) {1773 DRM_ERROR("cannot use PFP on REG wait\n");1774 return -EINVAL;1775 }1776 break;1777 case PACKET3_CP_DMA:1778 {1779 u32 command, size;1780 u64 offset, tmp;1781 if (pkt->count != 4) {1782 DRM_ERROR("bad CP DMA\n");1783 return -EINVAL;1784 }1785 command = radeon_get_ib_value(p, idx+4);1786 size = command & 0x1fffff;1787 if (command & PACKET3_CP_DMA_CMD_SAS) {1788 /* src address space is register */1789 DRM_ERROR("CP DMA SAS not supported\n");1790 return -EINVAL;1791 } else {1792 if (command & PACKET3_CP_DMA_CMD_SAIC) {1793 DRM_ERROR("CP DMA SAIC only supported for registers\n");1794 return -EINVAL;1795 }1796 /* src address space is memory */1797 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);1798 if (r) {1799 DRM_ERROR("bad CP DMA SRC\n");1800 return -EINVAL;1801 }1802 1803 tmp = radeon_get_ib_value(p, idx) +1804 ((u64)(radeon_get_ib_value(p, idx+1) & 0xff) << 32);1805 1806 offset = reloc->gpu_offset + tmp;1807 1808 if ((tmp + size) > radeon_bo_size(reloc->robj)) {1809 dev_warn(p->dev, "CP DMA src buffer too small (%llu %lu)\n",1810 tmp + size, radeon_bo_size(reloc->robj));1811 return -EINVAL;1812 }1813 1814 ib[idx] = offset;1815 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff);1816 }1817 if (command & PACKET3_CP_DMA_CMD_DAS) {1818 /* dst address space is register */1819 DRM_ERROR("CP DMA DAS not supported\n");1820 return -EINVAL;1821 } else {1822 /* dst address space is memory */1823 if (command & PACKET3_CP_DMA_CMD_DAIC) {1824 DRM_ERROR("CP DMA DAIC only supported for registers\n");1825 return -EINVAL;1826 }1827 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);1828 if (r) {1829 DRM_ERROR("bad CP DMA DST\n");1830 return -EINVAL;1831 }1832 1833 tmp = radeon_get_ib_value(p, idx+2) +1834 ((u64)(radeon_get_ib_value(p, idx+3) & 0xff) << 32);1835 1836 offset = reloc->gpu_offset + tmp;1837 1838 if ((tmp + size) > radeon_bo_size(reloc->robj)) {1839 dev_warn(p->dev, "CP DMA dst buffer too small (%llu %lu)\n",1840 tmp + size, radeon_bo_size(reloc->robj));1841 return -EINVAL;1842 }1843 1844 ib[idx+2] = offset;1845 ib[idx+3] = upper_32_bits(offset) & 0xff;1846 }1847 break;1848 }1849 case PACKET3_SURFACE_SYNC:1850 if (pkt->count != 3) {1851 DRM_ERROR("bad SURFACE_SYNC\n");1852 return -EINVAL;1853 }1854 /* 0xffffffff/0x0 is flush all cache flag */1855 if (radeon_get_ib_value(p, idx + 1) != 0xffffffff ||1856 radeon_get_ib_value(p, idx + 2) != 0) {1857 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);1858 if (r) {1859 DRM_ERROR("bad SURFACE_SYNC\n");1860 return -EINVAL;1861 }1862 ib[idx+2] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);1863 }1864 break;1865 case PACKET3_EVENT_WRITE:1866 if (pkt->count != 2 && pkt->count != 0) {1867 DRM_ERROR("bad EVENT_WRITE\n");1868 return -EINVAL;1869 }1870 if (pkt->count) {1871 uint64_t offset;1872 1873 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);1874 if (r) {1875 DRM_ERROR("bad EVENT_WRITE\n");1876 return -EINVAL;1877 }1878 offset = reloc->gpu_offset +1879 (radeon_get_ib_value(p, idx+1) & 0xfffffff8) +1880 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);1881 1882 ib[idx+1] = offset & 0xfffffff8;1883 ib[idx+2] = upper_32_bits(offset) & 0xff;1884 }1885 break;1886 case PACKET3_EVENT_WRITE_EOP:1887 {1888 uint64_t offset;1889 1890 if (pkt->count != 4) {1891 DRM_ERROR("bad EVENT_WRITE_EOP\n");1892 return -EINVAL;1893 }1894 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);1895 if (r) {1896 DRM_ERROR("bad EVENT_WRITE\n");1897 return -EINVAL;1898 }1899 1900 offset = reloc->gpu_offset +1901 (radeon_get_ib_value(p, idx+1) & 0xfffffffc) +1902 ((u64)(radeon_get_ib_value(p, idx+2) & 0xff) << 32);1903 1904 ib[idx+1] = offset & 0xfffffffc;1905 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff);1906 break;1907 }1908 case PACKET3_SET_CONFIG_REG:1909 start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET;1910 end_reg = 4 * pkt->count + start_reg - 4;1911 if ((start_reg < PACKET3_SET_CONFIG_REG_OFFSET) ||1912 (start_reg >= PACKET3_SET_CONFIG_REG_END) ||1913 (end_reg >= PACKET3_SET_CONFIG_REG_END)) {1914 DRM_ERROR("bad PACKET3_SET_CONFIG_REG\n");1915 return -EINVAL;1916 }1917 for (i = 0; i < pkt->count; i++) {1918 reg = start_reg + (4 * i);1919 r = r600_cs_check_reg(p, reg, idx+1+i);1920 if (r)1921 return r;1922 }1923 break;1924 case PACKET3_SET_CONTEXT_REG:1925 start_reg = (idx_value << 2) + PACKET3_SET_CONTEXT_REG_OFFSET;1926 end_reg = 4 * pkt->count + start_reg - 4;1927 if ((start_reg < PACKET3_SET_CONTEXT_REG_OFFSET) ||1928 (start_reg >= PACKET3_SET_CONTEXT_REG_END) ||1929 (end_reg >= PACKET3_SET_CONTEXT_REG_END)) {1930 DRM_ERROR("bad PACKET3_SET_CONTEXT_REG\n");1931 return -EINVAL;1932 }1933 for (i = 0; i < pkt->count; i++) {1934 reg = start_reg + (4 * i);1935 r = r600_cs_check_reg(p, reg, idx+1+i);1936 if (r)1937 return r;1938 }1939 break;1940 case PACKET3_SET_RESOURCE:1941 if (pkt->count % 7) {1942 DRM_ERROR("bad SET_RESOURCE\n");1943 return -EINVAL;1944 }1945 start_reg = (idx_value << 2) + PACKET3_SET_RESOURCE_OFFSET;1946 end_reg = 4 * pkt->count + start_reg - 4;1947 if ((start_reg < PACKET3_SET_RESOURCE_OFFSET) ||1948 (start_reg >= PACKET3_SET_RESOURCE_END) ||1949 (end_reg >= PACKET3_SET_RESOURCE_END)) {1950 DRM_ERROR("bad SET_RESOURCE\n");1951 return -EINVAL;1952 }1953 for (i = 0; i < (pkt->count / 7); i++) {1954 struct radeon_bo *texture, *mipmap;1955 u32 size, offset, base_offset, mip_offset;1956 1957 switch (G__SQ_VTX_CONSTANT_TYPE(radeon_get_ib_value(p, idx+(i*7)+6+1))) {1958 case SQ_TEX_VTX_VALID_TEXTURE:1959 /* tex base */1960 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);1961 if (r) {1962 DRM_ERROR("bad SET_RESOURCE\n");1963 return -EINVAL;1964 }1965 base_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);1966 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {1967 if (reloc->tiling_flags & RADEON_TILING_MACRO)1968 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_2D_TILED_THIN1);1969 else if (reloc->tiling_flags & RADEON_TILING_MICRO)1970 ib[idx+1+(i*7)+0] |= S_038000_TILE_MODE(V_038000_ARRAY_1D_TILED_THIN1);1971 }1972 texture = reloc->robj;1973 /* tex mip base */1974 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);1975 if (r) {1976 DRM_ERROR("bad SET_RESOURCE\n");1977 return -EINVAL;1978 }1979 mip_offset = (u32)((reloc->gpu_offset >> 8) & 0xffffffff);1980 mipmap = reloc->robj;1981 r = r600_check_texture_resource(p, idx+(i*7)+1,1982 texture, mipmap,1983 base_offset + radeon_get_ib_value(p, idx+1+(i*7)+2),1984 mip_offset + radeon_get_ib_value(p, idx+1+(i*7)+3),1985 reloc->tiling_flags);1986 if (r)1987 return r;1988 ib[idx+1+(i*7)+2] += base_offset;1989 ib[idx+1+(i*7)+3] += mip_offset;1990 break;1991 case SQ_TEX_VTX_VALID_BUFFER:1992 {1993 uint64_t offset64;1994 /* vtx base */1995 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);1996 if (r) {1997 DRM_ERROR("bad SET_RESOURCE\n");1998 return -EINVAL;1999 }2000 offset = radeon_get_ib_value(p, idx+1+(i*7)+0);2001 size = radeon_get_ib_value(p, idx+1+(i*7)+1) + 1;2002 if (p->rdev && (size + offset) > radeon_bo_size(reloc->robj)) {2003 /* force size to size of the buffer */2004 dev_warn(p->dev, "vbo resource seems too big (%d) for the bo (%ld)\n",2005 size + offset, radeon_bo_size(reloc->robj));2006 ib[idx+1+(i*7)+1] = radeon_bo_size(reloc->robj) - offset;2007 }2008 2009 offset64 = reloc->gpu_offset + offset;2010 ib[idx+1+(i*8)+0] = offset64;2011 ib[idx+1+(i*8)+2] = (ib[idx+1+(i*8)+2] & 0xffffff00) |2012 (upper_32_bits(offset64) & 0xff);2013 break;2014 }2015 case SQ_TEX_VTX_INVALID_TEXTURE:2016 case SQ_TEX_VTX_INVALID_BUFFER:2017 default:2018 DRM_ERROR("bad SET_RESOURCE\n");2019 return -EINVAL;2020 }2021 }2022 break;2023 case PACKET3_SET_ALU_CONST:2024 if (track->sq_config & DX9_CONSTS) {2025 start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;2026 end_reg = 4 * pkt->count + start_reg - 4;2027 if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||2028 (start_reg >= PACKET3_SET_ALU_CONST_END) ||2029 (end_reg >= PACKET3_SET_ALU_CONST_END)) {2030 DRM_ERROR("bad SET_ALU_CONST\n");2031 return -EINVAL;2032 }2033 }2034 break;2035 case PACKET3_SET_BOOL_CONST:2036 start_reg = (idx_value << 2) + PACKET3_SET_BOOL_CONST_OFFSET;2037 end_reg = 4 * pkt->count + start_reg - 4;2038 if ((start_reg < PACKET3_SET_BOOL_CONST_OFFSET) ||2039 (start_reg >= PACKET3_SET_BOOL_CONST_END) ||2040 (end_reg >= PACKET3_SET_BOOL_CONST_END)) {2041 DRM_ERROR("bad SET_BOOL_CONST\n");2042 return -EINVAL;2043 }2044 break;2045 case PACKET3_SET_LOOP_CONST:2046 start_reg = (idx_value << 2) + PACKET3_SET_LOOP_CONST_OFFSET;2047 end_reg = 4 * pkt->count + start_reg - 4;2048 if ((start_reg < PACKET3_SET_LOOP_CONST_OFFSET) ||2049 (start_reg >= PACKET3_SET_LOOP_CONST_END) ||2050 (end_reg >= PACKET3_SET_LOOP_CONST_END)) {2051 DRM_ERROR("bad SET_LOOP_CONST\n");2052 return -EINVAL;2053 }2054 break;2055 case PACKET3_SET_CTL_CONST:2056 start_reg = (idx_value << 2) + PACKET3_SET_CTL_CONST_OFFSET;2057 end_reg = 4 * pkt->count + start_reg - 4;2058 if ((start_reg < PACKET3_SET_CTL_CONST_OFFSET) ||2059 (start_reg >= PACKET3_SET_CTL_CONST_END) ||2060 (end_reg >= PACKET3_SET_CTL_CONST_END)) {2061 DRM_ERROR("bad SET_CTL_CONST\n");2062 return -EINVAL;2063 }2064 break;2065 case PACKET3_SET_SAMPLER:2066 if (pkt->count % 3) {2067 DRM_ERROR("bad SET_SAMPLER\n");2068 return -EINVAL;2069 }2070 start_reg = (idx_value << 2) + PACKET3_SET_SAMPLER_OFFSET;2071 end_reg = 4 * pkt->count + start_reg - 4;2072 if ((start_reg < PACKET3_SET_SAMPLER_OFFSET) ||2073 (start_reg >= PACKET3_SET_SAMPLER_END) ||2074 (end_reg >= PACKET3_SET_SAMPLER_END)) {2075 DRM_ERROR("bad SET_SAMPLER\n");2076 return -EINVAL;2077 }2078 break;2079 case PACKET3_STRMOUT_BASE_UPDATE:2080 /* RS780 and RS880 also need this */2081 if (p->family < CHIP_RS780) {2082 DRM_ERROR("STRMOUT_BASE_UPDATE only supported on 7xx\n");2083 return -EINVAL;2084 }2085 if (pkt->count != 1) {2086 DRM_ERROR("bad STRMOUT_BASE_UPDATE packet count\n");2087 return -EINVAL;2088 }2089 if (idx_value > 3) {2090 DRM_ERROR("bad STRMOUT_BASE_UPDATE index\n");2091 return -EINVAL;2092 }2093 {2094 u64 offset;2095 2096 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);2097 if (r) {2098 DRM_ERROR("bad STRMOUT_BASE_UPDATE reloc\n");2099 return -EINVAL;2100 }2101 2102 if (reloc->robj != track->vgt_strmout_bo[idx_value]) {2103 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo does not match\n");2104 return -EINVAL;2105 }2106 2107 offset = radeon_get_ib_value(p, idx+1) << 8;2108 if (offset != track->vgt_strmout_bo_offset[idx_value]) {2109 DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo offset does not match: 0x%llx, 0x%x\n",2110 offset, track->vgt_strmout_bo_offset[idx_value]);2111 return -EINVAL;2112 }2113 2114 if ((offset + 4) > radeon_bo_size(reloc->robj)) {2115 DRM_ERROR("bad STRMOUT_BASE_UPDATE bo too small: 0x%llx, 0x%lx\n",2116 offset + 4, radeon_bo_size(reloc->robj));2117 return -EINVAL;2118 }2119 ib[idx+1] += (u32)((reloc->gpu_offset >> 8) & 0xffffffff);2120 }2121 break;2122 case PACKET3_SURFACE_BASE_UPDATE:2123 if (p->family >= CHIP_RV770 || p->family == CHIP_R600) {2124 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");2125 return -EINVAL;2126 }2127 if (pkt->count) {2128 DRM_ERROR("bad SURFACE_BASE_UPDATE\n");2129 return -EINVAL;2130 }2131 break;2132 case PACKET3_STRMOUT_BUFFER_UPDATE:2133 if (pkt->count != 4) {2134 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (invalid count)\n");2135 return -EINVAL;2136 }2137 /* Updating memory at DST_ADDRESS. */2138 if (idx_value & 0x1) {2139 u64 offset;2140 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);2141 if (r) {2142 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing dst reloc)\n");2143 return -EINVAL;2144 }2145 offset = radeon_get_ib_value(p, idx+1);2146 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;2147 if ((offset + 4) > radeon_bo_size(reloc->robj)) {2148 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE dst bo too small: 0x%llx, 0x%lx\n",2149 offset + 4, radeon_bo_size(reloc->robj));2150 return -EINVAL;2151 }2152 offset += reloc->gpu_offset;2153 ib[idx+1] = offset;2154 ib[idx+2] = upper_32_bits(offset) & 0xff;2155 }2156 /* Reading data from SRC_ADDRESS. */2157 if (((idx_value >> 1) & 0x3) == 2) {2158 u64 offset;2159 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);2160 if (r) {2161 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE (missing src reloc)\n");2162 return -EINVAL;2163 }2164 offset = radeon_get_ib_value(p, idx+3);2165 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;2166 if ((offset + 4) > radeon_bo_size(reloc->robj)) {2167 DRM_ERROR("bad STRMOUT_BUFFER_UPDATE src bo too small: 0x%llx, 0x%lx\n",2168 offset + 4, radeon_bo_size(reloc->robj));2169 return -EINVAL;2170 }2171 offset += reloc->gpu_offset;2172 ib[idx+3] = offset;2173 ib[idx+4] = upper_32_bits(offset) & 0xff;2174 }2175 break;2176 case PACKET3_MEM_WRITE:2177 {2178 u64 offset;2179 2180 if (pkt->count != 3) {2181 DRM_ERROR("bad MEM_WRITE (invalid count)\n");2182 return -EINVAL;2183 }2184 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);2185 if (r) {2186 DRM_ERROR("bad MEM_WRITE (missing reloc)\n");2187 return -EINVAL;2188 }2189 offset = radeon_get_ib_value(p, idx+0);2190 offset += ((u64)(radeon_get_ib_value(p, idx+1) & 0xff)) << 32UL;2191 if (offset & 0x7) {2192 DRM_ERROR("bad MEM_WRITE (address not qwords aligned)\n");2193 return -EINVAL;2194 }2195 if ((offset + 8) > radeon_bo_size(reloc->robj)) {2196 DRM_ERROR("bad MEM_WRITE bo too small: 0x%llx, 0x%lx\n",2197 offset + 8, radeon_bo_size(reloc->robj));2198 return -EINVAL;2199 }2200 offset += reloc->gpu_offset;2201 ib[idx+0] = offset;2202 ib[idx+1] = upper_32_bits(offset) & 0xff;2203 break;2204 }2205 case PACKET3_COPY_DW:2206 if (pkt->count != 4) {2207 DRM_ERROR("bad COPY_DW (invalid count)\n");2208 return -EINVAL;2209 }2210 if (idx_value & 0x1) {2211 u64 offset;2212 /* SRC is memory. */2213 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);2214 if (r) {2215 DRM_ERROR("bad COPY_DW (missing src reloc)\n");2216 return -EINVAL;2217 }2218 offset = radeon_get_ib_value(p, idx+1);2219 offset += ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;2220 if ((offset + 4) > radeon_bo_size(reloc->robj)) {2221 DRM_ERROR("bad COPY_DW src bo too small: 0x%llx, 0x%lx\n",2222 offset + 4, radeon_bo_size(reloc->robj));2223 return -EINVAL;2224 }2225 offset += reloc->gpu_offset;2226 ib[idx+1] = offset;2227 ib[idx+2] = upper_32_bits(offset) & 0xff;2228 } else {2229 /* SRC is a reg. */2230 reg = radeon_get_ib_value(p, idx+1) << 2;2231 if (!r600_is_safe_reg(p, reg, idx+1))2232 return -EINVAL;2233 }2234 if (idx_value & 0x2) {2235 u64 offset;2236 /* DST is memory. */2237 r = radeon_cs_packet_next_reloc(p, &reloc, r600_nomm);2238 if (r) {2239 DRM_ERROR("bad COPY_DW (missing dst reloc)\n");2240 return -EINVAL;2241 }2242 offset = radeon_get_ib_value(p, idx+3);2243 offset += ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;2244 if ((offset + 4) > radeon_bo_size(reloc->robj)) {2245 DRM_ERROR("bad COPY_DW dst bo too small: 0x%llx, 0x%lx\n",2246 offset + 4, radeon_bo_size(reloc->robj));2247 return -EINVAL;2248 }2249 offset += reloc->gpu_offset;2250 ib[idx+3] = offset;2251 ib[idx+4] = upper_32_bits(offset) & 0xff;2252 } else {2253 /* DST is a reg. */2254 reg = radeon_get_ib_value(p, idx+3) << 2;2255 if (!r600_is_safe_reg(p, reg, idx+3))2256 return -EINVAL;2257 }2258 break;2259 case PACKET3_NOP:2260 break;2261 default:2262 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);2263 return -EINVAL;2264 }2265 return 0;2266}2267 2268int r600_cs_parse(struct radeon_cs_parser *p)2269{2270 struct radeon_cs_packet pkt;2271 struct r600_cs_track *track;2272 int r;2273 2274 if (p->track == NULL) {2275 /* initialize tracker, we are in kms */2276 track = kzalloc(sizeof(*track), GFP_KERNEL);2277 if (track == NULL)2278 return -ENOMEM;2279 r600_cs_track_init(track);2280 if (p->rdev->family < CHIP_RV770) {2281 track->npipes = p->rdev->config.r600.tiling_npipes;2282 track->nbanks = p->rdev->config.r600.tiling_nbanks;2283 track->group_size = p->rdev->config.r600.tiling_group_size;2284 } else if (p->rdev->family <= CHIP_RV740) {2285 track->npipes = p->rdev->config.rv770.tiling_npipes;2286 track->nbanks = p->rdev->config.rv770.tiling_nbanks;2287 track->group_size = p->rdev->config.rv770.tiling_group_size;2288 }2289 p->track = track;2290 }2291 do {2292 r = radeon_cs_packet_parse(p, &pkt, p->idx);2293 if (r) {2294 kfree(p->track);2295 p->track = NULL;2296 return r;2297 }2298 p->idx += pkt.count + 2;2299 switch (pkt.type) {2300 case RADEON_PACKET_TYPE0:2301 r = r600_cs_parse_packet0(p, &pkt);2302 break;2303 case RADEON_PACKET_TYPE2:2304 break;2305 case RADEON_PACKET_TYPE3:2306 r = r600_packet3_check(p, &pkt);2307 break;2308 default:2309 DRM_ERROR("Unknown packet type %d !\n", pkt.type);2310 kfree(p->track);2311 p->track = NULL;2312 return -EINVAL;2313 }2314 if (r) {2315 kfree(p->track);2316 p->track = NULL;2317 return r;2318 }2319 } while (p->idx < p->chunk_ib->length_dw);2320#if 02321 for (r = 0; r < p->ib.length_dw; r++) {2322 pr_info("%05d 0x%08X\n", r, p->ib.ptr[r]);2323 mdelay(1);2324 }2325#endif2326 kfree(p->track);2327 p->track = NULL;2328 return 0;2329}2330 2331/*2332 * DMA2333 */2334/**2335 * r600_dma_cs_next_reloc() - parse next reloc2336 * @p: parser structure holding parsing context.2337 * @cs_reloc: reloc information2338 *2339 * Return the next reloc, do bo validation and compute2340 * GPU offset using the provided start.2341 **/2342int r600_dma_cs_next_reloc(struct radeon_cs_parser *p,2343 struct radeon_bo_list **cs_reloc)2344{2345 unsigned idx;2346 2347 *cs_reloc = NULL;2348 if (p->chunk_relocs == NULL) {2349 DRM_ERROR("No relocation chunk !\n");2350 return -EINVAL;2351 }2352 idx = p->dma_reloc_idx;2353 if (idx >= p->nrelocs) {2354 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",2355 idx, p->nrelocs);2356 return -EINVAL;2357 }2358 *cs_reloc = &p->relocs[idx];2359 p->dma_reloc_idx++;2360 return 0;2361}2362 2363#define GET_DMA_CMD(h) (((h) & 0xf0000000) >> 28)2364#define GET_DMA_COUNT(h) ((h) & 0x0000ffff)2365#define GET_DMA_T(h) (((h) & 0x00800000) >> 23)2366 2367/**2368 * r600_dma_cs_parse() - parse the DMA IB2369 * @p: parser structure holding parsing context.2370 *2371 * Parses the DMA IB from the CS ioctl and updates2372 * the GPU addresses based on the reloc information and2373 * checks for errors. (R6xx-R7xx)2374 * Returns 0 for success and an error on failure.2375 **/2376int r600_dma_cs_parse(struct radeon_cs_parser *p)2377{2378 struct radeon_cs_chunk *ib_chunk = p->chunk_ib;2379 struct radeon_bo_list *src_reloc, *dst_reloc;2380 u32 header, cmd, count, tiled;2381 volatile u32 *ib = p->ib.ptr;2382 u32 idx, idx_value;2383 u64 src_offset, dst_offset;2384 int r;2385 2386 do {2387 if (p->idx >= ib_chunk->length_dw) {2388 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",2389 p->idx, ib_chunk->length_dw);2390 return -EINVAL;2391 }2392 idx = p->idx;2393 header = radeon_get_ib_value(p, idx);2394 cmd = GET_DMA_CMD(header);2395 count = GET_DMA_COUNT(header);2396 tiled = GET_DMA_T(header);2397 2398 switch (cmd) {2399 case DMA_PACKET_WRITE:2400 r = r600_dma_cs_next_reloc(p, &dst_reloc);2401 if (r) {2402 DRM_ERROR("bad DMA_PACKET_WRITE\n");2403 return -EINVAL;2404 }2405 if (tiled) {2406 dst_offset = radeon_get_ib_value(p, idx+1);2407 dst_offset <<= 8;2408 2409 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);2410 p->idx += count + 5;2411 } else {2412 dst_offset = radeon_get_ib_value(p, idx+1);2413 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+2) & 0xff)) << 32;2414 2415 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);2416 ib[idx+2] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;2417 p->idx += count + 3;2418 }2419 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {2420 dev_warn(p->dev, "DMA write buffer too small (%llu %lu)\n",2421 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));2422 return -EINVAL;2423 }2424 break;2425 case DMA_PACKET_COPY:2426 r = r600_dma_cs_next_reloc(p, &src_reloc);2427 if (r) {2428 DRM_ERROR("bad DMA_PACKET_COPY\n");2429 return -EINVAL;2430 }2431 r = r600_dma_cs_next_reloc(p, &dst_reloc);2432 if (r) {2433 DRM_ERROR("bad DMA_PACKET_COPY\n");2434 return -EINVAL;2435 }2436 if (tiled) {2437 idx_value = radeon_get_ib_value(p, idx + 2);2438 /* detile bit */2439 if (idx_value & (1 << 31)) {2440 /* tiled src, linear dst */2441 src_offset = radeon_get_ib_value(p, idx+1);2442 src_offset <<= 8;2443 ib[idx+1] += (u32)(src_reloc->gpu_offset >> 8);2444 2445 dst_offset = radeon_get_ib_value(p, idx+5);2446 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;2447 ib[idx+5] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);2448 ib[idx+6] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;2449 } else {2450 /* linear src, tiled dst */2451 src_offset = radeon_get_ib_value(p, idx+5);2452 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32;2453 ib[idx+5] += (u32)(src_reloc->gpu_offset & 0xfffffffc);2454 ib[idx+6] += upper_32_bits(src_reloc->gpu_offset) & 0xff;2455 2456 dst_offset = radeon_get_ib_value(p, idx+1);2457 dst_offset <<= 8;2458 ib[idx+1] += (u32)(dst_reloc->gpu_offset >> 8);2459 }2460 p->idx += 7;2461 } else {2462 if (p->family >= CHIP_RV770) {2463 src_offset = radeon_get_ib_value(p, idx+2);2464 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32;2465 dst_offset = radeon_get_ib_value(p, idx+1);2466 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;2467 2468 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);2469 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);2470 ib[idx+3] += upper_32_bits(dst_reloc->gpu_offset) & 0xff;2471 ib[idx+4] += upper_32_bits(src_reloc->gpu_offset) & 0xff;2472 p->idx += 5;2473 } else {2474 src_offset = radeon_get_ib_value(p, idx+2);2475 src_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32;2476 dst_offset = radeon_get_ib_value(p, idx+1);2477 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff0000)) << 16;2478 2479 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);2480 ib[idx+2] += (u32)(src_reloc->gpu_offset & 0xfffffffc);2481 ib[idx+3] += upper_32_bits(src_reloc->gpu_offset) & 0xff;2482 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) & 0xff) << 16;2483 p->idx += 4;2484 }2485 }2486 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) {2487 dev_warn(p->dev, "DMA copy src buffer too small (%llu %lu)\n",2488 src_offset + (count * 4), radeon_bo_size(src_reloc->robj));2489 return -EINVAL;2490 }2491 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {2492 dev_warn(p->dev, "DMA write dst buffer too small (%llu %lu)\n",2493 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));2494 return -EINVAL;2495 }2496 break;2497 case DMA_PACKET_CONSTANT_FILL:2498 if (p->family < CHIP_RV770) {2499 DRM_ERROR("Constant Fill is 7xx only !\n");2500 return -EINVAL;2501 }2502 r = r600_dma_cs_next_reloc(p, &dst_reloc);2503 if (r) {2504 DRM_ERROR("bad DMA_PACKET_WRITE\n");2505 return -EINVAL;2506 }2507 dst_offset = radeon_get_ib_value(p, idx+1);2508 dst_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0x00ff0000)) << 16;2509 if ((dst_offset + (count * 4)) > radeon_bo_size(dst_reloc->robj)) {2510 dev_warn(p->dev, "DMA constant fill buffer too small (%llu %lu)\n",2511 dst_offset + (count * 4), radeon_bo_size(dst_reloc->robj));2512 return -EINVAL;2513 }2514 ib[idx+1] += (u32)(dst_reloc->gpu_offset & 0xfffffffc);2515 ib[idx+3] += (upper_32_bits(dst_reloc->gpu_offset) << 16) & 0x00ff0000;2516 p->idx += 4;2517 break;2518 case DMA_PACKET_NOP:2519 p->idx += 1;2520 break;2521 default:2522 DRM_ERROR("Unknown packet type %d at %d !\n", cmd, idx);2523 return -EINVAL;2524 }2525 } while (p->idx < p->chunk_ib->length_dw);2526#if 02527 for (r = 0; r < p->ib->length_dw; r++) {2528 pr_info("%05d 0x%08X\n", r, p->ib.ptr[r]);2529 mdelay(1);2530 }2531#endif2532 return 0;2533}2534