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1/*2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario3 * Copyright 2007-8 Advanced Micro Devices, Inc.4 * Copyright 2008 Red Hat Inc.5 *6 * Permission is hereby granted, free of charge, to any person obtaining a7 * copy of this software and associated documentation files (the "Software"),8 * to deal in the Software without restriction, including without limitation9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,10 * and/or sell copies of the Software, and to permit persons to whom the11 * Software is furnished to do so, subject to the following conditions:12 *13 * The above copyright notice and this permission notice shall be included in14 * all copies or substantial portions of the Software.15 *16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR22 * OTHER DEALINGS IN THE SOFTWARE.23 *24 * Authors: Dave Airlie25 * Alex Deucher26 */27 28#include <linux/pci.h>29 30#include <drm/drm_device.h>31#include <drm/drm_edid.h>32#include <drm/radeon_drm.h>33 34#include "radeon.h"35#include "radeon_legacy_encoders.h"36#include "atom.h"37 38#ifdef CONFIG_PPC_PMAC39/* not sure which of these are needed */40#include <asm/machdep.h>41#include <asm/pmac_feature.h>42#include <asm/prom.h>43#endif /* CONFIG_PPC_PMAC */44 45/* old legacy ATI BIOS routines */46 47/* COMBIOS table offsets */48enum radeon_combios_table_offset {49 /* absolute offset tables */50 COMBIOS_ASIC_INIT_1_TABLE,51 COMBIOS_BIOS_SUPPORT_TABLE,52 COMBIOS_DAC_PROGRAMMING_TABLE,53 COMBIOS_MAX_COLOR_DEPTH_TABLE,54 COMBIOS_CRTC_INFO_TABLE,55 COMBIOS_PLL_INFO_TABLE,56 COMBIOS_TV_INFO_TABLE,57 COMBIOS_DFP_INFO_TABLE,58 COMBIOS_HW_CONFIG_INFO_TABLE,59 COMBIOS_MULTIMEDIA_INFO_TABLE,60 COMBIOS_TV_STD_PATCH_TABLE,61 COMBIOS_LCD_INFO_TABLE,62 COMBIOS_MOBILE_INFO_TABLE,63 COMBIOS_PLL_INIT_TABLE,64 COMBIOS_MEM_CONFIG_TABLE,65 COMBIOS_SAVE_MASK_TABLE,66 COMBIOS_HARDCODED_EDID_TABLE,67 COMBIOS_ASIC_INIT_2_TABLE,68 COMBIOS_CONNECTOR_INFO_TABLE,69 COMBIOS_DYN_CLK_1_TABLE,70 COMBIOS_RESERVED_MEM_TABLE,71 COMBIOS_EXT_TMDS_INFO_TABLE,72 COMBIOS_MEM_CLK_INFO_TABLE,73 COMBIOS_EXT_DAC_INFO_TABLE,74 COMBIOS_MISC_INFO_TABLE,75 COMBIOS_CRT_INFO_TABLE,76 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE,77 COMBIOS_COMPONENT_VIDEO_INFO_TABLE,78 COMBIOS_FAN_SPEED_INFO_TABLE,79 COMBIOS_OVERDRIVE_INFO_TABLE,80 COMBIOS_OEM_INFO_TABLE,81 COMBIOS_DYN_CLK_2_TABLE,82 COMBIOS_POWER_CONNECTOR_INFO_TABLE,83 COMBIOS_I2C_INFO_TABLE,84 /* relative offset tables */85 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */86 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */87 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */88 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */89 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */90 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */91 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */92 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */93 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */94 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */95 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */96};97 98enum radeon_combios_ddc {99 DDC_NONE_DETECTED,100 DDC_MONID,101 DDC_DVI,102 DDC_VGA,103 DDC_CRT2,104 DDC_LCD,105 DDC_GPIO,106};107 108enum radeon_combios_connector {109 CONNECTOR_NONE_LEGACY,110 CONNECTOR_PROPRIETARY_LEGACY,111 CONNECTOR_CRT_LEGACY,112 CONNECTOR_DVI_I_LEGACY,113 CONNECTOR_DVI_D_LEGACY,114 CONNECTOR_CTV_LEGACY,115 CONNECTOR_STV_LEGACY,116 CONNECTOR_UNSUPPORTED_LEGACY117};118 119static const int legacy_connector_convert[] = {120 DRM_MODE_CONNECTOR_Unknown,121 DRM_MODE_CONNECTOR_DVID,122 DRM_MODE_CONNECTOR_VGA,123 DRM_MODE_CONNECTOR_DVII,124 DRM_MODE_CONNECTOR_DVID,125 DRM_MODE_CONNECTOR_Composite,126 DRM_MODE_CONNECTOR_SVIDEO,127 DRM_MODE_CONNECTOR_Unknown,128};129 130static uint16_t combios_get_table_offset(struct drm_device *dev,131 enum radeon_combios_table_offset table)132{133 struct radeon_device *rdev = dev->dev_private;134 int rev, size;135 uint16_t offset = 0, check_offset;136 137 if (!rdev->bios)138 return 0;139 140 switch (table) {141 /* absolute offset tables */142 case COMBIOS_ASIC_INIT_1_TABLE:143 check_offset = 0xc;144 break;145 case COMBIOS_BIOS_SUPPORT_TABLE:146 check_offset = 0x14;147 break;148 case COMBIOS_DAC_PROGRAMMING_TABLE:149 check_offset = 0x2a;150 break;151 case COMBIOS_MAX_COLOR_DEPTH_TABLE:152 check_offset = 0x2c;153 break;154 case COMBIOS_CRTC_INFO_TABLE:155 check_offset = 0x2e;156 break;157 case COMBIOS_PLL_INFO_TABLE:158 check_offset = 0x30;159 break;160 case COMBIOS_TV_INFO_TABLE:161 check_offset = 0x32;162 break;163 case COMBIOS_DFP_INFO_TABLE:164 check_offset = 0x34;165 break;166 case COMBIOS_HW_CONFIG_INFO_TABLE:167 check_offset = 0x36;168 break;169 case COMBIOS_MULTIMEDIA_INFO_TABLE:170 check_offset = 0x38;171 break;172 case COMBIOS_TV_STD_PATCH_TABLE:173 check_offset = 0x3e;174 break;175 case COMBIOS_LCD_INFO_TABLE:176 check_offset = 0x40;177 break;178 case COMBIOS_MOBILE_INFO_TABLE:179 check_offset = 0x42;180 break;181 case COMBIOS_PLL_INIT_TABLE:182 check_offset = 0x46;183 break;184 case COMBIOS_MEM_CONFIG_TABLE:185 check_offset = 0x48;186 break;187 case COMBIOS_SAVE_MASK_TABLE:188 check_offset = 0x4a;189 break;190 case COMBIOS_HARDCODED_EDID_TABLE:191 check_offset = 0x4c;192 break;193 case COMBIOS_ASIC_INIT_2_TABLE:194 check_offset = 0x4e;195 break;196 case COMBIOS_CONNECTOR_INFO_TABLE:197 check_offset = 0x50;198 break;199 case COMBIOS_DYN_CLK_1_TABLE:200 check_offset = 0x52;201 break;202 case COMBIOS_RESERVED_MEM_TABLE:203 check_offset = 0x54;204 break;205 case COMBIOS_EXT_TMDS_INFO_TABLE:206 check_offset = 0x58;207 break;208 case COMBIOS_MEM_CLK_INFO_TABLE:209 check_offset = 0x5a;210 break;211 case COMBIOS_EXT_DAC_INFO_TABLE:212 check_offset = 0x5c;213 break;214 case COMBIOS_MISC_INFO_TABLE:215 check_offset = 0x5e;216 break;217 case COMBIOS_CRT_INFO_TABLE:218 check_offset = 0x60;219 break;220 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:221 check_offset = 0x62;222 break;223 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:224 check_offset = 0x64;225 break;226 case COMBIOS_FAN_SPEED_INFO_TABLE:227 check_offset = 0x66;228 break;229 case COMBIOS_OVERDRIVE_INFO_TABLE:230 check_offset = 0x68;231 break;232 case COMBIOS_OEM_INFO_TABLE:233 check_offset = 0x6a;234 break;235 case COMBIOS_DYN_CLK_2_TABLE:236 check_offset = 0x6c;237 break;238 case COMBIOS_POWER_CONNECTOR_INFO_TABLE:239 check_offset = 0x6e;240 break;241 case COMBIOS_I2C_INFO_TABLE:242 check_offset = 0x70;243 break;244 /* relative offset tables */245 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */246 check_offset =247 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);248 if (check_offset) {249 rev = RBIOS8(check_offset);250 if (rev > 0) {251 check_offset = RBIOS16(check_offset + 0x3);252 if (check_offset)253 offset = check_offset;254 }255 }256 break;257 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */258 check_offset =259 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);260 if (check_offset) {261 rev = RBIOS8(check_offset);262 if (rev > 0) {263 check_offset = RBIOS16(check_offset + 0x5);264 if (check_offset)265 offset = check_offset;266 }267 }268 break;269 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */270 check_offset =271 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);272 if (check_offset) {273 rev = RBIOS8(check_offset);274 if (rev > 0) {275 check_offset = RBIOS16(check_offset + 0x7);276 if (check_offset)277 offset = check_offset;278 }279 }280 break;281 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */282 check_offset =283 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE);284 if (check_offset) {285 rev = RBIOS8(check_offset);286 if (rev == 2) {287 check_offset = RBIOS16(check_offset + 0x9);288 if (check_offset)289 offset = check_offset;290 }291 }292 break;293 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */294 check_offset =295 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);296 if (check_offset) {297 while (RBIOS8(check_offset++));298 check_offset += 2;299 if (check_offset)300 offset = check_offset;301 }302 break;303 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */304 check_offset =305 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);306 if (check_offset) {307 check_offset = RBIOS16(check_offset + 0x11);308 if (check_offset)309 offset = check_offset;310 }311 break;312 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */313 check_offset =314 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);315 if (check_offset) {316 check_offset = RBIOS16(check_offset + 0x13);317 if (check_offset)318 offset = check_offset;319 }320 break;321 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */322 check_offset =323 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);324 if (check_offset) {325 check_offset = RBIOS16(check_offset + 0x15);326 if (check_offset)327 offset = check_offset;328 }329 break;330 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */331 check_offset =332 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE);333 if (check_offset) {334 check_offset = RBIOS16(check_offset + 0x17);335 if (check_offset)336 offset = check_offset;337 }338 break;339 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */340 check_offset =341 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);342 if (check_offset) {343 check_offset = RBIOS16(check_offset + 0x2);344 if (check_offset)345 offset = check_offset;346 }347 break;348 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */349 check_offset =350 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE);351 if (check_offset) {352 check_offset = RBIOS16(check_offset + 0x4);353 if (check_offset)354 offset = check_offset;355 }356 break;357 default:358 check_offset = 0;359 break;360 }361 362 size = RBIOS8(rdev->bios_header_start + 0x6);363 /* check absolute offset tables */364 if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size)365 offset = RBIOS16(rdev->bios_header_start + check_offset);366 367 return offset;368}369 370bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)371{372 int edid_info, size;373 const struct drm_edid *edid;374 unsigned char *raw;375 edid_info = combios_get_table_offset(rdev_to_drm(rdev), COMBIOS_HARDCODED_EDID_TABLE);376 if (!edid_info)377 return false;378 379 raw = rdev->bios + edid_info;380 size = EDID_LENGTH * (raw[0x7e] + 1);381 edid = drm_edid_alloc(raw, size);382 383 if (!drm_edid_valid(edid)) {384 drm_edid_free(edid);385 return false;386 }387 388 rdev->mode_info.bios_hardcoded_edid = edid;389 return true;390}391 392/* this is used for atom LCDs as well */393struct edid *394radeon_bios_get_hardcoded_edid(struct radeon_device *rdev)395{396 return drm_edid_duplicate(drm_edid_raw(rdev->mode_info.bios_hardcoded_edid));397}398 399static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev,400 enum radeon_combios_ddc ddc,401 u32 clk_mask,402 u32 data_mask)403{404 struct radeon_i2c_bus_rec i2c;405 int ddc_line = 0;406 407 /* ddc id = mask reg408 * DDC_NONE_DETECTED = none409 * DDC_DVI = RADEON_GPIO_DVI_DDC410 * DDC_VGA = RADEON_GPIO_VGA_DDC411 * DDC_LCD = RADEON_GPIOPAD_MASK412 * DDC_GPIO = RADEON_MDGPIO_MASK413 * r1xx414 * DDC_MONID = RADEON_GPIO_MONID415 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC416 * r200417 * DDC_MONID = RADEON_GPIO_MONID418 * DDC_CRT2 = RADEON_GPIO_DVI_DDC419 * r300/r350420 * DDC_MONID = RADEON_GPIO_DVI_DDC421 * DDC_CRT2 = RADEON_GPIO_DVI_DDC422 * rv2xx/rv3xx423 * DDC_MONID = RADEON_GPIO_MONID424 * DDC_CRT2 = RADEON_GPIO_MONID425 * rs3xx/rs4xx426 * DDC_MONID = RADEON_GPIOPAD_MASK427 * DDC_CRT2 = RADEON_GPIO_MONID428 */429 switch (ddc) {430 case DDC_NONE_DETECTED:431 default:432 ddc_line = 0;433 break;434 case DDC_DVI:435 ddc_line = RADEON_GPIO_DVI_DDC;436 break;437 case DDC_VGA:438 ddc_line = RADEON_GPIO_VGA_DDC;439 break;440 case DDC_LCD:441 ddc_line = RADEON_GPIOPAD_MASK;442 break;443 case DDC_GPIO:444 ddc_line = RADEON_MDGPIO_MASK;445 break;446 case DDC_MONID:447 if (rdev->family == CHIP_RS300 ||448 rdev->family == CHIP_RS400 ||449 rdev->family == CHIP_RS480)450 ddc_line = RADEON_GPIOPAD_MASK;451 else if (rdev->family == CHIP_R300 ||452 rdev->family == CHIP_R350) {453 ddc_line = RADEON_GPIO_DVI_DDC;454 ddc = DDC_DVI;455 } else456 ddc_line = RADEON_GPIO_MONID;457 break;458 case DDC_CRT2:459 if (rdev->family == CHIP_R200 ||460 rdev->family == CHIP_R300 ||461 rdev->family == CHIP_R350) {462 ddc_line = RADEON_GPIO_DVI_DDC;463 ddc = DDC_DVI;464 } else if (rdev->family == CHIP_RS300 ||465 rdev->family == CHIP_RS400 ||466 rdev->family == CHIP_RS480)467 ddc_line = RADEON_GPIO_MONID;468 else if (rdev->family >= CHIP_RV350) {469 ddc_line = RADEON_GPIO_MONID;470 ddc = DDC_MONID;471 } else472 ddc_line = RADEON_GPIO_CRT2_DDC;473 break;474 }475 476 if (ddc_line == RADEON_GPIOPAD_MASK) {477 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK;478 i2c.mask_data_reg = RADEON_GPIOPAD_MASK;479 i2c.a_clk_reg = RADEON_GPIOPAD_A;480 i2c.a_data_reg = RADEON_GPIOPAD_A;481 i2c.en_clk_reg = RADEON_GPIOPAD_EN;482 i2c.en_data_reg = RADEON_GPIOPAD_EN;483 i2c.y_clk_reg = RADEON_GPIOPAD_Y;484 i2c.y_data_reg = RADEON_GPIOPAD_Y;485 } else if (ddc_line == RADEON_MDGPIO_MASK) {486 i2c.mask_clk_reg = RADEON_MDGPIO_MASK;487 i2c.mask_data_reg = RADEON_MDGPIO_MASK;488 i2c.a_clk_reg = RADEON_MDGPIO_A;489 i2c.a_data_reg = RADEON_MDGPIO_A;490 i2c.en_clk_reg = RADEON_MDGPIO_EN;491 i2c.en_data_reg = RADEON_MDGPIO_EN;492 i2c.y_clk_reg = RADEON_MDGPIO_Y;493 i2c.y_data_reg = RADEON_MDGPIO_Y;494 } else {495 i2c.mask_clk_reg = ddc_line;496 i2c.mask_data_reg = ddc_line;497 i2c.a_clk_reg = ddc_line;498 i2c.a_data_reg = ddc_line;499 i2c.en_clk_reg = ddc_line;500 i2c.en_data_reg = ddc_line;501 i2c.y_clk_reg = ddc_line;502 i2c.y_data_reg = ddc_line;503 }504 505 if (clk_mask && data_mask) {506 /* system specific masks */507 i2c.mask_clk_mask = clk_mask;508 i2c.mask_data_mask = data_mask;509 i2c.a_clk_mask = clk_mask;510 i2c.a_data_mask = data_mask;511 i2c.en_clk_mask = clk_mask;512 i2c.en_data_mask = data_mask;513 i2c.y_clk_mask = clk_mask;514 i2c.y_data_mask = data_mask;515 } else if ((ddc_line == RADEON_GPIOPAD_MASK) ||516 (ddc_line == RADEON_MDGPIO_MASK)) {517 /* default gpiopad masks */518 i2c.mask_clk_mask = (0x20 << 8);519 i2c.mask_data_mask = 0x80;520 i2c.a_clk_mask = (0x20 << 8);521 i2c.a_data_mask = 0x80;522 i2c.en_clk_mask = (0x20 << 8);523 i2c.en_data_mask = 0x80;524 i2c.y_clk_mask = (0x20 << 8);525 i2c.y_data_mask = 0x80;526 } else {527 /* default masks for ddc pads */528 i2c.mask_clk_mask = RADEON_GPIO_MASK_1;529 i2c.mask_data_mask = RADEON_GPIO_MASK_0;530 i2c.a_clk_mask = RADEON_GPIO_A_1;531 i2c.a_data_mask = RADEON_GPIO_A_0;532 i2c.en_clk_mask = RADEON_GPIO_EN_1;533 i2c.en_data_mask = RADEON_GPIO_EN_0;534 i2c.y_clk_mask = RADEON_GPIO_Y_1;535 i2c.y_data_mask = RADEON_GPIO_Y_0;536 }537 538 switch (rdev->family) {539 case CHIP_R100:540 case CHIP_RV100:541 case CHIP_RS100:542 case CHIP_RV200:543 case CHIP_RS200:544 case CHIP_RS300:545 switch (ddc_line) {546 case RADEON_GPIO_DVI_DDC:547 i2c.hw_capable = true;548 break;549 default:550 i2c.hw_capable = false;551 break;552 }553 break;554 case CHIP_R200:555 switch (ddc_line) {556 case RADEON_GPIO_DVI_DDC:557 case RADEON_GPIO_MONID:558 i2c.hw_capable = true;559 break;560 default:561 i2c.hw_capable = false;562 break;563 }564 break;565 case CHIP_RV250:566 case CHIP_RV280:567 switch (ddc_line) {568 case RADEON_GPIO_VGA_DDC:569 case RADEON_GPIO_DVI_DDC:570 case RADEON_GPIO_CRT2_DDC:571 i2c.hw_capable = true;572 break;573 default:574 i2c.hw_capable = false;575 break;576 }577 break;578 case CHIP_R300:579 case CHIP_R350:580 switch (ddc_line) {581 case RADEON_GPIO_VGA_DDC:582 case RADEON_GPIO_DVI_DDC:583 i2c.hw_capable = true;584 break;585 default:586 i2c.hw_capable = false;587 break;588 }589 break;590 case CHIP_RV350:591 case CHIP_RV380:592 case CHIP_RS400:593 case CHIP_RS480:594 switch (ddc_line) {595 case RADEON_GPIO_VGA_DDC:596 case RADEON_GPIO_DVI_DDC:597 i2c.hw_capable = true;598 break;599 case RADEON_GPIO_MONID:600 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work601 * reliably on some pre-r4xx hardware; not sure why.602 */603 i2c.hw_capable = false;604 break;605 default:606 i2c.hw_capable = false;607 break;608 }609 break;610 default:611 i2c.hw_capable = false;612 break;613 }614 i2c.mm_i2c = false;615 616 i2c.i2c_id = ddc;617 i2c.hpd = RADEON_HPD_NONE;618 619 if (ddc_line)620 i2c.valid = true;621 else622 i2c.valid = false;623 624 return i2c;625}626 627static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev)628{629 struct drm_device *dev = rdev_to_drm(rdev);630 struct radeon_i2c_bus_rec i2c;631 u16 offset;632 u8 id, blocks, clk, data;633 int i;634 635 i2c.valid = false;636 637 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE);638 if (offset) {639 blocks = RBIOS8(offset + 2);640 for (i = 0; i < blocks; i++) {641 id = RBIOS8(offset + 3 + (i * 5) + 0);642 if (id == 136) {643 clk = RBIOS8(offset + 3 + (i * 5) + 3);644 data = RBIOS8(offset + 3 + (i * 5) + 4);645 /* gpiopad */646 i2c = combios_setup_i2c_bus(rdev, DDC_MONID,647 (1 << clk), (1 << data));648 break;649 }650 }651 }652 return i2c;653}654 655void radeon_combios_i2c_init(struct radeon_device *rdev)656{657 struct drm_device *dev = rdev_to_drm(rdev);658 struct radeon_i2c_bus_rec i2c;659 660 /* actual hw pads661 * r1xx/rs2xx/rs3xx662 * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm663 * r200664 * 0x60, 0x64, 0x68, mm665 * r300/r350666 * 0x60, 0x64, mm667 * rv2xx/rv3xx/rs4xx668 * 0x60, 0x64, 0x68, gpiopads, mm669 */670 671 /* 0x60 */672 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);673 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");674 /* 0x64 */675 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);676 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");677 678 /* mm i2c */679 i2c.valid = true;680 i2c.hw_capable = true;681 i2c.mm_i2c = true;682 i2c.i2c_id = 0xa0;683 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");684 685 if (rdev->family == CHIP_R300 ||686 rdev->family == CHIP_R350) {687 /* only 2 sw i2c pads */688 } else if (rdev->family == CHIP_RS300 ||689 rdev->family == CHIP_RS400 ||690 rdev->family == CHIP_RS480) {691 /* 0x68 */692 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);693 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");694 695 /* gpiopad */696 i2c = radeon_combios_get_i2c_info_from_table(rdev);697 if (i2c.valid)698 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");699 } else if ((rdev->family == CHIP_R200) ||700 (rdev->family >= CHIP_R300)) {701 /* 0x68 */702 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);703 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");704 } else {705 /* 0x68 */706 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);707 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");708 /* 0x6c */709 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);710 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");711 }712}713 714bool radeon_combios_get_clock_info(struct drm_device *dev)715{716 struct radeon_device *rdev = dev->dev_private;717 uint16_t pll_info;718 struct radeon_pll *p1pll = &rdev->clock.p1pll;719 struct radeon_pll *p2pll = &rdev->clock.p2pll;720 struct radeon_pll *spll = &rdev->clock.spll;721 struct radeon_pll *mpll = &rdev->clock.mpll;722 int8_t rev;723 uint16_t sclk, mclk;724 725 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE);726 if (pll_info) {727 rev = RBIOS8(pll_info);728 729 /* pixel clocks */730 p1pll->reference_freq = RBIOS16(pll_info + 0xe);731 p1pll->reference_div = RBIOS16(pll_info + 0x10);732 p1pll->pll_out_min = RBIOS32(pll_info + 0x12);733 p1pll->pll_out_max = RBIOS32(pll_info + 0x16);734 p1pll->lcd_pll_out_min = p1pll->pll_out_min;735 p1pll->lcd_pll_out_max = p1pll->pll_out_max;736 737 if (rev > 9) {738 p1pll->pll_in_min = RBIOS32(pll_info + 0x36);739 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a);740 } else {741 p1pll->pll_in_min = 40;742 p1pll->pll_in_max = 500;743 }744 *p2pll = *p1pll;745 746 /* system clock */747 spll->reference_freq = RBIOS16(pll_info + 0x1a);748 spll->reference_div = RBIOS16(pll_info + 0x1c);749 spll->pll_out_min = RBIOS32(pll_info + 0x1e);750 spll->pll_out_max = RBIOS32(pll_info + 0x22);751 752 if (rev > 10) {753 spll->pll_in_min = RBIOS32(pll_info + 0x48);754 spll->pll_in_max = RBIOS32(pll_info + 0x4c);755 } else {756 /* ??? */757 spll->pll_in_min = 40;758 spll->pll_in_max = 500;759 }760 761 /* memory clock */762 mpll->reference_freq = RBIOS16(pll_info + 0x26);763 mpll->reference_div = RBIOS16(pll_info + 0x28);764 mpll->pll_out_min = RBIOS32(pll_info + 0x2a);765 mpll->pll_out_max = RBIOS32(pll_info + 0x2e);766 767 if (rev > 10) {768 mpll->pll_in_min = RBIOS32(pll_info + 0x5a);769 mpll->pll_in_max = RBIOS32(pll_info + 0x5e);770 } else {771 /* ??? */772 mpll->pll_in_min = 40;773 mpll->pll_in_max = 500;774 }775 776 /* default sclk/mclk */777 sclk = RBIOS16(pll_info + 0xa);778 mclk = RBIOS16(pll_info + 0x8);779 if (sclk == 0)780 sclk = 200 * 100;781 if (mclk == 0)782 mclk = 200 * 100;783 784 rdev->clock.default_sclk = sclk;785 rdev->clock.default_mclk = mclk;786 787 if (RBIOS32(pll_info + 0x16))788 rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16);789 else790 rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */791 792 return true;793 }794 return false;795}796 797bool radeon_combios_sideport_present(struct radeon_device *rdev)798{799 struct drm_device *dev = rdev_to_drm(rdev);800 u16 igp_info;801 802 /* sideport is AMD only */803 if (rdev->family == CHIP_RS400)804 return false;805 806 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE);807 808 if (igp_info) {809 if (RBIOS16(igp_info + 0x4))810 return true;811 }812 return false;813}814 815static const uint32_t default_primarydac_adj[CHIP_LAST] = {816 0x00000808, /* r100 */817 0x00000808, /* rv100 */818 0x00000808, /* rs100 */819 0x00000808, /* rv200 */820 0x00000808, /* rs200 */821 0x00000808, /* r200 */822 0x00000808, /* rv250 */823 0x00000000, /* rs300 */824 0x00000808, /* rv280 */825 0x00000808, /* r300 */826 0x00000808, /* r350 */827 0x00000808, /* rv350 */828 0x00000808, /* rv380 */829 0x00000808, /* r420 */830 0x00000808, /* r423 */831 0x00000808, /* rv410 */832 0x00000000, /* rs400 */833 0x00000000, /* rs480 */834};835 836static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev,837 struct radeon_encoder_primary_dac *p_dac)838{839 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family];840 return;841}842 843struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct844 radeon_encoder845 *encoder)846{847 struct drm_device *dev = encoder->base.dev;848 struct radeon_device *rdev = dev->dev_private;849 uint16_t dac_info;850 uint8_t rev, bg, dac;851 struct radeon_encoder_primary_dac *p_dac;852 int found = 0;853 854 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac),855 GFP_KERNEL);856 857 if (!p_dac)858 return NULL;859 860 /* check CRT table */861 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);862 if (dac_info) {863 rev = RBIOS8(dac_info) & 0x3;864 if (rev < 2) {865 bg = RBIOS8(dac_info + 0x2) & 0xf;866 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf;867 p_dac->ps2_pdac_adj = (bg << 8) | (dac);868 } else {869 bg = RBIOS8(dac_info + 0x2) & 0xf;870 dac = RBIOS8(dac_info + 0x3) & 0xf;871 p_dac->ps2_pdac_adj = (bg << 8) | (dac);872 }873 /* if the values are zeros, use the table */874 if ((dac == 0) || (bg == 0))875 found = 0;876 else877 found = 1;878 }879 880 /* quirks */881 /* Radeon 7000 (RV100) */882 if (((rdev->pdev->device == 0x5159) &&883 (rdev->pdev->subsystem_vendor == 0x174B) &&884 (rdev->pdev->subsystem_device == 0x7c28)) ||885 /* Radeon 9100 (R200) */886 ((rdev->pdev->device == 0x514D) &&887 (rdev->pdev->subsystem_vendor == 0x174B) &&888 (rdev->pdev->subsystem_device == 0x7149))) {889 /* vbios value is bad, use the default */890 found = 0;891 }892 893 if (!found) /* fallback to defaults */894 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac);895 896 return p_dac;897}898 899enum radeon_tv_std900radeon_combios_get_tv_info(struct radeon_device *rdev)901{902 struct drm_device *dev = rdev_to_drm(rdev);903 uint16_t tv_info;904 enum radeon_tv_std tv_std = TV_STD_NTSC;905 906 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);907 if (tv_info) {908 if (RBIOS8(tv_info + 6) == 'T') {909 switch (RBIOS8(tv_info + 7) & 0xf) {910 case 1:911 tv_std = TV_STD_NTSC;912 DRM_DEBUG_KMS("Default TV standard: NTSC\n");913 break;914 case 2:915 tv_std = TV_STD_PAL;916 DRM_DEBUG_KMS("Default TV standard: PAL\n");917 break;918 case 3:919 tv_std = TV_STD_PAL_M;920 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");921 break;922 case 4:923 tv_std = TV_STD_PAL_60;924 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");925 break;926 case 5:927 tv_std = TV_STD_NTSC_J;928 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");929 break;930 case 6:931 tv_std = TV_STD_SCART_PAL;932 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n");933 break;934 default:935 tv_std = TV_STD_NTSC;936 DRM_DEBUG_KMS937 ("Unknown TV standard; defaulting to NTSC\n");938 break;939 }940 941 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) {942 case 0:943 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n");944 break;945 case 1:946 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n");947 break;948 case 2:949 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n");950 break;951 case 3:952 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n");953 break;954 default:955 break;956 }957 }958 }959 return tv_std;960}961 962static const uint32_t default_tvdac_adj[CHIP_LAST] = {963 0x00000000, /* r100 */964 0x00280000, /* rv100 */965 0x00000000, /* rs100 */966 0x00880000, /* rv200 */967 0x00000000, /* rs200 */968 0x00000000, /* r200 */969 0x00770000, /* rv250 */970 0x00290000, /* rs300 */971 0x00560000, /* rv280 */972 0x00780000, /* r300 */973 0x00770000, /* r350 */974 0x00780000, /* rv350 */975 0x00780000, /* rv380 */976 0x01080000, /* r420 */977 0x01080000, /* r423 */978 0x01080000, /* rv410 */979 0x00780000, /* rs400 */980 0x00780000, /* rs480 */981};982 983static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev,984 struct radeon_encoder_tv_dac *tv_dac)985{986 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family];987 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250))988 tv_dac->ps2_tvdac_adj = 0x00880000;989 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;990 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;991 return;992}993 994struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct995 radeon_encoder996 *encoder)997{998 struct drm_device *dev = encoder->base.dev;999 struct radeon_device *rdev = dev->dev_private;1000 uint16_t dac_info;1001 uint8_t rev, bg, dac;1002 struct radeon_encoder_tv_dac *tv_dac;1003 int found = 0;1004 1005 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);1006 if (!tv_dac)1007 return NULL;1008 1009 /* first check TV table */1010 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);1011 if (dac_info) {1012 rev = RBIOS8(dac_info + 0x3);1013 if (rev > 4) {1014 bg = RBIOS8(dac_info + 0xc) & 0xf;1015 dac = RBIOS8(dac_info + 0xd) & 0xf;1016 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);1017 1018 bg = RBIOS8(dac_info + 0xe) & 0xf;1019 dac = RBIOS8(dac_info + 0xf) & 0xf;1020 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);1021 1022 bg = RBIOS8(dac_info + 0x10) & 0xf;1023 dac = RBIOS8(dac_info + 0x11) & 0xf;1024 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);1025 /* if the values are all zeros, use the table */1026 if (tv_dac->ps2_tvdac_adj)1027 found = 1;1028 } else if (rev > 1) {1029 bg = RBIOS8(dac_info + 0xc) & 0xf;1030 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf;1031 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);1032 1033 bg = RBIOS8(dac_info + 0xd) & 0xf;1034 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf;1035 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);1036 1037 bg = RBIOS8(dac_info + 0xe) & 0xf;1038 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf;1039 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);1040 /* if the values are all zeros, use the table */1041 if (tv_dac->ps2_tvdac_adj)1042 found = 1;1043 }1044 tv_dac->tv_std = radeon_combios_get_tv_info(rdev);1045 }1046 if (!found) {1047 /* then check CRT table */1048 dac_info =1049 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);1050 if (dac_info) {1051 rev = RBIOS8(dac_info) & 0x3;1052 if (rev < 2) {1053 bg = RBIOS8(dac_info + 0x3) & 0xf;1054 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf;1055 tv_dac->ps2_tvdac_adj =1056 (bg << 16) | (dac << 20);1057 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;1058 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;1059 /* if the values are all zeros, use the table */1060 if (tv_dac->ps2_tvdac_adj)1061 found = 1;1062 } else {1063 bg = RBIOS8(dac_info + 0x4) & 0xf;1064 dac = RBIOS8(dac_info + 0x5) & 0xf;1065 tv_dac->ps2_tvdac_adj =1066 (bg << 16) | (dac << 20);1067 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj;1068 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj;1069 /* if the values are all zeros, use the table */1070 if (tv_dac->ps2_tvdac_adj)1071 found = 1;1072 }1073 } else {1074 DRM_INFO("No TV DAC info found in BIOS\n");1075 }1076 }1077 1078 if (!found) /* fallback to defaults */1079 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac);1080 1081 return tv_dac;1082}1083 1084static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct1085 radeon_device1086 *rdev)1087{1088 struct radeon_encoder_lvds *lvds;1089 uint32_t fp_vert_stretch, fp_horz_stretch;1090 uint32_t ppll_div_sel, ppll_val;1091 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);1092 1093 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);1094 1095 if (!lvds)1096 return NULL;1097 1098 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH);1099 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH);1100 1101 /* These should be fail-safe defaults, fingers crossed */1102 lvds->panel_pwr_delay = 200;1103 lvds->panel_vcc_delay = 2000;1104 1105 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);1106 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf;1107 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf;1108 1109 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE)1110 lvds->native_mode.vdisplay =1111 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >>1112 RADEON_VERT_PANEL_SHIFT) + 1;1113 else1114 lvds->native_mode.vdisplay =1115 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1;1116 1117 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE)1118 lvds->native_mode.hdisplay =1119 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >>1120 RADEON_HORZ_PANEL_SHIFT) + 1) * 8;1121 else1122 lvds->native_mode.hdisplay =1123 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8;1124 1125 if ((lvds->native_mode.hdisplay < 640) ||1126 (lvds->native_mode.vdisplay < 480)) {1127 lvds->native_mode.hdisplay = 640;1128 lvds->native_mode.vdisplay = 480;1129 }1130 1131 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3;1132 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel);1133 if ((ppll_val & 0x000707ff) == 0x1bb)1134 lvds->use_bios_dividers = false;1135 else {1136 lvds->panel_ref_divider =1137 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff;1138 lvds->panel_post_divider = (ppll_val >> 16) & 0x7;1139 lvds->panel_fb_divider = ppll_val & 0x7ff;1140 1141 if ((lvds->panel_ref_divider != 0) &&1142 (lvds->panel_fb_divider > 3))1143 lvds->use_bios_dividers = true;1144 }1145 lvds->panel_vcc_delay = 200;1146 1147 DRM_INFO("Panel info derived from registers\n");1148 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,1149 lvds->native_mode.vdisplay);1150 1151 return lvds;1152}1153 1154struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder1155 *encoder)1156{1157 struct drm_device *dev = encoder->base.dev;1158 struct radeon_device *rdev = dev->dev_private;1159 uint16_t lcd_info;1160 uint32_t panel_setup;1161 char stmp[30];1162 int tmp, i;1163 struct radeon_encoder_lvds *lvds = NULL;1164 1165 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);1166 1167 if (lcd_info) {1168 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL);1169 1170 if (!lvds)1171 return NULL;1172 1173 for (i = 0; i < 24; i++)1174 stmp[i] = RBIOS8(lcd_info + i + 1);1175 stmp[24] = 0;1176 1177 DRM_INFO("Panel ID String: %s\n", stmp);1178 1179 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19);1180 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b);1181 1182 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay,1183 lvds->native_mode.vdisplay);1184 1185 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c);1186 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000);1187 1188 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24);1189 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf;1190 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf;1191 1192 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e);1193 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30);1194 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31);1195 if ((lvds->panel_ref_divider != 0) &&1196 (lvds->panel_fb_divider > 3))1197 lvds->use_bios_dividers = true;1198 1199 panel_setup = RBIOS32(lcd_info + 0x39);1200 lvds->lvds_gen_cntl = 0xff00;1201 if (panel_setup & 0x1)1202 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT;1203 1204 if ((panel_setup >> 4) & 0x1)1205 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE;1206 1207 switch ((panel_setup >> 8) & 0x7) {1208 case 0:1209 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM;1210 break;1211 case 1:1212 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY;1213 break;1214 case 2:1215 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY;1216 break;1217 default:1218 break;1219 }1220 1221 if ((panel_setup >> 16) & 0x1)1222 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW;1223 1224 if ((panel_setup >> 17) & 0x1)1225 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW;1226 1227 if ((panel_setup >> 18) & 0x1)1228 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW;1229 1230 if ((panel_setup >> 23) & 0x1)1231 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL;1232 1233 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000);1234 1235 for (i = 0; i < 32; i++) {1236 tmp = RBIOS16(lcd_info + 64 + i * 2);1237 if (tmp == 0)1238 break;1239 1240 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) &&1241 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) {1242 u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8;1243 1244 if (hss > lvds->native_mode.hdisplay)1245 hss = (10 - 1) * 8;1246 1247 lvds->native_mode.htotal = lvds->native_mode.hdisplay +1248 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8;1249 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +1250 hss;1251 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +1252 (RBIOS8(tmp + 23) * 8);1253 1254 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +1255 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26));1256 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +1257 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26));1258 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +1259 ((RBIOS16(tmp + 28) & 0xf800) >> 11);1260 1261 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10;1262 lvds->native_mode.flags = 0;1263 /* set crtc values */1264 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);1265 1266 }1267 }1268 } else {1269 DRM_INFO("No panel info found in BIOS\n");1270 lvds = radeon_legacy_get_lvds_info_from_regs(rdev);1271 }1272 1273 if (lvds)1274 encoder->native_mode = lvds->native_mode;1275 return lvds;1276}1277 1278static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = {1279 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */1280 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */1281 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */1282 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */1283 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */1284 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */1285 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */1286 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */1287 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */1288 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */1289 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */1290 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */1291 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */1292 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */1293 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */1294 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */1295 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */1296 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */1297};1298 1299bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,1300 struct radeon_encoder_int_tmds *tmds)1301{1302 struct drm_device *dev = encoder->base.dev;1303 struct radeon_device *rdev = dev->dev_private;1304 int i;1305 1306 for (i = 0; i < 4; i++) {1307 tmds->tmds_pll[i].value =1308 default_tmds_pll[rdev->family][i].value;1309 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq;1310 }1311 1312 return true;1313}1314 1315bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,1316 struct radeon_encoder_int_tmds *tmds)1317{1318 struct drm_device *dev = encoder->base.dev;1319 struct radeon_device *rdev = dev->dev_private;1320 uint16_t tmds_info;1321 int i, n;1322 uint8_t ver;1323 1324 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);1325 1326 if (tmds_info) {1327 ver = RBIOS8(tmds_info);1328 DRM_DEBUG_KMS("DFP table revision: %d\n", ver);1329 if (ver == 3) {1330 n = RBIOS8(tmds_info + 5) + 1;1331 if (n > 4)1332 n = 4;1333 for (i = 0; i < n; i++) {1334 tmds->tmds_pll[i].value =1335 RBIOS32(tmds_info + i * 10 + 0x08);1336 tmds->tmds_pll[i].freq =1337 RBIOS16(tmds_info + i * 10 + 0x10);1338 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",1339 tmds->tmds_pll[i].freq,1340 tmds->tmds_pll[i].value);1341 }1342 } else if (ver == 4) {1343 int stride = 0;1344 n = RBIOS8(tmds_info + 5) + 1;1345 if (n > 4)1346 n = 4;1347 for (i = 0; i < n; i++) {1348 tmds->tmds_pll[i].value =1349 RBIOS32(tmds_info + stride + 0x08);1350 tmds->tmds_pll[i].freq =1351 RBIOS16(tmds_info + stride + 0x10);1352 if (i == 0)1353 stride += 10;1354 else1355 stride += 6;1356 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n",1357 tmds->tmds_pll[i].freq,1358 tmds->tmds_pll[i].value);1359 }1360 }1361 } else {1362 DRM_INFO("No TMDS info found in BIOS\n");1363 return false;1364 }1365 return true;1366}1367 1368bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,1369 struct radeon_encoder_ext_tmds *tmds)1370{1371 struct drm_device *dev = encoder->base.dev;1372 struct radeon_device *rdev = dev->dev_private;1373 struct radeon_i2c_bus_rec i2c_bus;1374 1375 /* default for macs */1376 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);1377 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);1378 1379 /* XXX some macs have duallink chips */1380 switch (rdev->mode_info.connector_table) {1381 case CT_POWERBOOK_EXTERNAL:1382 case CT_MINI_EXTERNAL:1383 default:1384 tmds->dvo_chip = DVO_SIL164;1385 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */1386 break;1387 }1388 1389 return true;1390}1391 1392bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,1393 struct radeon_encoder_ext_tmds *tmds)1394{1395 struct drm_device *dev = encoder->base.dev;1396 struct radeon_device *rdev = dev->dev_private;1397 uint16_t offset;1398 uint8_t ver;1399 enum radeon_combios_ddc gpio;1400 struct radeon_i2c_bus_rec i2c_bus;1401 1402 tmds->i2c_bus = NULL;1403 if (rdev->flags & RADEON_IS_IGP) {1404 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);1405 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);1406 tmds->dvo_chip = DVO_SIL164;1407 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */1408 } else {1409 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);1410 if (offset) {1411 ver = RBIOS8(offset);1412 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver);1413 tmds->slave_addr = RBIOS8(offset + 4 + 2);1414 tmds->slave_addr >>= 1; /* 7 bit addressing */1415 gpio = RBIOS8(offset + 4 + 3);1416 if (gpio == DDC_LCD) {1417 /* MM i2c */1418 i2c_bus.valid = true;1419 i2c_bus.hw_capable = true;1420 i2c_bus.mm_i2c = true;1421 i2c_bus.i2c_id = 0xa0;1422 } else1423 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);1424 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);1425 }1426 }1427 1428 if (!tmds->i2c_bus) {1429 DRM_INFO("No valid Ext TMDS info found in BIOS\n");1430 return false;1431 }1432 1433 return true;1434}1435 1436bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev)1437{1438 struct radeon_device *rdev = dev->dev_private;1439 struct radeon_i2c_bus_rec ddc_i2c;1440 struct radeon_hpd hpd;1441 1442 rdev->mode_info.connector_table = radeon_connector_table;1443 if (rdev->mode_info.connector_table == CT_NONE) {1444#ifdef CONFIG_PPC_PMAC1445 if (of_machine_is_compatible("PowerBook3,3")) {1446 /* powerbook with VGA */1447 rdev->mode_info.connector_table = CT_POWERBOOK_VGA;1448 } else if (of_machine_is_compatible("PowerBook3,4") ||1449 of_machine_is_compatible("PowerBook3,5")) {1450 /* powerbook with internal tmds */1451 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL;1452 } else if (of_machine_is_compatible("PowerBook5,1") ||1453 of_machine_is_compatible("PowerBook5,2") ||1454 of_machine_is_compatible("PowerBook5,3") ||1455 of_machine_is_compatible("PowerBook5,4") ||1456 of_machine_is_compatible("PowerBook5,5")) {1457 /* powerbook with external single link tmds (sil164) */1458 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;1459 } else if (of_machine_is_compatible("PowerBook5,6")) {1460 /* powerbook with external dual or single link tmds */1461 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;1462 } else if (of_machine_is_compatible("PowerBook5,7") ||1463 of_machine_is_compatible("PowerBook5,8") ||1464 of_machine_is_compatible("PowerBook5,9")) {1465 /* PowerBook6,2 ? */1466 /* powerbook with external dual link tmds (sil1178?) */1467 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL;1468 } else if (of_machine_is_compatible("PowerBook4,1") ||1469 of_machine_is_compatible("PowerBook4,2") ||1470 of_machine_is_compatible("PowerBook4,3") ||1471 of_machine_is_compatible("PowerBook6,3") ||1472 of_machine_is_compatible("PowerBook6,5") ||1473 of_machine_is_compatible("PowerBook6,7")) {1474 /* ibook */1475 rdev->mode_info.connector_table = CT_IBOOK;1476 } else if (of_machine_is_compatible("PowerMac3,5")) {1477 /* PowerMac G4 Silver radeon 7500 */1478 rdev->mode_info.connector_table = CT_MAC_G4_SILVER;1479 } else if (of_machine_is_compatible("PowerMac4,4")) {1480 /* emac */1481 rdev->mode_info.connector_table = CT_EMAC;1482 } else if (of_machine_is_compatible("PowerMac10,1")) {1483 /* mini with internal tmds */1484 rdev->mode_info.connector_table = CT_MINI_INTERNAL;1485 } else if (of_machine_is_compatible("PowerMac10,2")) {1486 /* mini with external tmds */1487 rdev->mode_info.connector_table = CT_MINI_EXTERNAL;1488 } else if (of_machine_is_compatible("PowerMac12,1")) {1489 /* PowerMac8,1 ? */1490 /* imac g5 isight */1491 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT;1492 } else if ((rdev->pdev->device == 0x4a48) &&1493 (rdev->pdev->subsystem_vendor == 0x1002) &&1494 (rdev->pdev->subsystem_device == 0x4a48)) {1495 /* Mac X800 */1496 rdev->mode_info.connector_table = CT_MAC_X800;1497 } else if ((of_machine_is_compatible("PowerMac7,2") ||1498 of_machine_is_compatible("PowerMac7,3")) &&1499 (rdev->pdev->device == 0x4150) &&1500 (rdev->pdev->subsystem_vendor == 0x1002) &&1501 (rdev->pdev->subsystem_device == 0x4150)) {1502 /* Mac G5 tower 9600 */1503 rdev->mode_info.connector_table = CT_MAC_G5_9600;1504 } else if ((rdev->pdev->device == 0x4c66) &&1505 (rdev->pdev->subsystem_vendor == 0x1002) &&1506 (rdev->pdev->subsystem_device == 0x4c66)) {1507 /* SAM440ep RV250 embedded board */1508 rdev->mode_info.connector_table = CT_SAM440EP;1509 } else1510#endif /* CONFIG_PPC_PMAC */1511#ifdef CONFIG_PPC641512 if (ASIC_IS_RN50(rdev))1513 rdev->mode_info.connector_table = CT_RN50_POWER;1514 else1515#endif1516 rdev->mode_info.connector_table = CT_GENERIC;1517 }1518 1519 switch (rdev->mode_info.connector_table) {1520 case CT_GENERIC:1521 DRM_INFO("Connector Table: %d (generic)\n",1522 rdev->mode_info.connector_table);1523 /* these are the most common settings */1524 if (rdev->flags & RADEON_SINGLE_CRTC) {1525 /* VGA - primary dac */1526 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);1527 hpd.hpd = RADEON_HPD_NONE;1528 radeon_add_legacy_encoder(dev,1529 radeon_get_encoder_enum(dev,1530 ATOM_DEVICE_CRT1_SUPPORT,1531 1),1532 ATOM_DEVICE_CRT1_SUPPORT);1533 radeon_add_legacy_connector(dev, 0,1534 ATOM_DEVICE_CRT1_SUPPORT,1535 DRM_MODE_CONNECTOR_VGA,1536 &ddc_i2c,1537 CONNECTOR_OBJECT_ID_VGA,1538 &hpd);1539 } else if (rdev->flags & RADEON_IS_MOBILITY) {1540 /* LVDS */1541 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);1542 hpd.hpd = RADEON_HPD_NONE;1543 radeon_add_legacy_encoder(dev,1544 radeon_get_encoder_enum(dev,1545 ATOM_DEVICE_LCD1_SUPPORT,1546 0),1547 ATOM_DEVICE_LCD1_SUPPORT);1548 radeon_add_legacy_connector(dev, 0,1549 ATOM_DEVICE_LCD1_SUPPORT,1550 DRM_MODE_CONNECTOR_LVDS,1551 &ddc_i2c,1552 CONNECTOR_OBJECT_ID_LVDS,1553 &hpd);1554 1555 /* VGA - primary dac */1556 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);1557 hpd.hpd = RADEON_HPD_NONE;1558 radeon_add_legacy_encoder(dev,1559 radeon_get_encoder_enum(dev,1560 ATOM_DEVICE_CRT1_SUPPORT,1561 1),1562 ATOM_DEVICE_CRT1_SUPPORT);1563 radeon_add_legacy_connector(dev, 1,1564 ATOM_DEVICE_CRT1_SUPPORT,1565 DRM_MODE_CONNECTOR_VGA,1566 &ddc_i2c,1567 CONNECTOR_OBJECT_ID_VGA,1568 &hpd);1569 } else {1570 /* DVI-I - tv dac, int tmds */1571 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);1572 hpd.hpd = RADEON_HPD_1;1573 radeon_add_legacy_encoder(dev,1574 radeon_get_encoder_enum(dev,1575 ATOM_DEVICE_DFP1_SUPPORT,1576 0),1577 ATOM_DEVICE_DFP1_SUPPORT);1578 radeon_add_legacy_encoder(dev,1579 radeon_get_encoder_enum(dev,1580 ATOM_DEVICE_CRT2_SUPPORT,1581 2),1582 ATOM_DEVICE_CRT2_SUPPORT);1583 radeon_add_legacy_connector(dev, 0,1584 ATOM_DEVICE_DFP1_SUPPORT |1585 ATOM_DEVICE_CRT2_SUPPORT,1586 DRM_MODE_CONNECTOR_DVII,1587 &ddc_i2c,1588 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,1589 &hpd);1590 1591 /* VGA - primary dac */1592 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);1593 hpd.hpd = RADEON_HPD_NONE;1594 radeon_add_legacy_encoder(dev,1595 radeon_get_encoder_enum(dev,1596 ATOM_DEVICE_CRT1_SUPPORT,1597 1),1598 ATOM_DEVICE_CRT1_SUPPORT);1599 radeon_add_legacy_connector(dev, 1,1600 ATOM_DEVICE_CRT1_SUPPORT,1601 DRM_MODE_CONNECTOR_VGA,1602 &ddc_i2c,1603 CONNECTOR_OBJECT_ID_VGA,1604 &hpd);1605 }1606 1607 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {1608 /* TV - tv dac */1609 ddc_i2c.valid = false;1610 hpd.hpd = RADEON_HPD_NONE;1611 radeon_add_legacy_encoder(dev,1612 radeon_get_encoder_enum(dev,1613 ATOM_DEVICE_TV1_SUPPORT,1614 2),1615 ATOM_DEVICE_TV1_SUPPORT);1616 radeon_add_legacy_connector(dev, 2,1617 ATOM_DEVICE_TV1_SUPPORT,1618 DRM_MODE_CONNECTOR_SVIDEO,1619 &ddc_i2c,1620 CONNECTOR_OBJECT_ID_SVIDEO,1621 &hpd);1622 }1623 break;1624 case CT_IBOOK:1625 DRM_INFO("Connector Table: %d (ibook)\n",1626 rdev->mode_info.connector_table);1627 /* LVDS */1628 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);1629 hpd.hpd = RADEON_HPD_NONE;1630 radeon_add_legacy_encoder(dev,1631 radeon_get_encoder_enum(dev,1632 ATOM_DEVICE_LCD1_SUPPORT,1633 0),1634 ATOM_DEVICE_LCD1_SUPPORT);1635 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,1636 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,1637 CONNECTOR_OBJECT_ID_LVDS,1638 &hpd);1639 /* VGA - TV DAC */1640 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);1641 hpd.hpd = RADEON_HPD_NONE;1642 radeon_add_legacy_encoder(dev,1643 radeon_get_encoder_enum(dev,1644 ATOM_DEVICE_CRT2_SUPPORT,1645 2),1646 ATOM_DEVICE_CRT2_SUPPORT);1647 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,1648 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,1649 CONNECTOR_OBJECT_ID_VGA,1650 &hpd);1651 /* TV - TV DAC */1652 ddc_i2c.valid = false;1653 hpd.hpd = RADEON_HPD_NONE;1654 radeon_add_legacy_encoder(dev,1655 radeon_get_encoder_enum(dev,1656 ATOM_DEVICE_TV1_SUPPORT,1657 2),1658 ATOM_DEVICE_TV1_SUPPORT);1659 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,1660 DRM_MODE_CONNECTOR_SVIDEO,1661 &ddc_i2c,1662 CONNECTOR_OBJECT_ID_SVIDEO,1663 &hpd);1664 break;1665 case CT_POWERBOOK_EXTERNAL:1666 DRM_INFO("Connector Table: %d (powerbook external tmds)\n",1667 rdev->mode_info.connector_table);1668 /* LVDS */1669 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);1670 hpd.hpd = RADEON_HPD_NONE;1671 radeon_add_legacy_encoder(dev,1672 radeon_get_encoder_enum(dev,1673 ATOM_DEVICE_LCD1_SUPPORT,1674 0),1675 ATOM_DEVICE_LCD1_SUPPORT);1676 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,1677 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,1678 CONNECTOR_OBJECT_ID_LVDS,1679 &hpd);1680 /* DVI-I - primary dac, ext tmds */1681 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);1682 hpd.hpd = RADEON_HPD_2; /* ??? */1683 radeon_add_legacy_encoder(dev,1684 radeon_get_encoder_enum(dev,1685 ATOM_DEVICE_DFP2_SUPPORT,1686 0),1687 ATOM_DEVICE_DFP2_SUPPORT);1688 radeon_add_legacy_encoder(dev,1689 radeon_get_encoder_enum(dev,1690 ATOM_DEVICE_CRT1_SUPPORT,1691 1),1692 ATOM_DEVICE_CRT1_SUPPORT);1693 /* XXX some are SL */1694 radeon_add_legacy_connector(dev, 1,1695 ATOM_DEVICE_DFP2_SUPPORT |1696 ATOM_DEVICE_CRT1_SUPPORT,1697 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,1698 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,1699 &hpd);1700 /* TV - TV DAC */1701 ddc_i2c.valid = false;1702 hpd.hpd = RADEON_HPD_NONE;1703 radeon_add_legacy_encoder(dev,1704 radeon_get_encoder_enum(dev,1705 ATOM_DEVICE_TV1_SUPPORT,1706 2),1707 ATOM_DEVICE_TV1_SUPPORT);1708 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,1709 DRM_MODE_CONNECTOR_SVIDEO,1710 &ddc_i2c,1711 CONNECTOR_OBJECT_ID_SVIDEO,1712 &hpd);1713 break;1714 case CT_POWERBOOK_INTERNAL:1715 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n",1716 rdev->mode_info.connector_table);1717 /* LVDS */1718 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);1719 hpd.hpd = RADEON_HPD_NONE;1720 radeon_add_legacy_encoder(dev,1721 radeon_get_encoder_enum(dev,1722 ATOM_DEVICE_LCD1_SUPPORT,1723 0),1724 ATOM_DEVICE_LCD1_SUPPORT);1725 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,1726 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,1727 CONNECTOR_OBJECT_ID_LVDS,1728 &hpd);1729 /* DVI-I - primary dac, int tmds */1730 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);1731 hpd.hpd = RADEON_HPD_1; /* ??? */1732 radeon_add_legacy_encoder(dev,1733 radeon_get_encoder_enum(dev,1734 ATOM_DEVICE_DFP1_SUPPORT,1735 0),1736 ATOM_DEVICE_DFP1_SUPPORT);1737 radeon_add_legacy_encoder(dev,1738 radeon_get_encoder_enum(dev,1739 ATOM_DEVICE_CRT1_SUPPORT,1740 1),1741 ATOM_DEVICE_CRT1_SUPPORT);1742 radeon_add_legacy_connector(dev, 1,1743 ATOM_DEVICE_DFP1_SUPPORT |1744 ATOM_DEVICE_CRT1_SUPPORT,1745 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,1746 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,1747 &hpd);1748 /* TV - TV DAC */1749 ddc_i2c.valid = false;1750 hpd.hpd = RADEON_HPD_NONE;1751 radeon_add_legacy_encoder(dev,1752 radeon_get_encoder_enum(dev,1753 ATOM_DEVICE_TV1_SUPPORT,1754 2),1755 ATOM_DEVICE_TV1_SUPPORT);1756 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,1757 DRM_MODE_CONNECTOR_SVIDEO,1758 &ddc_i2c,1759 CONNECTOR_OBJECT_ID_SVIDEO,1760 &hpd);1761 break;1762 case CT_POWERBOOK_VGA:1763 DRM_INFO("Connector Table: %d (powerbook vga)\n",1764 rdev->mode_info.connector_table);1765 /* LVDS */1766 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);1767 hpd.hpd = RADEON_HPD_NONE;1768 radeon_add_legacy_encoder(dev,1769 radeon_get_encoder_enum(dev,1770 ATOM_DEVICE_LCD1_SUPPORT,1771 0),1772 ATOM_DEVICE_LCD1_SUPPORT);1773 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,1774 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,1775 CONNECTOR_OBJECT_ID_LVDS,1776 &hpd);1777 /* VGA - primary dac */1778 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);1779 hpd.hpd = RADEON_HPD_NONE;1780 radeon_add_legacy_encoder(dev,1781 radeon_get_encoder_enum(dev,1782 ATOM_DEVICE_CRT1_SUPPORT,1783 1),1784 ATOM_DEVICE_CRT1_SUPPORT);1785 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,1786 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,1787 CONNECTOR_OBJECT_ID_VGA,1788 &hpd);1789 /* TV - TV DAC */1790 ddc_i2c.valid = false;1791 hpd.hpd = RADEON_HPD_NONE;1792 radeon_add_legacy_encoder(dev,1793 radeon_get_encoder_enum(dev,1794 ATOM_DEVICE_TV1_SUPPORT,1795 2),1796 ATOM_DEVICE_TV1_SUPPORT);1797 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,1798 DRM_MODE_CONNECTOR_SVIDEO,1799 &ddc_i2c,1800 CONNECTOR_OBJECT_ID_SVIDEO,1801 &hpd);1802 break;1803 case CT_MINI_EXTERNAL:1804 DRM_INFO("Connector Table: %d (mini external tmds)\n",1805 rdev->mode_info.connector_table);1806 /* DVI-I - tv dac, ext tmds */1807 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);1808 hpd.hpd = RADEON_HPD_2; /* ??? */1809 radeon_add_legacy_encoder(dev,1810 radeon_get_encoder_enum(dev,1811 ATOM_DEVICE_DFP2_SUPPORT,1812 0),1813 ATOM_DEVICE_DFP2_SUPPORT);1814 radeon_add_legacy_encoder(dev,1815 radeon_get_encoder_enum(dev,1816 ATOM_DEVICE_CRT2_SUPPORT,1817 2),1818 ATOM_DEVICE_CRT2_SUPPORT);1819 /* XXX are any DL? */1820 radeon_add_legacy_connector(dev, 0,1821 ATOM_DEVICE_DFP2_SUPPORT |1822 ATOM_DEVICE_CRT2_SUPPORT,1823 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,1824 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,1825 &hpd);1826 /* TV - TV DAC */1827 ddc_i2c.valid = false;1828 hpd.hpd = RADEON_HPD_NONE;1829 radeon_add_legacy_encoder(dev,1830 radeon_get_encoder_enum(dev,1831 ATOM_DEVICE_TV1_SUPPORT,1832 2),1833 ATOM_DEVICE_TV1_SUPPORT);1834 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,1835 DRM_MODE_CONNECTOR_SVIDEO,1836 &ddc_i2c,1837 CONNECTOR_OBJECT_ID_SVIDEO,1838 &hpd);1839 break;1840 case CT_MINI_INTERNAL:1841 DRM_INFO("Connector Table: %d (mini internal tmds)\n",1842 rdev->mode_info.connector_table);1843 /* DVI-I - tv dac, int tmds */1844 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);1845 hpd.hpd = RADEON_HPD_1; /* ??? */1846 radeon_add_legacy_encoder(dev,1847 radeon_get_encoder_enum(dev,1848 ATOM_DEVICE_DFP1_SUPPORT,1849 0),1850 ATOM_DEVICE_DFP1_SUPPORT);1851 radeon_add_legacy_encoder(dev,1852 radeon_get_encoder_enum(dev,1853 ATOM_DEVICE_CRT2_SUPPORT,1854 2),1855 ATOM_DEVICE_CRT2_SUPPORT);1856 radeon_add_legacy_connector(dev, 0,1857 ATOM_DEVICE_DFP1_SUPPORT |1858 ATOM_DEVICE_CRT2_SUPPORT,1859 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,1860 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,1861 &hpd);1862 /* TV - TV DAC */1863 ddc_i2c.valid = false;1864 hpd.hpd = RADEON_HPD_NONE;1865 radeon_add_legacy_encoder(dev,1866 radeon_get_encoder_enum(dev,1867 ATOM_DEVICE_TV1_SUPPORT,1868 2),1869 ATOM_DEVICE_TV1_SUPPORT);1870 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT,1871 DRM_MODE_CONNECTOR_SVIDEO,1872 &ddc_i2c,1873 CONNECTOR_OBJECT_ID_SVIDEO,1874 &hpd);1875 break;1876 case CT_IMAC_G5_ISIGHT:1877 DRM_INFO("Connector Table: %d (imac g5 isight)\n",1878 rdev->mode_info.connector_table);1879 /* DVI-D - int tmds */1880 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);1881 hpd.hpd = RADEON_HPD_1; /* ??? */1882 radeon_add_legacy_encoder(dev,1883 radeon_get_encoder_enum(dev,1884 ATOM_DEVICE_DFP1_SUPPORT,1885 0),1886 ATOM_DEVICE_DFP1_SUPPORT);1887 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT,1888 DRM_MODE_CONNECTOR_DVID, &ddc_i2c,1889 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,1890 &hpd);1891 /* VGA - tv dac */1892 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);1893 hpd.hpd = RADEON_HPD_NONE;1894 radeon_add_legacy_encoder(dev,1895 radeon_get_encoder_enum(dev,1896 ATOM_DEVICE_CRT2_SUPPORT,1897 2),1898 ATOM_DEVICE_CRT2_SUPPORT);1899 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,1900 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,1901 CONNECTOR_OBJECT_ID_VGA,1902 &hpd);1903 /* TV - TV DAC */1904 ddc_i2c.valid = false;1905 hpd.hpd = RADEON_HPD_NONE;1906 radeon_add_legacy_encoder(dev,1907 radeon_get_encoder_enum(dev,1908 ATOM_DEVICE_TV1_SUPPORT,1909 2),1910 ATOM_DEVICE_TV1_SUPPORT);1911 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,1912 DRM_MODE_CONNECTOR_SVIDEO,1913 &ddc_i2c,1914 CONNECTOR_OBJECT_ID_SVIDEO,1915 &hpd);1916 break;1917 case CT_EMAC:1918 DRM_INFO("Connector Table: %d (emac)\n",1919 rdev->mode_info.connector_table);1920 /* VGA - primary dac */1921 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);1922 hpd.hpd = RADEON_HPD_NONE;1923 radeon_add_legacy_encoder(dev,1924 radeon_get_encoder_enum(dev,1925 ATOM_DEVICE_CRT1_SUPPORT,1926 1),1927 ATOM_DEVICE_CRT1_SUPPORT);1928 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,1929 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,1930 CONNECTOR_OBJECT_ID_VGA,1931 &hpd);1932 /* VGA - tv dac */1933 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);1934 hpd.hpd = RADEON_HPD_NONE;1935 radeon_add_legacy_encoder(dev,1936 radeon_get_encoder_enum(dev,1937 ATOM_DEVICE_CRT2_SUPPORT,1938 2),1939 ATOM_DEVICE_CRT2_SUPPORT);1940 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,1941 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,1942 CONNECTOR_OBJECT_ID_VGA,1943 &hpd);1944 /* TV - TV DAC */1945 ddc_i2c.valid = false;1946 hpd.hpd = RADEON_HPD_NONE;1947 radeon_add_legacy_encoder(dev,1948 radeon_get_encoder_enum(dev,1949 ATOM_DEVICE_TV1_SUPPORT,1950 2),1951 ATOM_DEVICE_TV1_SUPPORT);1952 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,1953 DRM_MODE_CONNECTOR_SVIDEO,1954 &ddc_i2c,1955 CONNECTOR_OBJECT_ID_SVIDEO,1956 &hpd);1957 break;1958 case CT_RN50_POWER:1959 DRM_INFO("Connector Table: %d (rn50-power)\n",1960 rdev->mode_info.connector_table);1961 /* VGA - primary dac */1962 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);1963 hpd.hpd = RADEON_HPD_NONE;1964 radeon_add_legacy_encoder(dev,1965 radeon_get_encoder_enum(dev,1966 ATOM_DEVICE_CRT1_SUPPORT,1967 1),1968 ATOM_DEVICE_CRT1_SUPPORT);1969 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT,1970 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,1971 CONNECTOR_OBJECT_ID_VGA,1972 &hpd);1973 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);1974 hpd.hpd = RADEON_HPD_NONE;1975 radeon_add_legacy_encoder(dev,1976 radeon_get_encoder_enum(dev,1977 ATOM_DEVICE_CRT2_SUPPORT,1978 2),1979 ATOM_DEVICE_CRT2_SUPPORT);1980 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT,1981 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,1982 CONNECTOR_OBJECT_ID_VGA,1983 &hpd);1984 break;1985 case CT_MAC_X800:1986 DRM_INFO("Connector Table: %d (mac x800)\n",1987 rdev->mode_info.connector_table);1988 /* DVI - primary dac, internal tmds */1989 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);1990 hpd.hpd = RADEON_HPD_1; /* ??? */1991 radeon_add_legacy_encoder(dev,1992 radeon_get_encoder_enum(dev,1993 ATOM_DEVICE_DFP1_SUPPORT,1994 0),1995 ATOM_DEVICE_DFP1_SUPPORT);1996 radeon_add_legacy_encoder(dev,1997 radeon_get_encoder_enum(dev,1998 ATOM_DEVICE_CRT1_SUPPORT,1999 1),2000 ATOM_DEVICE_CRT1_SUPPORT);2001 radeon_add_legacy_connector(dev, 0,2002 ATOM_DEVICE_DFP1_SUPPORT |2003 ATOM_DEVICE_CRT1_SUPPORT,2004 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,2005 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,2006 &hpd);2007 /* DVI - tv dac, dvo */2008 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);2009 hpd.hpd = RADEON_HPD_2; /* ??? */2010 radeon_add_legacy_encoder(dev,2011 radeon_get_encoder_enum(dev,2012 ATOM_DEVICE_DFP2_SUPPORT,2013 0),2014 ATOM_DEVICE_DFP2_SUPPORT);2015 radeon_add_legacy_encoder(dev,2016 radeon_get_encoder_enum(dev,2017 ATOM_DEVICE_CRT2_SUPPORT,2018 2),2019 ATOM_DEVICE_CRT2_SUPPORT);2020 radeon_add_legacy_connector(dev, 1,2021 ATOM_DEVICE_DFP2_SUPPORT |2022 ATOM_DEVICE_CRT2_SUPPORT,2023 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,2024 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I,2025 &hpd);2026 break;2027 case CT_MAC_G5_9600:2028 DRM_INFO("Connector Table: %d (mac g5 9600)\n",2029 rdev->mode_info.connector_table);2030 /* DVI - tv dac, dvo */2031 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);2032 hpd.hpd = RADEON_HPD_1; /* ??? */2033 radeon_add_legacy_encoder(dev,2034 radeon_get_encoder_enum(dev,2035 ATOM_DEVICE_DFP2_SUPPORT,2036 0),2037 ATOM_DEVICE_DFP2_SUPPORT);2038 radeon_add_legacy_encoder(dev,2039 radeon_get_encoder_enum(dev,2040 ATOM_DEVICE_CRT2_SUPPORT,2041 2),2042 ATOM_DEVICE_CRT2_SUPPORT);2043 radeon_add_legacy_connector(dev, 0,2044 ATOM_DEVICE_DFP2_SUPPORT |2045 ATOM_DEVICE_CRT2_SUPPORT,2046 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,2047 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,2048 &hpd);2049 /* ADC - primary dac, internal tmds */2050 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);2051 hpd.hpd = RADEON_HPD_2; /* ??? */2052 radeon_add_legacy_encoder(dev,2053 radeon_get_encoder_enum(dev,2054 ATOM_DEVICE_DFP1_SUPPORT,2055 0),2056 ATOM_DEVICE_DFP1_SUPPORT);2057 radeon_add_legacy_encoder(dev,2058 radeon_get_encoder_enum(dev,2059 ATOM_DEVICE_CRT1_SUPPORT,2060 1),2061 ATOM_DEVICE_CRT1_SUPPORT);2062 radeon_add_legacy_connector(dev, 1,2063 ATOM_DEVICE_DFP1_SUPPORT |2064 ATOM_DEVICE_CRT1_SUPPORT,2065 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,2066 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,2067 &hpd);2068 /* TV - TV DAC */2069 ddc_i2c.valid = false;2070 hpd.hpd = RADEON_HPD_NONE;2071 radeon_add_legacy_encoder(dev,2072 radeon_get_encoder_enum(dev,2073 ATOM_DEVICE_TV1_SUPPORT,2074 2),2075 ATOM_DEVICE_TV1_SUPPORT);2076 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,2077 DRM_MODE_CONNECTOR_SVIDEO,2078 &ddc_i2c,2079 CONNECTOR_OBJECT_ID_SVIDEO,2080 &hpd);2081 break;2082 case CT_SAM440EP:2083 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n",2084 rdev->mode_info.connector_table);2085 /* LVDS */2086 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0);2087 hpd.hpd = RADEON_HPD_NONE;2088 radeon_add_legacy_encoder(dev,2089 radeon_get_encoder_enum(dev,2090 ATOM_DEVICE_LCD1_SUPPORT,2091 0),2092 ATOM_DEVICE_LCD1_SUPPORT);2093 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT,2094 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c,2095 CONNECTOR_OBJECT_ID_LVDS,2096 &hpd);2097 /* DVI-I - secondary dac, int tmds */2098 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);2099 hpd.hpd = RADEON_HPD_1; /* ??? */2100 radeon_add_legacy_encoder(dev,2101 radeon_get_encoder_enum(dev,2102 ATOM_DEVICE_DFP1_SUPPORT,2103 0),2104 ATOM_DEVICE_DFP1_SUPPORT);2105 radeon_add_legacy_encoder(dev,2106 radeon_get_encoder_enum(dev,2107 ATOM_DEVICE_CRT2_SUPPORT,2108 2),2109 ATOM_DEVICE_CRT2_SUPPORT);2110 radeon_add_legacy_connector(dev, 1,2111 ATOM_DEVICE_DFP1_SUPPORT |2112 ATOM_DEVICE_CRT2_SUPPORT,2113 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,2114 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,2115 &hpd);2116 /* VGA - primary dac */2117 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);2118 hpd.hpd = RADEON_HPD_NONE;2119 radeon_add_legacy_encoder(dev,2120 radeon_get_encoder_enum(dev,2121 ATOM_DEVICE_CRT1_SUPPORT,2122 1),2123 ATOM_DEVICE_CRT1_SUPPORT);2124 radeon_add_legacy_connector(dev, 2,2125 ATOM_DEVICE_CRT1_SUPPORT,2126 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,2127 CONNECTOR_OBJECT_ID_VGA,2128 &hpd);2129 /* TV - TV DAC */2130 ddc_i2c.valid = false;2131 hpd.hpd = RADEON_HPD_NONE;2132 radeon_add_legacy_encoder(dev,2133 radeon_get_encoder_enum(dev,2134 ATOM_DEVICE_TV1_SUPPORT,2135 2),2136 ATOM_DEVICE_TV1_SUPPORT);2137 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT,2138 DRM_MODE_CONNECTOR_SVIDEO,2139 &ddc_i2c,2140 CONNECTOR_OBJECT_ID_SVIDEO,2141 &hpd);2142 break;2143 case CT_MAC_G4_SILVER:2144 DRM_INFO("Connector Table: %d (mac g4 silver)\n",2145 rdev->mode_info.connector_table);2146 /* DVI-I - tv dac, int tmds */2147 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);2148 hpd.hpd = RADEON_HPD_1; /* ??? */2149 radeon_add_legacy_encoder(dev,2150 radeon_get_encoder_enum(dev,2151 ATOM_DEVICE_DFP1_SUPPORT,2152 0),2153 ATOM_DEVICE_DFP1_SUPPORT);2154 radeon_add_legacy_encoder(dev,2155 radeon_get_encoder_enum(dev,2156 ATOM_DEVICE_CRT2_SUPPORT,2157 2),2158 ATOM_DEVICE_CRT2_SUPPORT);2159 radeon_add_legacy_connector(dev, 0,2160 ATOM_DEVICE_DFP1_SUPPORT |2161 ATOM_DEVICE_CRT2_SUPPORT,2162 DRM_MODE_CONNECTOR_DVII, &ddc_i2c,2163 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,2164 &hpd);2165 /* VGA - primary dac */2166 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);2167 hpd.hpd = RADEON_HPD_NONE;2168 radeon_add_legacy_encoder(dev,2169 radeon_get_encoder_enum(dev,2170 ATOM_DEVICE_CRT1_SUPPORT,2171 1),2172 ATOM_DEVICE_CRT1_SUPPORT);2173 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT,2174 DRM_MODE_CONNECTOR_VGA, &ddc_i2c,2175 CONNECTOR_OBJECT_ID_VGA,2176 &hpd);2177 /* TV - TV DAC */2178 ddc_i2c.valid = false;2179 hpd.hpd = RADEON_HPD_NONE;2180 radeon_add_legacy_encoder(dev,2181 radeon_get_encoder_enum(dev,2182 ATOM_DEVICE_TV1_SUPPORT,2183 2),2184 ATOM_DEVICE_TV1_SUPPORT);2185 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT,2186 DRM_MODE_CONNECTOR_SVIDEO,2187 &ddc_i2c,2188 CONNECTOR_OBJECT_ID_SVIDEO,2189 &hpd);2190 break;2191 default:2192 DRM_INFO("Connector table: %d (invalid)\n",2193 rdev->mode_info.connector_table);2194 return false;2195 }2196 2197 radeon_link_encoder_connector(dev);2198 2199 return true;2200}2201 2202static bool radeon_apply_legacy_quirks(struct drm_device *dev,2203 int bios_index,2204 enum radeon_combios_connector2205 *legacy_connector,2206 struct radeon_i2c_bus_rec *ddc_i2c,2207 struct radeon_hpd *hpd)2208{2209 struct radeon_device *rdev = dev->dev_private;2210 2211 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs,2212 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */2213 if (rdev->pdev->device == 0x515e &&2214 rdev->pdev->subsystem_vendor == 0x1014) {2215 if (*legacy_connector == CONNECTOR_CRT_LEGACY &&2216 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC)2217 return false;2218 }2219 2220 /* X300 card with extra non-existent DVI port */2221 if (rdev->pdev->device == 0x5B60 &&2222 rdev->pdev->subsystem_vendor == 0x17af &&2223 rdev->pdev->subsystem_device == 0x201e && bios_index == 2) {2224 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY)2225 return false;2226 }2227 2228 return true;2229}2230 2231static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev)2232{2233 struct radeon_device *rdev = dev->dev_private;2234 2235 /* Acer 5102 has non-existent TV port */2236 if (rdev->pdev->device == 0x5975 &&2237 rdev->pdev->subsystem_vendor == 0x1025 &&2238 rdev->pdev->subsystem_device == 0x009f)2239 return false;2240 2241 /* HP dc5750 has non-existent TV port */2242 if (rdev->pdev->device == 0x5974 &&2243 rdev->pdev->subsystem_vendor == 0x103c &&2244 rdev->pdev->subsystem_device == 0x280a)2245 return false;2246 2247 /* MSI S270 has non-existent TV port */2248 if (rdev->pdev->device == 0x5955 &&2249 rdev->pdev->subsystem_vendor == 0x1462 &&2250 rdev->pdev->subsystem_device == 0x0131)2251 return false;2252 2253 return true;2254}2255 2256static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d)2257{2258 struct radeon_device *rdev = dev->dev_private;2259 uint32_t ext_tmds_info;2260 2261 if (rdev->flags & RADEON_IS_IGP) {2262 if (is_dvi_d)2263 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;2264 else2265 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;2266 }2267 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);2268 if (ext_tmds_info) {2269 uint8_t rev = RBIOS8(ext_tmds_info);2270 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5);2271 if (rev >= 3) {2272 if (is_dvi_d)2273 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;2274 else2275 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;2276 } else {2277 if (flags & 1) {2278 if (is_dvi_d)2279 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;2280 else2281 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;2282 }2283 }2284 }2285 if (is_dvi_d)2286 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;2287 else2288 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;2289}2290 2291bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)2292{2293 struct radeon_device *rdev = dev->dev_private;2294 uint32_t conn_info, entry, devices;2295 uint16_t tmp, connector_object_id;2296 enum radeon_combios_ddc ddc_type;2297 enum radeon_combios_connector connector;2298 int i = 0;2299 struct radeon_i2c_bus_rec ddc_i2c;2300 struct radeon_hpd hpd;2301 2302 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE);2303 if (conn_info) {2304 for (i = 0; i < 4; i++) {2305 entry = conn_info + 2 + i * 2;2306 2307 if (!RBIOS16(entry))2308 break;2309 2310 tmp = RBIOS16(entry);2311 2312 connector = (tmp >> 12) & 0xf;2313 2314 ddc_type = (tmp >> 8) & 0xf;2315 if (ddc_type == 5)2316 ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev);2317 else2318 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0);2319 2320 switch (connector) {2321 case CONNECTOR_PROPRIETARY_LEGACY:2322 case CONNECTOR_DVI_I_LEGACY:2323 case CONNECTOR_DVI_D_LEGACY:2324 if ((tmp >> 4) & 0x1)2325 hpd.hpd = RADEON_HPD_2;2326 else2327 hpd.hpd = RADEON_HPD_1;2328 break;2329 default:2330 hpd.hpd = RADEON_HPD_NONE;2331 break;2332 }2333 2334 if (!radeon_apply_legacy_quirks(dev, i, &connector,2335 &ddc_i2c, &hpd))2336 continue;2337 2338 switch (connector) {2339 case CONNECTOR_PROPRIETARY_LEGACY:2340 if ((tmp >> 4) & 0x1)2341 devices = ATOM_DEVICE_DFP2_SUPPORT;2342 else2343 devices = ATOM_DEVICE_DFP1_SUPPORT;2344 radeon_add_legacy_encoder(dev,2345 radeon_get_encoder_enum2346 (dev, devices, 0),2347 devices);2348 radeon_add_legacy_connector(dev, i, devices,2349 legacy_connector_convert2350 [connector],2351 &ddc_i2c,2352 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D,2353 &hpd);2354 break;2355 case CONNECTOR_CRT_LEGACY:2356 if (tmp & 0x1) {2357 devices = ATOM_DEVICE_CRT2_SUPPORT;2358 radeon_add_legacy_encoder(dev,2359 radeon_get_encoder_enum2360 (dev,2361 ATOM_DEVICE_CRT2_SUPPORT,2362 2),2363 ATOM_DEVICE_CRT2_SUPPORT);2364 } else {2365 devices = ATOM_DEVICE_CRT1_SUPPORT;2366 radeon_add_legacy_encoder(dev,2367 radeon_get_encoder_enum2368 (dev,2369 ATOM_DEVICE_CRT1_SUPPORT,2370 1),2371 ATOM_DEVICE_CRT1_SUPPORT);2372 }2373 radeon_add_legacy_connector(dev,2374 i,2375 devices,2376 legacy_connector_convert2377 [connector],2378 &ddc_i2c,2379 CONNECTOR_OBJECT_ID_VGA,2380 &hpd);2381 break;2382 case CONNECTOR_DVI_I_LEGACY:2383 devices = 0;2384 if (tmp & 0x1) {2385 devices |= ATOM_DEVICE_CRT2_SUPPORT;2386 radeon_add_legacy_encoder(dev,2387 radeon_get_encoder_enum2388 (dev,2389 ATOM_DEVICE_CRT2_SUPPORT,2390 2),2391 ATOM_DEVICE_CRT2_SUPPORT);2392 } else {2393 devices |= ATOM_DEVICE_CRT1_SUPPORT;2394 radeon_add_legacy_encoder(dev,2395 radeon_get_encoder_enum2396 (dev,2397 ATOM_DEVICE_CRT1_SUPPORT,2398 1),2399 ATOM_DEVICE_CRT1_SUPPORT);2400 }2401 /* RV100 board with external TDMS bit mis-set.2402 * Actually uses internal TMDS, clear the bit.2403 */2404 if (rdev->pdev->device == 0x5159 &&2405 rdev->pdev->subsystem_vendor == 0x1014 &&2406 rdev->pdev->subsystem_device == 0x029A) {2407 tmp &= ~(1 << 4);2408 }2409 if ((tmp >> 4) & 0x1) {2410 devices |= ATOM_DEVICE_DFP2_SUPPORT;2411 radeon_add_legacy_encoder(dev,2412 radeon_get_encoder_enum2413 (dev,2414 ATOM_DEVICE_DFP2_SUPPORT,2415 0),2416 ATOM_DEVICE_DFP2_SUPPORT);2417 connector_object_id = combios_check_dl_dvi(dev, 0);2418 } else {2419 devices |= ATOM_DEVICE_DFP1_SUPPORT;2420 radeon_add_legacy_encoder(dev,2421 radeon_get_encoder_enum2422 (dev,2423 ATOM_DEVICE_DFP1_SUPPORT,2424 0),2425 ATOM_DEVICE_DFP1_SUPPORT);2426 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;2427 }2428 radeon_add_legacy_connector(dev,2429 i,2430 devices,2431 legacy_connector_convert2432 [connector],2433 &ddc_i2c,2434 connector_object_id,2435 &hpd);2436 break;2437 case CONNECTOR_DVI_D_LEGACY:2438 if ((tmp >> 4) & 0x1) {2439 devices = ATOM_DEVICE_DFP2_SUPPORT;2440 connector_object_id = combios_check_dl_dvi(dev, 1);2441 } else {2442 devices = ATOM_DEVICE_DFP1_SUPPORT;2443 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;2444 }2445 radeon_add_legacy_encoder(dev,2446 radeon_get_encoder_enum2447 (dev, devices, 0),2448 devices);2449 radeon_add_legacy_connector(dev, i, devices,2450 legacy_connector_convert2451 [connector],2452 &ddc_i2c,2453 connector_object_id,2454 &hpd);2455 break;2456 case CONNECTOR_CTV_LEGACY:2457 case CONNECTOR_STV_LEGACY:2458 radeon_add_legacy_encoder(dev,2459 radeon_get_encoder_enum2460 (dev,2461 ATOM_DEVICE_TV1_SUPPORT,2462 2),2463 ATOM_DEVICE_TV1_SUPPORT);2464 radeon_add_legacy_connector(dev, i,2465 ATOM_DEVICE_TV1_SUPPORT,2466 legacy_connector_convert2467 [connector],2468 &ddc_i2c,2469 CONNECTOR_OBJECT_ID_SVIDEO,2470 &hpd);2471 break;2472 default:2473 DRM_ERROR("Unknown connector type: %d\n",2474 connector);2475 continue;2476 }2477 2478 }2479 } else {2480 uint16_t tmds_info =2481 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE);2482 if (tmds_info) {2483 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n");2484 2485 radeon_add_legacy_encoder(dev,2486 radeon_get_encoder_enum(dev,2487 ATOM_DEVICE_CRT1_SUPPORT,2488 1),2489 ATOM_DEVICE_CRT1_SUPPORT);2490 radeon_add_legacy_encoder(dev,2491 radeon_get_encoder_enum(dev,2492 ATOM_DEVICE_DFP1_SUPPORT,2493 0),2494 ATOM_DEVICE_DFP1_SUPPORT);2495 2496 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);2497 hpd.hpd = RADEON_HPD_1;2498 radeon_add_legacy_connector(dev,2499 0,2500 ATOM_DEVICE_CRT1_SUPPORT |2501 ATOM_DEVICE_DFP1_SUPPORT,2502 DRM_MODE_CONNECTOR_DVII,2503 &ddc_i2c,2504 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I,2505 &hpd);2506 } else {2507 uint16_t crt_info =2508 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE);2509 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n");2510 if (crt_info) {2511 radeon_add_legacy_encoder(dev,2512 radeon_get_encoder_enum(dev,2513 ATOM_DEVICE_CRT1_SUPPORT,2514 1),2515 ATOM_DEVICE_CRT1_SUPPORT);2516 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);2517 hpd.hpd = RADEON_HPD_NONE;2518 radeon_add_legacy_connector(dev,2519 0,2520 ATOM_DEVICE_CRT1_SUPPORT,2521 DRM_MODE_CONNECTOR_VGA,2522 &ddc_i2c,2523 CONNECTOR_OBJECT_ID_VGA,2524 &hpd);2525 } else {2526 DRM_DEBUG_KMS("No connector info found\n");2527 return false;2528 }2529 }2530 }2531 2532 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) {2533 uint16_t lcd_info =2534 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE);2535 if (lcd_info) {2536 uint16_t lcd_ddc_info =2537 combios_get_table_offset(dev,2538 COMBIOS_LCD_DDC_INFO_TABLE);2539 2540 radeon_add_legacy_encoder(dev,2541 radeon_get_encoder_enum(dev,2542 ATOM_DEVICE_LCD1_SUPPORT,2543 0),2544 ATOM_DEVICE_LCD1_SUPPORT);2545 2546 if (lcd_ddc_info) {2547 ddc_type = RBIOS8(lcd_ddc_info + 2);2548 switch (ddc_type) {2549 case DDC_LCD:2550 ddc_i2c =2551 combios_setup_i2c_bus(rdev,2552 DDC_LCD,2553 RBIOS32(lcd_ddc_info + 3),2554 RBIOS32(lcd_ddc_info + 7));2555 radeon_i2c_add(rdev, &ddc_i2c, "LCD");2556 break;2557 case DDC_GPIO:2558 ddc_i2c =2559 combios_setup_i2c_bus(rdev,2560 DDC_GPIO,2561 RBIOS32(lcd_ddc_info + 3),2562 RBIOS32(lcd_ddc_info + 7));2563 radeon_i2c_add(rdev, &ddc_i2c, "LCD");2564 break;2565 default:2566 ddc_i2c =2567 combios_setup_i2c_bus(rdev, ddc_type, 0, 0);2568 break;2569 }2570 DRM_DEBUG_KMS("LCD DDC Info Table found!\n");2571 } else2572 ddc_i2c.valid = false;2573 2574 hpd.hpd = RADEON_HPD_NONE;2575 radeon_add_legacy_connector(dev,2576 5,2577 ATOM_DEVICE_LCD1_SUPPORT,2578 DRM_MODE_CONNECTOR_LVDS,2579 &ddc_i2c,2580 CONNECTOR_OBJECT_ID_LVDS,2581 &hpd);2582 }2583 }2584 2585 /* check TV table */2586 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) {2587 uint32_t tv_info =2588 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE);2589 if (tv_info) {2590 if (RBIOS8(tv_info + 6) == 'T') {2591 if (radeon_apply_legacy_tv_quirks(dev)) {2592 hpd.hpd = RADEON_HPD_NONE;2593 ddc_i2c.valid = false;2594 radeon_add_legacy_encoder(dev,2595 radeon_get_encoder_enum2596 (dev,2597 ATOM_DEVICE_TV1_SUPPORT,2598 2),2599 ATOM_DEVICE_TV1_SUPPORT);2600 radeon_add_legacy_connector(dev, 6,2601 ATOM_DEVICE_TV1_SUPPORT,2602 DRM_MODE_CONNECTOR_SVIDEO,2603 &ddc_i2c,2604 CONNECTOR_OBJECT_ID_SVIDEO,2605 &hpd);2606 }2607 }2608 }2609 }2610 2611 radeon_link_encoder_connector(dev);2612 2613 return true;2614}2615 2616static const char *thermal_controller_names[] = {2617 "NONE",2618 "lm63",2619 "adm1032",2620};2621 2622void radeon_combios_get_power_modes(struct radeon_device *rdev)2623{2624 struct drm_device *dev = rdev_to_drm(rdev);2625 u16 offset, misc, misc2 = 0;2626 u8 rev, tmp;2627 int state_index = 0;2628 struct radeon_i2c_bus_rec i2c_bus;2629 2630 rdev->pm.default_power_state_index = -1;2631 2632 /* allocate 2 power states */2633 rdev->pm.power_state = kcalloc(2, sizeof(struct radeon_power_state),2634 GFP_KERNEL);2635 if (rdev->pm.power_state) {2636 /* allocate 1 clock mode per state */2637 rdev->pm.power_state[0].clock_info =2638 kcalloc(1, sizeof(struct radeon_pm_clock_info),2639 GFP_KERNEL);2640 rdev->pm.power_state[1].clock_info =2641 kcalloc(1, sizeof(struct radeon_pm_clock_info),2642 GFP_KERNEL);2643 if (!rdev->pm.power_state[0].clock_info ||2644 !rdev->pm.power_state[1].clock_info)2645 goto pm_failed;2646 } else2647 goto pm_failed;2648 2649 /* check for a thermal chip */2650 offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);2651 if (offset) {2652 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;2653 2654 rev = RBIOS8(offset);2655 2656 if (rev == 0) {2657 thermal_controller = RBIOS8(offset + 3);2658 gpio = RBIOS8(offset + 4) & 0x3f;2659 i2c_addr = RBIOS8(offset + 5);2660 } else if (rev == 1) {2661 thermal_controller = RBIOS8(offset + 4);2662 gpio = RBIOS8(offset + 5) & 0x3f;2663 i2c_addr = RBIOS8(offset + 6);2664 } else if (rev == 2) {2665 thermal_controller = RBIOS8(offset + 4);2666 gpio = RBIOS8(offset + 5) & 0x3f;2667 i2c_addr = RBIOS8(offset + 6);2668 clk_bit = RBIOS8(offset + 0xa);2669 data_bit = RBIOS8(offset + 0xb);2670 }2671 if ((thermal_controller > 0) && (thermal_controller < 3)) {2672 DRM_INFO("Possible %s thermal controller at 0x%02x\n",2673 thermal_controller_names[thermal_controller],2674 i2c_addr >> 1);2675 if (gpio == DDC_LCD) {2676 /* MM i2c */2677 i2c_bus.valid = true;2678 i2c_bus.hw_capable = true;2679 i2c_bus.mm_i2c = true;2680 i2c_bus.i2c_id = 0xa0;2681 } else if (gpio == DDC_GPIO)2682 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);2683 else2684 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);2685 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);2686 if (rdev->pm.i2c_bus) {2687 struct i2c_board_info info = { };2688 const char *name = thermal_controller_names[thermal_controller];2689 info.addr = i2c_addr >> 1;2690 strscpy(info.type, name, sizeof(info.type));2691 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);2692 }2693 }2694 } else {2695 /* boards with a thermal chip, but no overdrive table */2696 2697 /* Asus 9600xt has an f75375 on the monid bus */2698 if ((rdev->pdev->device == 0x4152) &&2699 (rdev->pdev->subsystem_vendor == 0x1043) &&2700 (rdev->pdev->subsystem_device == 0xc002)) {2701 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);2702 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);2703 if (rdev->pm.i2c_bus) {2704 struct i2c_board_info info = { };2705 const char *name = "f75375";2706 info.addr = 0x28;2707 strscpy(info.type, name, sizeof(info.type));2708 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);2709 DRM_INFO("Possible %s thermal controller at 0x%02x\n",2710 name, info.addr);2711 }2712 }2713 }2714 2715 if (rdev->flags & RADEON_IS_MOBILITY) {2716 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);2717 if (offset) {2718 rev = RBIOS8(offset);2719 /* power mode 0 tends to be the only valid one */2720 rdev->pm.power_state[state_index].num_clock_modes = 1;2721 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2);2722 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6);2723 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||2724 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))2725 goto default_mode;2726 rdev->pm.power_state[state_index].type =2727 POWER_STATE_TYPE_BATTERY;2728 misc = RBIOS16(offset + 0x5 + 0x0);2729 if (rev > 4)2730 misc2 = RBIOS16(offset + 0x5 + 0xe);2731 rdev->pm.power_state[state_index].misc = misc;2732 rdev->pm.power_state[state_index].misc2 = misc2;2733 if (misc & 0x4) {2734 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO;2735 if (misc & 0x8)2736 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =2737 true;2738 else2739 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =2740 false;2741 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true;2742 if (rev < 6) {2743 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =2744 RBIOS16(offset + 0x5 + 0xb) * 4;2745 tmp = RBIOS8(offset + 0x5 + 0xd);2746 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);2747 } else {2748 u8 entries = RBIOS8(offset + 0x5 + 0xb);2749 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc);2750 if (entries && voltage_table_offset) {2751 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg =2752 RBIOS16(voltage_table_offset) * 4;2753 tmp = RBIOS8(voltage_table_offset + 0x2);2754 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp);2755 } else2756 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false;2757 }2758 switch ((misc2 & 0x700) >> 8) {2759 case 0:2760 default:2761 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0;2762 break;2763 case 1:2764 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33;2765 break;2766 case 2:2767 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66;2768 break;2769 case 3:2770 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99;2771 break;2772 case 4:2773 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132;2774 break;2775 }2776 } else2777 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;2778 if (rev > 6)2779 rdev->pm.power_state[state_index].pcie_lanes =2780 RBIOS8(offset + 0x5 + 0x10);2781 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;2782 state_index++;2783 } else {2784 /* XXX figure out some good default low power mode for mobility cards w/out power tables */2785 }2786 } else {2787 /* XXX figure out some good default low power mode for desktop cards */2788 }2789 2790default_mode:2791 /* add the default mode */2792 rdev->pm.power_state[state_index].type =2793 POWER_STATE_TYPE_DEFAULT;2794 rdev->pm.power_state[state_index].num_clock_modes = 1;2795 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;2796 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;2797 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0];2798 if ((state_index > 0) &&2799 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO))2800 rdev->pm.power_state[state_index].clock_info[0].voltage =2801 rdev->pm.power_state[0].clock_info[0].voltage;2802 else2803 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;2804 rdev->pm.power_state[state_index].pcie_lanes = 16;2805 rdev->pm.power_state[state_index].flags = 0;2806 rdev->pm.default_power_state_index = state_index;2807 rdev->pm.num_power_states = state_index + 1;2808 2809 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;2810 rdev->pm.current_clock_mode_index = 0;2811 return;2812 2813pm_failed:2814 rdev->pm.default_power_state_index = state_index;2815 rdev->pm.num_power_states = 0;2816 2817 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;2818 rdev->pm.current_clock_mode_index = 0;2819}2820 2821void radeon_external_tmds_setup(struct drm_encoder *encoder)2822{2823 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);2824 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;2825 2826 if (!tmds)2827 return;2828 2829 switch (tmds->dvo_chip) {2830 case DVO_SIL164:2831 /* sil 164 */2832 radeon_i2c_put_byte(tmds->i2c_bus,2833 tmds->slave_addr,2834 0x08, 0x30);2835 radeon_i2c_put_byte(tmds->i2c_bus,2836 tmds->slave_addr,2837 0x09, 0x00);2838 radeon_i2c_put_byte(tmds->i2c_bus,2839 tmds->slave_addr,2840 0x0a, 0x90);2841 radeon_i2c_put_byte(tmds->i2c_bus,2842 tmds->slave_addr,2843 0x0c, 0x89);2844 radeon_i2c_put_byte(tmds->i2c_bus,2845 tmds->slave_addr,2846 0x08, 0x3b);2847 break;2848 case DVO_SIL1178:2849 /* sil 1178 - untested */2850 /*2851 * 0x0f, 0x442852 * 0x0f, 0x4c2853 * 0x0e, 0x012854 * 0x0a, 0x802855 * 0x09, 0x302856 * 0x0c, 0xc92857 * 0x0d, 0x702858 * 0x08, 0x322859 * 0x08, 0x332860 */2861 break;2862 default:2863 break;2864 }2865 2866}2867 2868bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder)2869{2870 struct drm_device *dev = encoder->dev;2871 struct radeon_device *rdev = dev->dev_private;2872 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);2873 uint16_t offset;2874 uint8_t blocks, slave_addr, rev;2875 uint32_t index, id;2876 uint32_t reg, val, and_mask, or_mask;2877 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;2878 2879 if (!tmds)2880 return false;2881 2882 if (rdev->flags & RADEON_IS_IGP) {2883 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE);2884 rev = RBIOS8(offset);2885 if (offset) {2886 rev = RBIOS8(offset);2887 if (rev > 1) {2888 blocks = RBIOS8(offset + 3);2889 index = offset + 4;2890 while (blocks > 0) {2891 id = RBIOS16(index);2892 index += 2;2893 switch (id >> 13) {2894 case 0:2895 reg = (id & 0x1fff) * 4;2896 val = RBIOS32(index);2897 index += 4;2898 WREG32(reg, val);2899 break;2900 case 2:2901 reg = (id & 0x1fff) * 4;2902 and_mask = RBIOS32(index);2903 index += 4;2904 or_mask = RBIOS32(index);2905 index += 4;2906 val = RREG32(reg);2907 val = (val & and_mask) | or_mask;2908 WREG32(reg, val);2909 break;2910 case 3:2911 val = RBIOS16(index);2912 index += 2;2913 udelay(val);2914 break;2915 case 4:2916 val = RBIOS16(index);2917 index += 2;2918 mdelay(val);2919 break;2920 case 6:2921 slave_addr = id & 0xff;2922 slave_addr >>= 1; /* 7 bit addressing */2923 index++;2924 reg = RBIOS8(index);2925 index++;2926 val = RBIOS8(index);2927 index++;2928 radeon_i2c_put_byte(tmds->i2c_bus,2929 slave_addr,2930 reg, val);2931 break;2932 default:2933 DRM_ERROR("Unknown id %d\n", id >> 13);2934 break;2935 }2936 blocks--;2937 }2938 return true;2939 }2940 }2941 } else {2942 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE);2943 if (offset) {2944 index = offset + 10;2945 id = RBIOS16(index);2946 while (id != 0xffff) {2947 index += 2;2948 switch (id >> 13) {2949 case 0:2950 reg = (id & 0x1fff) * 4;2951 val = RBIOS32(index);2952 WREG32(reg, val);2953 break;2954 case 2:2955 reg = (id & 0x1fff) * 4;2956 and_mask = RBIOS32(index);2957 index += 4;2958 or_mask = RBIOS32(index);2959 index += 4;2960 val = RREG32(reg);2961 val = (val & and_mask) | or_mask;2962 WREG32(reg, val);2963 break;2964 case 4:2965 val = RBIOS16(index);2966 index += 2;2967 udelay(val);2968 break;2969 case 5:2970 reg = id & 0x1fff;2971 and_mask = RBIOS32(index);2972 index += 4;2973 or_mask = RBIOS32(index);2974 index += 4;2975 val = RREG32_PLL(reg);2976 val = (val & and_mask) | or_mask;2977 WREG32_PLL(reg, val);2978 break;2979 case 6:2980 reg = id & 0x1fff;2981 val = RBIOS8(index);2982 index += 1;2983 radeon_i2c_put_byte(tmds->i2c_bus,2984 tmds->slave_addr,2985 reg, val);2986 break;2987 default:2988 DRM_ERROR("Unknown id %d\n", id >> 13);2989 break;2990 }2991 id = RBIOS16(index);2992 }2993 return true;2994 }2995 }2996 return false;2997}2998 2999static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset)3000{3001 struct radeon_device *rdev = dev->dev_private;3002 3003 if (offset) {3004 while (RBIOS16(offset)) {3005 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13);3006 uint32_t addr = (RBIOS16(offset) & 0x1fff);3007 uint32_t val, and_mask, or_mask;3008 uint32_t tmp;3009 3010 offset += 2;3011 switch (cmd) {3012 case 0:3013 val = RBIOS32(offset);3014 offset += 4;3015 WREG32(addr, val);3016 break;3017 case 1:3018 val = RBIOS32(offset);3019 offset += 4;3020 WREG32(addr, val);3021 break;3022 case 2:3023 and_mask = RBIOS32(offset);3024 offset += 4;3025 or_mask = RBIOS32(offset);3026 offset += 4;3027 tmp = RREG32(addr);3028 tmp &= and_mask;3029 tmp |= or_mask;3030 WREG32(addr, tmp);3031 break;3032 case 3:3033 and_mask = RBIOS32(offset);3034 offset += 4;3035 or_mask = RBIOS32(offset);3036 offset += 4;3037 tmp = RREG32(addr);3038 tmp &= and_mask;3039 tmp |= or_mask;3040 WREG32(addr, tmp);3041 break;3042 case 4:3043 val = RBIOS16(offset);3044 offset += 2;3045 udelay(val);3046 break;3047 case 5:3048 val = RBIOS16(offset);3049 offset += 2;3050 switch (addr) {3051 case 8:3052 while (val--) {3053 if (!3054 (RREG32_PLL3055 (RADEON_CLK_PWRMGT_CNTL) &3056 RADEON_MC_BUSY))3057 break;3058 }3059 break;3060 case 9:3061 while (val--) {3062 if ((RREG32(RADEON_MC_STATUS) &3063 RADEON_MC_IDLE))3064 break;3065 }3066 break;3067 default:3068 break;3069 }3070 break;3071 default:3072 break;3073 }3074 }3075 }3076}3077 3078static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset)3079{3080 struct radeon_device *rdev = dev->dev_private;3081 3082 if (offset) {3083 while (RBIOS8(offset)) {3084 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6);3085 uint8_t addr = (RBIOS8(offset) & 0x3f);3086 uint32_t val, shift, tmp;3087 uint32_t and_mask, or_mask;3088 3089 offset++;3090 switch (cmd) {3091 case 0:3092 val = RBIOS32(offset);3093 offset += 4;3094 WREG32_PLL(addr, val);3095 break;3096 case 1:3097 shift = RBIOS8(offset) * 8;3098 offset++;3099 and_mask = RBIOS8(offset) << shift;3100 and_mask |= ~(0xff << shift);3101 offset++;3102 or_mask = RBIOS8(offset) << shift;3103 offset++;3104 tmp = RREG32_PLL(addr);3105 tmp &= and_mask;3106 tmp |= or_mask;3107 WREG32_PLL(addr, tmp);3108 break;3109 case 2:3110 case 3:3111 tmp = 1000;3112 switch (addr) {3113 case 1:3114 udelay(150);3115 break;3116 case 2:3117 mdelay(1);3118 break;3119 case 3:3120 while (tmp--) {3121 if (!3122 (RREG32_PLL3123 (RADEON_CLK_PWRMGT_CNTL) &3124 RADEON_MC_BUSY))3125 break;3126 }3127 break;3128 case 4:3129 while (tmp--) {3130 if (RREG32_PLL3131 (RADEON_CLK_PWRMGT_CNTL) &3132 RADEON_DLL_READY)3133 break;3134 }3135 break;3136 case 5:3137 tmp =3138 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL);3139 if (tmp & RADEON_CG_NO1_DEBUG_0) {3140#if 03141 uint32_t mclk_cntl =3142 RREG32_PLL3143 (RADEON_MCLK_CNTL);3144 mclk_cntl &= 0xffff0000;3145 /*mclk_cntl |= 0x00001111;*//* ??? */3146 WREG32_PLL(RADEON_MCLK_CNTL,3147 mclk_cntl);3148 mdelay(10);3149#endif3150 WREG32_PLL3151 (RADEON_CLK_PWRMGT_CNTL,3152 tmp &3153 ~RADEON_CG_NO1_DEBUG_0);3154 mdelay(10);3155 }3156 break;3157 default:3158 break;3159 }3160 break;3161 default:3162 break;3163 }3164 }3165 }3166}3167 3168static void combios_parse_ram_reset_table(struct drm_device *dev,3169 uint16_t offset)3170{3171 struct radeon_device *rdev = dev->dev_private;3172 uint32_t tmp;3173 3174 if (offset) {3175 uint8_t val = RBIOS8(offset);3176 while (val != 0xff) {3177 offset++;3178 3179 if (val == 0x0f) {3180 uint32_t channel_complete_mask;3181 3182 if (ASIC_IS_R300(rdev))3183 channel_complete_mask =3184 R300_MEM_PWRUP_COMPLETE;3185 else3186 channel_complete_mask =3187 RADEON_MEM_PWRUP_COMPLETE;3188 tmp = 20000;3189 while (tmp--) {3190 if ((RREG32(RADEON_MEM_STR_CNTL) &3191 channel_complete_mask) ==3192 channel_complete_mask)3193 break;3194 }3195 } else {3196 uint32_t or_mask = RBIOS16(offset);3197 offset += 2;3198 3199 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);3200 tmp &= RADEON_SDRAM_MODE_MASK;3201 tmp |= or_mask;3202 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);3203 3204 or_mask = val << 24;3205 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG);3206 tmp &= RADEON_B3MEM_RESET_MASK;3207 tmp |= or_mask;3208 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp);3209 }3210 val = RBIOS8(offset);3211 }3212 }3213}3214 3215static uint32_t combios_detect_ram(struct drm_device *dev, int ram,3216 int mem_addr_mapping)3217{3218 struct radeon_device *rdev = dev->dev_private;3219 uint32_t mem_cntl;3220 uint32_t mem_size;3221 uint32_t addr = 0;3222 3223 mem_cntl = RREG32(RADEON_MEM_CNTL);3224 if (mem_cntl & RV100_HALF_MODE)3225 ram /= 2;3226 mem_size = ram;3227 mem_cntl &= ~(0xff << 8);3228 mem_cntl |= (mem_addr_mapping & 0xff) << 8;3229 WREG32(RADEON_MEM_CNTL, mem_cntl);3230 RREG32(RADEON_MEM_CNTL);3231 3232 /* sdram reset ? */3233 3234 /* something like this???? */3235 while (ram--) {3236 addr = ram * 1024 * 1024;3237 /* write to each page */3238 WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef);3239 /* read back and verify */3240 if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef)3241 return 0;3242 }3243 3244 return mem_size;3245}3246 3247static void combios_write_ram_size(struct drm_device *dev)3248{3249 struct radeon_device *rdev = dev->dev_private;3250 uint8_t rev;3251 uint16_t offset;3252 uint32_t mem_size = 0;3253 uint32_t mem_cntl = 0;3254 3255 /* should do something smarter here I guess... */3256 if (rdev->flags & RADEON_IS_IGP)3257 return;3258 3259 /* first check detected mem table */3260 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE);3261 if (offset) {3262 rev = RBIOS8(offset);3263 if (rev < 3) {3264 mem_cntl = RBIOS32(offset + 1);3265 mem_size = RBIOS16(offset + 5);3266 if ((rdev->family < CHIP_R200) &&3267 !ASIC_IS_RN50(rdev))3268 WREG32(RADEON_MEM_CNTL, mem_cntl);3269 }3270 }3271 3272 if (!mem_size) {3273 offset =3274 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE);3275 if (offset) {3276 rev = RBIOS8(offset - 1);3277 if (rev < 1) {3278 if ((rdev->family < CHIP_R200)3279 && !ASIC_IS_RN50(rdev)) {3280 int ram = 0;3281 int mem_addr_mapping = 0;3282 3283 while (RBIOS8(offset)) {3284 ram = RBIOS8(offset);3285 mem_addr_mapping =3286 RBIOS8(offset + 1);3287 if (mem_addr_mapping != 0x25)3288 ram *= 2;3289 mem_size =3290 combios_detect_ram(dev, ram,3291 mem_addr_mapping);3292 if (mem_size)3293 break;3294 offset += 2;3295 }3296 } else3297 mem_size = RBIOS8(offset);3298 } else {3299 mem_size = RBIOS8(offset);3300 mem_size *= 2; /* convert to MB */3301 }3302 }3303 }3304 3305 mem_size *= (1024 * 1024); /* convert to bytes */3306 WREG32(RADEON_CONFIG_MEMSIZE, mem_size);3307}3308 3309void radeon_combios_asic_init(struct drm_device *dev)3310{3311 struct radeon_device *rdev = dev->dev_private;3312 uint16_t table;3313 3314 /* port hardcoded mac stuff from radeonfb */3315 if (rdev->bios == NULL)3316 return;3317 3318 /* ASIC INIT 1 */3319 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE);3320 if (table)3321 combios_parse_mmio_table(dev, table);3322 3323 /* PLL INIT */3324 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE);3325 if (table)3326 combios_parse_pll_table(dev, table);3327 3328 /* ASIC INIT 2 */3329 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE);3330 if (table)3331 combios_parse_mmio_table(dev, table);3332 3333 if (!(rdev->flags & RADEON_IS_IGP)) {3334 /* ASIC INIT 4 */3335 table =3336 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE);3337 if (table)3338 combios_parse_mmio_table(dev, table);3339 3340 /* RAM RESET */3341 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE);3342 if (table)3343 combios_parse_ram_reset_table(dev, table);3344 3345 /* ASIC INIT 3 */3346 table =3347 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE);3348 if (table)3349 combios_parse_mmio_table(dev, table);3350 3351 /* write CONFIG_MEMSIZE */3352 combios_write_ram_size(dev);3353 }3354 3355 /* quirk for rs4xx HP nx6125 laptop to make it resume3356 * - it hangs on resume inside the dynclk 1 table.3357 */3358 if (rdev->family == CHIP_RS480 &&3359 rdev->pdev->subsystem_vendor == 0x103c &&3360 rdev->pdev->subsystem_device == 0x308b)3361 return;3362 3363 /* quirk for rs4xx HP dv5000 laptop to make it resume3364 * - it hangs on resume inside the dynclk 1 table.3365 */3366 if (rdev->family == CHIP_RS480 &&3367 rdev->pdev->subsystem_vendor == 0x103c &&3368 rdev->pdev->subsystem_device == 0x30a4)3369 return;3370 3371 /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume3372 * - it hangs on resume inside the dynclk 1 table.3373 */3374 if (rdev->family == CHIP_RS480 &&3375 rdev->pdev->subsystem_vendor == 0x103c &&3376 rdev->pdev->subsystem_device == 0x30ae)3377 return;3378 3379 /* quirk for rs4xx HP Compaq dc5750 Small Form Factor to make it resume3380 * - it hangs on resume inside the dynclk 1 table.3381 */3382 if (rdev->family == CHIP_RS480 &&3383 rdev->pdev->subsystem_vendor == 0x103c &&3384 rdev->pdev->subsystem_device == 0x280a)3385 return;3386 /* quirk for rs4xx Toshiba Sattellite L20-183 latop to make it resume3387 * - it hangs on resume inside the dynclk 1 table.3388 */3389 if (rdev->family == CHIP_RS400 &&3390 rdev->pdev->subsystem_vendor == 0x1179 &&3391 rdev->pdev->subsystem_device == 0xff31)3392 return;3393 3394 /* DYN CLK 1 */3395 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);3396 if (table)3397 combios_parse_pll_table(dev, table);3398 3399}3400 3401void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev)3402{3403 struct radeon_device *rdev = dev->dev_private;3404 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch;3405 3406 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);3407 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);3408 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH);3409 3410 /* let the bios control the backlight */3411 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN;3412 3413 /* tell the bios not to handle mode switching */3414 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS |3415 RADEON_ACC_MODE_CHANGE);3416 3417 /* tell the bios a driver is loaded */3418 bios_7_scratch |= RADEON_DRV_LOADED;3419 3420 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);3421 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);3422 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch);3423}3424 3425void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock)3426{3427 struct drm_device *dev = encoder->dev;3428 struct radeon_device *rdev = dev->dev_private;3429 uint32_t bios_6_scratch;3430 3431 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);3432 3433 if (lock)3434 bios_6_scratch |= RADEON_DRIVER_CRITICAL;3435 else3436 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL;3437 3438 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);3439}3440 3441void3442radeon_combios_connected_scratch_regs(struct drm_connector *connector,3443 struct drm_encoder *encoder,3444 bool connected)3445{3446 struct drm_device *dev = connector->dev;3447 struct radeon_device *rdev = dev->dev_private;3448 struct radeon_connector *radeon_connector =3449 to_radeon_connector(connector);3450 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);3451 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH);3452 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);3453 3454 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&3455 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {3456 if (connected) {3457 DRM_DEBUG_KMS("TV1 connected\n");3458 /* fix me */3459 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO;3460 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */3461 bios_5_scratch |= RADEON_TV1_ON;3462 bios_5_scratch |= RADEON_ACC_REQ_TV1;3463 } else {3464 DRM_DEBUG_KMS("TV1 disconnected\n");3465 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK;3466 bios_5_scratch &= ~RADEON_TV1_ON;3467 bios_5_scratch &= ~RADEON_ACC_REQ_TV1;3468 }3469 }3470 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&3471 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {3472 if (connected) {3473 DRM_DEBUG_KMS("LCD1 connected\n");3474 bios_4_scratch |= RADEON_LCD1_ATTACHED;3475 bios_5_scratch |= RADEON_LCD1_ON;3476 bios_5_scratch |= RADEON_ACC_REQ_LCD1;3477 } else {3478 DRM_DEBUG_KMS("LCD1 disconnected\n");3479 bios_4_scratch &= ~RADEON_LCD1_ATTACHED;3480 bios_5_scratch &= ~RADEON_LCD1_ON;3481 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1;3482 }3483 }3484 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&3485 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {3486 if (connected) {3487 DRM_DEBUG_KMS("CRT1 connected\n");3488 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR;3489 bios_5_scratch |= RADEON_CRT1_ON;3490 bios_5_scratch |= RADEON_ACC_REQ_CRT1;3491 } else {3492 DRM_DEBUG_KMS("CRT1 disconnected\n");3493 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK;3494 bios_5_scratch &= ~RADEON_CRT1_ON;3495 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1;3496 }3497 }3498 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&3499 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {3500 if (connected) {3501 DRM_DEBUG_KMS("CRT2 connected\n");3502 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR;3503 bios_5_scratch |= RADEON_CRT2_ON;3504 bios_5_scratch |= RADEON_ACC_REQ_CRT2;3505 } else {3506 DRM_DEBUG_KMS("CRT2 disconnected\n");3507 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK;3508 bios_5_scratch &= ~RADEON_CRT2_ON;3509 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2;3510 }3511 }3512 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&3513 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {3514 if (connected) {3515 DRM_DEBUG_KMS("DFP1 connected\n");3516 bios_4_scratch |= RADEON_DFP1_ATTACHED;3517 bios_5_scratch |= RADEON_DFP1_ON;3518 bios_5_scratch |= RADEON_ACC_REQ_DFP1;3519 } else {3520 DRM_DEBUG_KMS("DFP1 disconnected\n");3521 bios_4_scratch &= ~RADEON_DFP1_ATTACHED;3522 bios_5_scratch &= ~RADEON_DFP1_ON;3523 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1;3524 }3525 }3526 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&3527 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {3528 if (connected) {3529 DRM_DEBUG_KMS("DFP2 connected\n");3530 bios_4_scratch |= RADEON_DFP2_ATTACHED;3531 bios_5_scratch |= RADEON_DFP2_ON;3532 bios_5_scratch |= RADEON_ACC_REQ_DFP2;3533 } else {3534 DRM_DEBUG_KMS("DFP2 disconnected\n");3535 bios_4_scratch &= ~RADEON_DFP2_ATTACHED;3536 bios_5_scratch &= ~RADEON_DFP2_ON;3537 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2;3538 }3539 }3540 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch);3541 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);3542}3543 3544void3545radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)3546{3547 struct drm_device *dev = encoder->dev;3548 struct radeon_device *rdev = dev->dev_private;3549 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);3550 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH);3551 3552 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {3553 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK;3554 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT);3555 }3556 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {3557 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK;3558 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT);3559 }3560 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {3561 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK;3562 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT);3563 }3564 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {3565 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK;3566 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT);3567 }3568 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {3569 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK;3570 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT);3571 }3572 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {3573 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK;3574 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT);3575 }3576 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch);3577}3578 3579void3580radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)3581{3582 struct drm_device *dev = encoder->dev;3583 struct radeon_device *rdev = dev->dev_private;3584 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);3585 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);3586 3587 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) {3588 if (on)3589 bios_6_scratch |= RADEON_TV_DPMS_ON;3590 else3591 bios_6_scratch &= ~RADEON_TV_DPMS_ON;3592 }3593 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {3594 if (on)3595 bios_6_scratch |= RADEON_CRT_DPMS_ON;3596 else3597 bios_6_scratch &= ~RADEON_CRT_DPMS_ON;3598 }3599 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {3600 if (on)3601 bios_6_scratch |= RADEON_LCD_DPMS_ON;3602 else3603 bios_6_scratch &= ~RADEON_LCD_DPMS_ON;3604 }3605 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {3606 if (on)3607 bios_6_scratch |= RADEON_DFP_DPMS_ON;3608 else3609 bios_6_scratch &= ~RADEON_DFP_DPMS_ON;3610 }3611 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);3612}3613