1102 lines · c
1/*2 * Copyright 2009 Jerome Glisse.3 * All Rights Reserved.4 *5 * Permission is hereby granted, free of charge, to any person obtaining a6 * copy of this software and associated documentation files (the7 * "Software"), to deal in the Software without restriction, including8 * without limitation the rights to use, copy, modify, merge, publish,9 * distribute, sub license, and/or sell copies of the Software, and to10 * permit persons to whom the Software is furnished to do so, subject to11 * the following conditions:12 *13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE19 * USE OR OTHER DEALINGS IN THE SOFTWARE.20 *21 * The above copyright notice and this permission notice (including the22 * next paragraph) shall be included in all copies or substantial portions23 * of the Software.24 *25 */26/*27 * Authors:28 * Jerome Glisse <glisse@freedesktop.org>29 * Dave Airlie30 */31 32#include <linux/atomic.h>33#include <linux/debugfs.h>34#include <linux/firmware.h>35#include <linux/kref.h>36#include <linux/sched/signal.h>37#include <linux/seq_file.h>38#include <linux/slab.h>39#include <linux/wait.h>40 41#include <drm/drm_device.h>42#include <drm/drm_file.h>43 44#include "radeon.h"45#include "radeon_reg.h"46#include "radeon_trace.h"47 48/*49 * Fences mark an event in the GPUs pipeline and are used50 * for GPU/CPU synchronization. When the fence is written,51 * it is expected that all buffers associated with that fence52 * are no longer in use by the associated ring on the GPU and53 * that the relevant GPU caches have been flushed. Whether54 * we use a scratch register or memory location depends on the asic55 * and whether writeback is enabled.56 */57 58/**59 * radeon_fence_write - write a fence value60 *61 * @rdev: radeon_device pointer62 * @seq: sequence number to write63 * @ring: ring index the fence is associated with64 *65 * Writes a fence value to memory or a scratch register (all asics).66 */67static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)68{69 struct radeon_fence_driver *drv = &rdev->fence_drv[ring];70 71 if (likely(rdev->wb.enabled || !drv->scratch_reg)) {72 if (drv->cpu_addr)73 *drv->cpu_addr = cpu_to_le32(seq);74 } else {75 WREG32(drv->scratch_reg, seq);76 }77}78 79/**80 * radeon_fence_read - read a fence value81 *82 * @rdev: radeon_device pointer83 * @ring: ring index the fence is associated with84 *85 * Reads a fence value from memory or a scratch register (all asics).86 * Returns the value of the fence read from memory or register.87 */88static u32 radeon_fence_read(struct radeon_device *rdev, int ring)89{90 struct radeon_fence_driver *drv = &rdev->fence_drv[ring];91 u32 seq = 0;92 93 if (likely(rdev->wb.enabled || !drv->scratch_reg)) {94 if (drv->cpu_addr)95 seq = le32_to_cpu(*drv->cpu_addr);96 else97 seq = lower_32_bits(atomic64_read(&drv->last_seq));98 } else {99 seq = RREG32(drv->scratch_reg);100 }101 return seq;102}103 104/**105 * radeon_fence_schedule_check - schedule lockup check106 *107 * @rdev: radeon_device pointer108 * @ring: ring index we should work with109 *110 * Queues a delayed work item to check for lockups.111 */112static void radeon_fence_schedule_check(struct radeon_device *rdev, int ring)113{114 /*115 * Do not reset the timer here with mod_delayed_work,116 * this can livelock in an interaction with TTM delayed destroy.117 */118 queue_delayed_work(system_power_efficient_wq,119 &rdev->fence_drv[ring].lockup_work,120 RADEON_FENCE_JIFFIES_TIMEOUT);121}122 123/**124 * radeon_fence_emit - emit a fence on the requested ring125 *126 * @rdev: radeon_device pointer127 * @fence: radeon fence object128 * @ring: ring index the fence is associated with129 *130 * Emits a fence command on the requested ring (all asics).131 * Returns 0 on success, -ENOMEM on failure.132 */133int radeon_fence_emit(struct radeon_device *rdev,134 struct radeon_fence **fence,135 int ring)136{137 u64 seq;138 139 /* we are protected by the ring emission mutex */140 *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);141 if ((*fence) == NULL)142 return -ENOMEM;143 144 (*fence)->rdev = rdev;145 (*fence)->seq = seq = ++rdev->fence_drv[ring].sync_seq[ring];146 (*fence)->ring = ring;147 (*fence)->is_vm_update = false;148 dma_fence_init(&(*fence)->base, &radeon_fence_ops,149 &rdev->fence_queue.lock,150 rdev->fence_context + ring,151 seq);152 radeon_fence_ring_emit(rdev, ring, *fence);153 trace_radeon_fence_emit(rdev_to_drm(rdev), ring, (*fence)->seq);154 radeon_fence_schedule_check(rdev, ring);155 return 0;156}157 158/*159 * radeon_fence_check_signaled - callback from fence_queue160 *161 * this function is called with fence_queue lock held, which is also used162 * for the fence locking itself, so unlocked variants are used for163 * fence_signal, and remove_wait_queue.164 */165static int radeon_fence_check_signaled(wait_queue_entry_t *wait,166 unsigned int mode, int flags, void *key)167{168 struct radeon_fence *fence;169 u64 seq;170 171 fence = container_of(wait, struct radeon_fence, fence_wake);172 173 /*174 * We cannot use radeon_fence_process here because we're already175 * in the waitqueue, in a call from wake_up_all.176 */177 seq = atomic64_read(&fence->rdev->fence_drv[fence->ring].last_seq);178 if (seq >= fence->seq) {179 dma_fence_signal_locked(&fence->base);180 radeon_irq_kms_sw_irq_put(fence->rdev, fence->ring);181 __remove_wait_queue(&fence->rdev->fence_queue, &fence->fence_wake);182 dma_fence_put(&fence->base);183 }184 return 0;185}186 187/**188 * radeon_fence_activity - check for fence activity189 *190 * @rdev: radeon_device pointer191 * @ring: ring index the fence is associated with192 *193 * Checks the current fence value and calculates the last194 * signalled fence value. Returns true if activity occured195 * on the ring, and the fence_queue should be waken up.196 */197static bool radeon_fence_activity(struct radeon_device *rdev, int ring)198{199 uint64_t seq, last_seq, last_emitted;200 unsigned int count_loop = 0;201 bool wake = false;202 203 /* Note there is a scenario here for an infinite loop but it's204 * very unlikely to happen. For it to happen, the current polling205 * process need to be interrupted by another process and another206 * process needs to update the last_seq btw the atomic read and207 * xchg of the current process.208 *209 * More over for this to go in infinite loop there need to be210 * continuously new fence signaled ie radeon_fence_read needs211 * to return a different value each time for both the currently212 * polling process and the other process that xchg the last_seq213 * btw atomic read and xchg of the current process. And the214 * value the other process set as last seq must be higher than215 * the seq value we just read. Which means that current process216 * need to be interrupted after radeon_fence_read and before217 * atomic xchg.218 *219 * To be even more safe we count the number of time we loop and220 * we bail after 10 loop just accepting the fact that we might221 * have temporarly set the last_seq not to the true real last222 * seq but to an older one.223 */224 last_seq = atomic64_read(&rdev->fence_drv[ring].last_seq);225 do {226 last_emitted = rdev->fence_drv[ring].sync_seq[ring];227 seq = radeon_fence_read(rdev, ring);228 seq |= last_seq & 0xffffffff00000000LL;229 if (seq < last_seq) {230 seq &= 0xffffffff;231 seq |= last_emitted & 0xffffffff00000000LL;232 }233 234 if (seq <= last_seq || seq > last_emitted)235 break;236 237 /* If we loop over we don't want to return without238 * checking if a fence is signaled as it means that the239 * seq we just read is different from the previous on.240 */241 wake = true;242 last_seq = seq;243 if ((count_loop++) > 10) {244 /* We looped over too many time leave with the245 * fact that we might have set an older fence246 * seq then the current real last seq as signaled247 * by the hw.248 */249 break;250 }251 } while (atomic64_xchg(&rdev->fence_drv[ring].last_seq, seq) > seq);252 253 if (seq < last_emitted)254 radeon_fence_schedule_check(rdev, ring);255 256 return wake;257}258 259/**260 * radeon_fence_check_lockup - check for hardware lockup261 *262 * @work: delayed work item263 *264 * Checks for fence activity and if there is none probe265 * the hardware if a lockup occured.266 */267static void radeon_fence_check_lockup(struct work_struct *work)268{269 struct radeon_fence_driver *fence_drv;270 struct radeon_device *rdev;271 int ring;272 273 fence_drv = container_of(work, struct radeon_fence_driver,274 lockup_work.work);275 rdev = fence_drv->rdev;276 ring = fence_drv - &rdev->fence_drv[0];277 278 if (!down_read_trylock(&rdev->exclusive_lock)) {279 /* just reschedule the check if a reset is going on */280 radeon_fence_schedule_check(rdev, ring);281 return;282 }283 284 if (fence_drv->delayed_irq && rdev->irq.installed) {285 unsigned long irqflags;286 287 fence_drv->delayed_irq = false;288 spin_lock_irqsave(&rdev->irq.lock, irqflags);289 radeon_irq_set(rdev);290 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);291 }292 293 if (radeon_fence_activity(rdev, ring))294 wake_up_all(&rdev->fence_queue);295 296 else if (radeon_ring_is_lockup(rdev, ring, &rdev->ring[ring])) {297 298 /* good news we believe it's a lockup */299 dev_warn(rdev->dev, "GPU lockup (current fence id 0x%016llx last fence id 0x%016llx on ring %d)\n",300 (uint64_t)atomic64_read(&fence_drv->last_seq),301 fence_drv->sync_seq[ring], ring);302 303 /* remember that we need an reset */304 rdev->needs_reset = true;305 wake_up_all(&rdev->fence_queue);306 }307 up_read(&rdev->exclusive_lock);308}309 310/**311 * radeon_fence_process - process a fence312 *313 * @rdev: radeon_device pointer314 * @ring: ring index the fence is associated with315 *316 * Checks the current fence value and wakes the fence queue317 * if the sequence number has increased (all asics).318 */319void radeon_fence_process(struct radeon_device *rdev, int ring)320{321 if (radeon_fence_activity(rdev, ring))322 wake_up_all(&rdev->fence_queue);323}324 325/**326 * radeon_fence_seq_signaled - check if a fence sequence number has signaled327 *328 * @rdev: radeon device pointer329 * @seq: sequence number330 * @ring: ring index the fence is associated with331 *332 * Check if the last signaled fence sequnce number is >= the requested333 * sequence number (all asics).334 * Returns true if the fence has signaled (current fence value335 * is >= requested value) or false if it has not (current fence336 * value is < the requested value. Helper function for337 * radeon_fence_signaled().338 */339static bool radeon_fence_seq_signaled(struct radeon_device *rdev,340 u64 seq, unsigned int ring)341{342 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq)343 return true;344 345 /* poll new last sequence at least once */346 radeon_fence_process(rdev, ring);347 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq)348 return true;349 350 return false;351}352 353static bool radeon_fence_is_signaled(struct dma_fence *f)354{355 struct radeon_fence *fence = to_radeon_fence(f);356 struct radeon_device *rdev = fence->rdev;357 unsigned int ring = fence->ring;358 u64 seq = fence->seq;359 360 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq)361 return true;362 363 if (down_read_trylock(&rdev->exclusive_lock)) {364 radeon_fence_process(rdev, ring);365 up_read(&rdev->exclusive_lock);366 367 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq)368 return true;369 }370 return false;371}372 373/**374 * radeon_fence_enable_signaling - enable signalling on fence375 * @f: fence376 *377 * This function is called with fence_queue lock held, and adds a callback378 * to fence_queue that checks if this fence is signaled, and if so it379 * signals the fence and removes itself.380 */381static bool radeon_fence_enable_signaling(struct dma_fence *f)382{383 struct radeon_fence *fence = to_radeon_fence(f);384 struct radeon_device *rdev = fence->rdev;385 386 if (atomic64_read(&rdev->fence_drv[fence->ring].last_seq) >= fence->seq)387 return false;388 389 if (down_read_trylock(&rdev->exclusive_lock)) {390 radeon_irq_kms_sw_irq_get(rdev, fence->ring);391 392 if (radeon_fence_activity(rdev, fence->ring))393 wake_up_all_locked(&rdev->fence_queue);394 395 /* did fence get signaled after we enabled the sw irq? */396 if (atomic64_read(&rdev->fence_drv[fence->ring].last_seq) >= fence->seq) {397 radeon_irq_kms_sw_irq_put(rdev, fence->ring);398 up_read(&rdev->exclusive_lock);399 return false;400 }401 402 up_read(&rdev->exclusive_lock);403 } else {404 /* we're probably in a lockup, lets not fiddle too much */405 if (radeon_irq_kms_sw_irq_get_delayed(rdev, fence->ring))406 rdev->fence_drv[fence->ring].delayed_irq = true;407 radeon_fence_schedule_check(rdev, fence->ring);408 }409 410 fence->fence_wake.flags = 0;411 fence->fence_wake.private = NULL;412 fence->fence_wake.func = radeon_fence_check_signaled;413 __add_wait_queue(&rdev->fence_queue, &fence->fence_wake);414 dma_fence_get(f);415 return true;416}417 418/**419 * radeon_fence_signaled - check if a fence has signaled420 *421 * @fence: radeon fence object422 *423 * Check if the requested fence has signaled (all asics).424 * Returns true if the fence has signaled or false if it has not.425 */426bool radeon_fence_signaled(struct radeon_fence *fence)427{428 if (!fence)429 return true;430 431 if (radeon_fence_seq_signaled(fence->rdev, fence->seq, fence->ring)) {432 dma_fence_signal(&fence->base);433 return true;434 }435 return false;436}437 438/**439 * radeon_fence_any_seq_signaled - check if any sequence number is signaled440 *441 * @rdev: radeon device pointer442 * @seq: sequence numbers443 *444 * Check if the last signaled fence sequnce number is >= the requested445 * sequence number (all asics).446 * Returns true if any has signaled (current value is >= requested value)447 * or false if it has not. Helper function for radeon_fence_wait_seq.448 */449static bool radeon_fence_any_seq_signaled(struct radeon_device *rdev, u64 *seq)450{451 unsigned int i;452 453 for (i = 0; i < RADEON_NUM_RINGS; ++i) {454 if (seq[i] && radeon_fence_seq_signaled(rdev, seq[i], i))455 return true;456 }457 return false;458}459 460/**461 * radeon_fence_wait_seq_timeout - wait for a specific sequence numbers462 *463 * @rdev: radeon device pointer464 * @target_seq: sequence number(s) we want to wait for465 * @intr: use interruptable sleep466 * @timeout: maximum time to wait, or MAX_SCHEDULE_TIMEOUT for infinite wait467 *468 * Wait for the requested sequence number(s) to be written by any ring469 * (all asics). Sequnce number array is indexed by ring id.470 * @intr selects whether to use interruptable (true) or non-interruptable471 * (false) sleep when waiting for the sequence number. Helper function472 * for radeon_fence_wait_*().473 * Returns remaining time if the sequence number has passed, 0 when474 * the wait timeout, or an error for all other cases.475 * -EDEADLK is returned when a GPU lockup has been detected.476 */477static long radeon_fence_wait_seq_timeout(struct radeon_device *rdev,478 u64 *target_seq, bool intr,479 long timeout)480{481 long r;482 int i;483 484 if (radeon_fence_any_seq_signaled(rdev, target_seq))485 return timeout;486 487 /* enable IRQs and tracing */488 for (i = 0; i < RADEON_NUM_RINGS; ++i) {489 if (!target_seq[i])490 continue;491 492 trace_radeon_fence_wait_begin(rdev_to_drm(rdev), i, target_seq[i]);493 radeon_irq_kms_sw_irq_get(rdev, i);494 }495 496 if (intr) {497 r = wait_event_interruptible_timeout(rdev->fence_queue, (498 radeon_fence_any_seq_signaled(rdev, target_seq)499 || rdev->needs_reset), timeout);500 } else {501 r = wait_event_timeout(rdev->fence_queue, (502 radeon_fence_any_seq_signaled(rdev, target_seq)503 || rdev->needs_reset), timeout);504 }505 506 if (rdev->needs_reset)507 r = -EDEADLK;508 509 for (i = 0; i < RADEON_NUM_RINGS; ++i) {510 if (!target_seq[i])511 continue;512 513 radeon_irq_kms_sw_irq_put(rdev, i);514 trace_radeon_fence_wait_end(rdev_to_drm(rdev), i, target_seq[i]);515 }516 517 return r;518}519 520/**521 * radeon_fence_wait_timeout - wait for a fence to signal with timeout522 *523 * @fence: radeon fence object524 * @intr: use interruptible sleep525 *526 * Wait for the requested fence to signal (all asics).527 * @intr selects whether to use interruptable (true) or non-interruptable528 * (false) sleep when waiting for the fence.529 * @timeout: maximum time to wait, or MAX_SCHEDULE_TIMEOUT for infinite wait530 * Returns remaining time if the sequence number has passed, 0 when531 * the wait timeout, or an error for all other cases.532 */533long radeon_fence_wait_timeout(struct radeon_fence *fence, bool intr, long timeout)534{535 uint64_t seq[RADEON_NUM_RINGS] = {};536 long r;537 538 /*539 * This function should not be called on !radeon fences.540 * If this is the case, it would mean this function can541 * also be called on radeon fences belonging to another card.542 * exclusive_lock is not held in that case.543 */544 if (WARN_ON_ONCE(!to_radeon_fence(&fence->base)))545 return dma_fence_wait(&fence->base, intr);546 547 seq[fence->ring] = fence->seq;548 r = radeon_fence_wait_seq_timeout(fence->rdev, seq, intr, timeout);549 if (r <= 0)550 return r;551 552 dma_fence_signal(&fence->base);553 return r;554}555 556/**557 * radeon_fence_wait - wait for a fence to signal558 *559 * @fence: radeon fence object560 * @intr: use interruptible sleep561 *562 * Wait for the requested fence to signal (all asics).563 * @intr selects whether to use interruptable (true) or non-interruptable564 * (false) sleep when waiting for the fence.565 * Returns 0 if the fence has passed, error for all other cases.566 */567int radeon_fence_wait(struct radeon_fence *fence, bool intr)568{569 long r = radeon_fence_wait_timeout(fence, intr, MAX_SCHEDULE_TIMEOUT);570 571 if (r > 0)572 return 0;573 else574 return r;575}576 577/**578 * radeon_fence_wait_any - wait for a fence to signal on any ring579 *580 * @rdev: radeon device pointer581 * @fences: radeon fence object(s)582 * @intr: use interruptable sleep583 *584 * Wait for any requested fence to signal (all asics). Fence585 * array is indexed by ring id. @intr selects whether to use586 * interruptable (true) or non-interruptable (false) sleep when587 * waiting for the fences. Used by the suballocator.588 * Returns 0 if any fence has passed, error for all other cases.589 */590int radeon_fence_wait_any(struct radeon_device *rdev,591 struct radeon_fence **fences,592 bool intr)593{594 uint64_t seq[RADEON_NUM_RINGS];595 unsigned int i, num_rings = 0;596 long r;597 598 for (i = 0; i < RADEON_NUM_RINGS; ++i) {599 seq[i] = 0;600 601 if (!fences[i])602 continue;603 604 seq[i] = fences[i]->seq;605 ++num_rings;606 }607 608 /* nothing to wait for ? */609 if (num_rings == 0)610 return -ENOENT;611 612 r = radeon_fence_wait_seq_timeout(rdev, seq, intr, MAX_SCHEDULE_TIMEOUT);613 if (r < 0)614 return r;615 616 return 0;617}618 619/**620 * radeon_fence_wait_next - wait for the next fence to signal621 *622 * @rdev: radeon device pointer623 * @ring: ring index the fence is associated with624 *625 * Wait for the next fence on the requested ring to signal (all asics).626 * Returns 0 if the next fence has passed, error for all other cases.627 * Caller must hold ring lock.628 */629int radeon_fence_wait_next(struct radeon_device *rdev, int ring)630{631 uint64_t seq[RADEON_NUM_RINGS] = {};632 long r;633 634 seq[ring] = atomic64_read(&rdev->fence_drv[ring].last_seq) + 1ULL;635 if (seq[ring] >= rdev->fence_drv[ring].sync_seq[ring]) {636 /* nothing to wait for, last_seq is already637 * the last emited fence638 */639 return -ENOENT;640 }641 642 r = radeon_fence_wait_seq_timeout(rdev, seq, false, MAX_SCHEDULE_TIMEOUT);643 if (r < 0)644 return r;645 646 return 0;647}648 649/**650 * radeon_fence_wait_empty - wait for all fences to signal651 *652 * @rdev: radeon device pointer653 * @ring: ring index the fence is associated with654 *655 * Wait for all fences on the requested ring to signal (all asics).656 * Returns 0 if the fences have passed, error for all other cases.657 * Caller must hold ring lock.658 */659int radeon_fence_wait_empty(struct radeon_device *rdev, int ring)660{661 uint64_t seq[RADEON_NUM_RINGS] = {};662 long r;663 664 seq[ring] = rdev->fence_drv[ring].sync_seq[ring];665 if (!seq[ring])666 return 0;667 668 r = radeon_fence_wait_seq_timeout(rdev, seq, false, MAX_SCHEDULE_TIMEOUT);669 if (r < 0) {670 if (r == -EDEADLK)671 return -EDEADLK;672 673 dev_err(rdev->dev, "error waiting for ring[%d] to become idle (%ld)\n",674 ring, r);675 }676 return 0;677}678 679/**680 * radeon_fence_ref - take a ref on a fence681 *682 * @fence: radeon fence object683 *684 * Take a reference on a fence (all asics).685 * Returns the fence.686 */687struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)688{689 dma_fence_get(&fence->base);690 return fence;691}692 693/**694 * radeon_fence_unref - remove a ref on a fence695 *696 * @fence: radeon fence object697 *698 * Remove a reference on a fence (all asics).699 */700void radeon_fence_unref(struct radeon_fence **fence)701{702 struct radeon_fence *tmp = *fence;703 704 *fence = NULL;705 if (tmp)706 dma_fence_put(&tmp->base);707}708 709/**710 * radeon_fence_count_emitted - get the count of emitted fences711 *712 * @rdev: radeon device pointer713 * @ring: ring index the fence is associated with714 *715 * Get the number of fences emitted on the requested ring (all asics).716 * Returns the number of emitted fences on the ring. Used by the717 * dynpm code to ring track activity.718 */719unsigned int radeon_fence_count_emitted(struct radeon_device *rdev, int ring)720{721 uint64_t emitted;722 723 /* We are not protected by ring lock when reading the last sequence724 * but it's ok to report slightly wrong fence count here.725 */726 radeon_fence_process(rdev, ring);727 emitted = rdev->fence_drv[ring].sync_seq[ring]728 - atomic64_read(&rdev->fence_drv[ring].last_seq);729 /* to avoid 32bits warp around */730 if (emitted > 0x10000000)731 emitted = 0x10000000;732 733 return (unsigned int)emitted;734}735 736/**737 * radeon_fence_need_sync - do we need a semaphore738 *739 * @fence: radeon fence object740 * @dst_ring: which ring to check against741 *742 * Check if the fence needs to be synced against another ring743 * (all asics). If so, we need to emit a semaphore.744 * Returns true if we need to sync with another ring, false if745 * not.746 */747bool radeon_fence_need_sync(struct radeon_fence *fence, int dst_ring)748{749 struct radeon_fence_driver *fdrv;750 751 if (!fence)752 return false;753 754 if (fence->ring == dst_ring)755 return false;756 757 /* we are protected by the ring mutex */758 fdrv = &fence->rdev->fence_drv[dst_ring];759 if (fence->seq <= fdrv->sync_seq[fence->ring])760 return false;761 762 return true;763}764 765/**766 * radeon_fence_note_sync - record the sync point767 *768 * @fence: radeon fence object769 * @dst_ring: which ring to check against770 *771 * Note the sequence number at which point the fence will772 * be synced with the requested ring (all asics).773 */774void radeon_fence_note_sync(struct radeon_fence *fence, int dst_ring)775{776 struct radeon_fence_driver *dst, *src;777 unsigned int i;778 779 if (!fence)780 return;781 782 if (fence->ring == dst_ring)783 return;784 785 /* we are protected by the ring mutex */786 src = &fence->rdev->fence_drv[fence->ring];787 dst = &fence->rdev->fence_drv[dst_ring];788 for (i = 0; i < RADEON_NUM_RINGS; ++i) {789 if (i == dst_ring)790 continue;791 792 dst->sync_seq[i] = max(dst->sync_seq[i], src->sync_seq[i]);793 }794}795 796/**797 * radeon_fence_driver_start_ring - make the fence driver798 * ready for use on the requested ring.799 *800 * @rdev: radeon device pointer801 * @ring: ring index to start the fence driver on802 *803 * Make the fence driver ready for processing (all asics).804 * Not all asics have all rings, so each asic will only805 * start the fence driver on the rings it has.806 * Returns 0 for success, errors for failure.807 */808int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)809{810 uint64_t index;811 int r;812 813 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);814 if (rdev->wb.use_event || !radeon_ring_supports_scratch_reg(rdev, &rdev->ring[ring])) {815 rdev->fence_drv[ring].scratch_reg = 0;816 if (ring != R600_RING_TYPE_UVD_INDEX) {817 index = R600_WB_EVENT_OFFSET + ring * 4;818 rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];819 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr +820 index;821 822 } else {823 /* put fence directly behind firmware */824 index = ALIGN(rdev->uvd_fw->size, 8);825 rdev->fence_drv[ring].cpu_addr = rdev->uvd.cpu_addr + index;826 rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr + index;827 }828 829 } else {830 r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg);831 if (r) {832 dev_err(rdev->dev, "fence failed to get scratch register\n");833 return r;834 }835 index = RADEON_WB_SCRATCH_OFFSET +836 rdev->fence_drv[ring].scratch_reg -837 rdev->scratch.reg_base;838 rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];839 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;840 }841 radeon_fence_write(rdev, atomic64_read(&rdev->fence_drv[ring].last_seq), ring);842 rdev->fence_drv[ring].initialized = true;843 dev_info(rdev->dev, "fence driver on ring %d use gpu addr 0x%016llx\n",844 ring, rdev->fence_drv[ring].gpu_addr);845 return 0;846}847 848/**849 * radeon_fence_driver_init_ring - init the fence driver850 * for the requested ring.851 *852 * @rdev: radeon device pointer853 * @ring: ring index to start the fence driver on854 *855 * Init the fence driver for the requested ring (all asics).856 * Helper function for radeon_fence_driver_init().857 */858static void radeon_fence_driver_init_ring(struct radeon_device *rdev, int ring)859{860 int i;861 862 rdev->fence_drv[ring].scratch_reg = -1;863 rdev->fence_drv[ring].cpu_addr = NULL;864 rdev->fence_drv[ring].gpu_addr = 0;865 for (i = 0; i < RADEON_NUM_RINGS; ++i)866 rdev->fence_drv[ring].sync_seq[i] = 0;867 atomic64_set(&rdev->fence_drv[ring].last_seq, 0);868 rdev->fence_drv[ring].initialized = false;869 INIT_DELAYED_WORK(&rdev->fence_drv[ring].lockup_work,870 radeon_fence_check_lockup);871 rdev->fence_drv[ring].rdev = rdev;872}873 874/**875 * radeon_fence_driver_init - init the fence driver876 * for all possible rings.877 *878 * @rdev: radeon device pointer879 *880 * Init the fence driver for all possible rings (all asics).881 * Not all asics have all rings, so each asic will only882 * start the fence driver on the rings it has using883 * radeon_fence_driver_start_ring().884 */885void radeon_fence_driver_init(struct radeon_device *rdev)886{887 int ring;888 889 init_waitqueue_head(&rdev->fence_queue);890 for (ring = 0; ring < RADEON_NUM_RINGS; ring++)891 radeon_fence_driver_init_ring(rdev, ring);892 893 radeon_debugfs_fence_init(rdev);894}895 896/**897 * radeon_fence_driver_fini - tear down the fence driver898 * for all possible rings.899 *900 * @rdev: radeon device pointer901 *902 * Tear down the fence driver for all possible rings (all asics).903 */904void radeon_fence_driver_fini(struct radeon_device *rdev)905{906 int ring, r;907 908 mutex_lock(&rdev->ring_lock);909 for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {910 if (!rdev->fence_drv[ring].initialized)911 continue;912 r = radeon_fence_wait_empty(rdev, ring);913 if (r) {914 /* no need to trigger GPU reset as we are unloading */915 radeon_fence_driver_force_completion(rdev, ring);916 }917 cancel_delayed_work_sync(&rdev->fence_drv[ring].lockup_work);918 wake_up_all(&rdev->fence_queue);919 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);920 rdev->fence_drv[ring].initialized = false;921 }922 mutex_unlock(&rdev->ring_lock);923}924 925/**926 * radeon_fence_driver_force_completion - force all fence waiter to complete927 *928 * @rdev: radeon device pointer929 * @ring: the ring to complete930 *931 * In case of GPU reset failure make sure no process keep waiting on fence932 * that will never complete.933 */934void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring)935{936 if (rdev->fence_drv[ring].initialized) {937 radeon_fence_write(rdev, rdev->fence_drv[ring].sync_seq[ring], ring);938 cancel_delayed_work_sync(&rdev->fence_drv[ring].lockup_work);939 }940}941 942 943/*944 * Fence debugfs945 */946#if defined(CONFIG_DEBUG_FS)947static int radeon_debugfs_fence_info_show(struct seq_file *m, void *data)948{949 struct radeon_device *rdev = m->private;950 int i, j;951 952 for (i = 0; i < RADEON_NUM_RINGS; ++i) {953 if (!rdev->fence_drv[i].initialized)954 continue;955 956 radeon_fence_process(rdev, i);957 958 seq_printf(m, "--- ring %d ---\n", i);959 seq_printf(m, "Last signaled fence 0x%016llx\n",960 (unsigned long long)atomic64_read(&rdev->fence_drv[i].last_seq));961 seq_printf(m, "Last emitted 0x%016llx\n",962 rdev->fence_drv[i].sync_seq[i]);963 964 for (j = 0; j < RADEON_NUM_RINGS; ++j) {965 if (i != j && rdev->fence_drv[j].initialized)966 seq_printf(m, "Last sync to ring %d 0x%016llx\n",967 j, rdev->fence_drv[i].sync_seq[j]);968 }969 }970 return 0;971}972 973/*974 * radeon_debugfs_gpu_reset - manually trigger a gpu reset975 *976 * Manually trigger a gpu reset at the next fence wait.977 */978static int radeon_debugfs_gpu_reset(void *data, u64 *val)979{980 struct radeon_device *rdev = (struct radeon_device *)data;981 982 down_read(&rdev->exclusive_lock);983 *val = rdev->needs_reset;984 rdev->needs_reset = true;985 wake_up_all(&rdev->fence_queue);986 up_read(&rdev->exclusive_lock);987 988 return 0;989}990DEFINE_SHOW_ATTRIBUTE(radeon_debugfs_fence_info);991DEFINE_DEBUGFS_ATTRIBUTE(radeon_debugfs_gpu_reset_fops,992 radeon_debugfs_gpu_reset, NULL, "%lld\n");993#endif994 995void radeon_debugfs_fence_init(struct radeon_device *rdev)996{997#if defined(CONFIG_DEBUG_FS)998 struct dentry *root = rdev_to_drm(rdev)->primary->debugfs_root;999 1000 debugfs_create_file("radeon_gpu_reset", 0444, root, rdev,1001 &radeon_debugfs_gpu_reset_fops);1002 debugfs_create_file("radeon_fence_info", 0444, root, rdev,1003 &radeon_debugfs_fence_info_fops);1004 1005 1006#endif1007}1008 1009static const char *radeon_fence_get_driver_name(struct dma_fence *fence)1010{1011 return "radeon";1012}1013 1014static const char *radeon_fence_get_timeline_name(struct dma_fence *f)1015{1016 struct radeon_fence *fence = to_radeon_fence(f);1017 1018 switch (fence->ring) {1019 case RADEON_RING_TYPE_GFX_INDEX: return "radeon.gfx";1020 case CAYMAN_RING_TYPE_CP1_INDEX: return "radeon.cp1";1021 case CAYMAN_RING_TYPE_CP2_INDEX: return "radeon.cp2";1022 case R600_RING_TYPE_DMA_INDEX: return "radeon.dma";1023 case CAYMAN_RING_TYPE_DMA1_INDEX: return "radeon.dma1";1024 case R600_RING_TYPE_UVD_INDEX: return "radeon.uvd";1025 case TN_RING_TYPE_VCE1_INDEX: return "radeon.vce1";1026 case TN_RING_TYPE_VCE2_INDEX: return "radeon.vce2";1027 default:1028 WARN_ON_ONCE(1);1029 return "radeon.unk";1030 }1031}1032 1033static inline bool radeon_test_signaled(struct radeon_fence *fence)1034{1035 return test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->base.flags);1036}1037 1038struct radeon_wait_cb {1039 struct dma_fence_cb base;1040 struct task_struct *task;1041};1042 1043static void1044radeon_fence_wait_cb(struct dma_fence *fence, struct dma_fence_cb *cb)1045{1046 struct radeon_wait_cb *wait =1047 container_of(cb, struct radeon_wait_cb, base);1048 1049 wake_up_process(wait->task);1050}1051 1052static signed long radeon_fence_default_wait(struct dma_fence *f, bool intr,1053 signed long t)1054{1055 struct radeon_fence *fence = to_radeon_fence(f);1056 struct radeon_device *rdev = fence->rdev;1057 struct radeon_wait_cb cb;1058 1059 cb.task = current;1060 1061 if (dma_fence_add_callback(f, &cb.base, radeon_fence_wait_cb))1062 return t;1063 1064 while (t > 0) {1065 if (intr)1066 set_current_state(TASK_INTERRUPTIBLE);1067 else1068 set_current_state(TASK_UNINTERRUPTIBLE);1069 1070 /*1071 * radeon_test_signaled must be called after1072 * set_current_state to prevent a race with wake_up_process1073 */1074 if (radeon_test_signaled(fence))1075 break;1076 1077 if (rdev->needs_reset) {1078 t = -EDEADLK;1079 break;1080 }1081 1082 t = schedule_timeout(t);1083 1084 if (t > 0 && intr && signal_pending(current))1085 t = -ERESTARTSYS;1086 }1087 1088 __set_current_state(TASK_RUNNING);1089 dma_fence_remove_callback(f, &cb.base);1090 1091 return t;1092}1093 1094const struct dma_fence_ops radeon_fence_ops = {1095 .get_driver_name = radeon_fence_get_driver_name,1096 .get_timeline_name = radeon_fence_get_timeline_name,1097 .enable_signaling = radeon_fence_enable_signaling,1098 .signaled = radeon_fence_is_signaled,1099 .wait = radeon_fence_default_wait,1100 .release = NULL,1101};1102