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1/*2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and3 * VA Linux Systems Inc., Fremont, California.4 *5 * All Rights Reserved.6 *7 * Permission is hereby granted, free of charge, to any person obtaining8 * a copy of this software and associated documentation files (the9 * "Software"), to deal in the Software without restriction, including10 * without limitation on the rights to use, copy, modify, merge,11 * publish, distribute, sublicense, and/or sell copies of the Software,12 * and to permit persons to whom the Software is furnished to do so,13 * subject to the following conditions:14 *15 * The above copyright notice and this permission notice (including the16 * next paragraph) shall be included in all copies or substantial17 * portions of the Software.18 *19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER26 * DEALINGS IN THE SOFTWARE.27 */28 29/*30 * Authors:31 * Kevin E. Martin <martin@xfree86.org>32 * Rickard E. Faith <faith@valinux.com>33 * Alan Hourihane <alanh@fairlite.demon.co.uk>34 *35 * References:36 *37 * !!!! FIXME !!!!38 * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical39 * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April40 * 1999.41 *42 * !!!! FIXME !!!!43 * RAGE 128 Software Development Manual (Technical Reference Manual P/N44 * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999.45 *46 */47 48/* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h49 * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT50 * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */51#ifndef _RADEON_REG_H_52#define _RADEON_REG_H_53 54#include "r300_reg.h"55#include "r500_reg.h"56#include "r600_reg.h"57#include "evergreen_reg.h"58#include "ni_reg.h"59#include "si_reg.h"60#include "cik_reg.h"61 62#define RADEON_MC_AGP_LOCATION 0x014c63#define RADEON_MC_AGP_START_MASK 0x0000FFFF64#define RADEON_MC_AGP_START_SHIFT 065#define RADEON_MC_AGP_TOP_MASK 0xFFFF000066#define RADEON_MC_AGP_TOP_SHIFT 1667#define RADEON_MC_FB_LOCATION 0x014868#define RADEON_MC_FB_START_MASK 0x0000FFFF69#define RADEON_MC_FB_START_SHIFT 070#define RADEON_MC_FB_TOP_MASK 0xFFFF000071#define RADEON_MC_FB_TOP_SHIFT 1672#define RADEON_AGP_BASE_2 0x015c /* r200+ only */73#define RADEON_AGP_BASE 0x017074 75#define ATI_DATATYPE_VQ 076#define ATI_DATATYPE_CI4 177#define ATI_DATATYPE_CI8 278#define ATI_DATATYPE_ARGB1555 379#define ATI_DATATYPE_RGB565 480#define ATI_DATATYPE_RGB888 581#define ATI_DATATYPE_ARGB8888 682#define ATI_DATATYPE_RGB332 783#define ATI_DATATYPE_Y8 884#define ATI_DATATYPE_RGB8 985#define ATI_DATATYPE_CI16 1086#define ATI_DATATYPE_VYUY_422 1187#define ATI_DATATYPE_YVYU_422 1288#define ATI_DATATYPE_AYUV_444 1489#define ATI_DATATYPE_ARGB4444 1590 91 /* Registers for 2D/Video/Overlay */92#define RADEON_ADAPTER_ID 0x0f2c /* PCI */93#define RADEON_AGP_BASE 0x017094#define RADEON_AGP_CNTL 0x017495# define RADEON_AGP_APER_SIZE_256MB (0x00 << 0)96# define RADEON_AGP_APER_SIZE_128MB (0x20 << 0)97# define RADEON_AGP_APER_SIZE_64MB (0x30 << 0)98# define RADEON_AGP_APER_SIZE_32MB (0x38 << 0)99# define RADEON_AGP_APER_SIZE_16MB (0x3c << 0)100# define RADEON_AGP_APER_SIZE_8MB (0x3e << 0)101# define RADEON_AGP_APER_SIZE_4MB (0x3f << 0)102# define RADEON_AGP_APER_SIZE_MASK (0x3f << 0)103#define RADEON_STATUS_PCI_CONFIG 0x06104# define RADEON_CAP_LIST 0x100000105#define RADEON_CAPABILITIES_PTR_PCI_CONFIG 0x34 /* offset in PCI config*/106# define RADEON_CAP_PTR_MASK 0xfc /* mask off reserved bits of CAP_PTR */107# define RADEON_CAP_ID_NULL 0x00 /* End of capability list */108# define RADEON_CAP_ID_AGP 0x02 /* AGP capability ID */109# define RADEON_CAP_ID_EXP 0x10 /* PCI Express */110#define RADEON_AGP_COMMAND 0x0f60 /* PCI */111#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/112# define RADEON_AGP_ENABLE (1<<8)113#define RADEON_AGP_PLL_CNTL 0x000b /* PLL */114#define RADEON_AGP_STATUS 0x0f5c /* PCI */115# define RADEON_AGP_1X_MODE 0x01116# define RADEON_AGP_2X_MODE 0x02117# define RADEON_AGP_4X_MODE 0x04118# define RADEON_AGP_FW_MODE 0x10119# define RADEON_AGP_MODE_MASK 0x17120# define RADEON_AGPv3_MODE 0x08121# define RADEON_AGPv3_4X_MODE 0x01122# define RADEON_AGPv3_8X_MODE 0x02123#define RADEON_ATTRDR 0x03c1 /* VGA */124#define RADEON_ATTRDW 0x03c0 /* VGA */125#define RADEON_ATTRX 0x03c0 /* VGA */126#define RADEON_AUX_SC_CNTL 0x1660127# define RADEON_AUX1_SC_EN (1 << 0)128# define RADEON_AUX1_SC_MODE_OR (0 << 1)129# define RADEON_AUX1_SC_MODE_NAND (1 << 1)130# define RADEON_AUX2_SC_EN (1 << 2)131# define RADEON_AUX2_SC_MODE_OR (0 << 3)132# define RADEON_AUX2_SC_MODE_NAND (1 << 3)133# define RADEON_AUX3_SC_EN (1 << 4)134# define RADEON_AUX3_SC_MODE_OR (0 << 5)135# define RADEON_AUX3_SC_MODE_NAND (1 << 5)136#define RADEON_AUX1_SC_BOTTOM 0x1670137#define RADEON_AUX1_SC_LEFT 0x1664138#define RADEON_AUX1_SC_RIGHT 0x1668139#define RADEON_AUX1_SC_TOP 0x166c140#define RADEON_AUX2_SC_BOTTOM 0x1680141#define RADEON_AUX2_SC_LEFT 0x1674142#define RADEON_AUX2_SC_RIGHT 0x1678143#define RADEON_AUX2_SC_TOP 0x167c144#define RADEON_AUX3_SC_BOTTOM 0x1690145#define RADEON_AUX3_SC_LEFT 0x1684146#define RADEON_AUX3_SC_RIGHT 0x1688147#define RADEON_AUX3_SC_TOP 0x168c148#define RADEON_AUX_WINDOW_HORZ_CNTL 0x02d8149#define RADEON_AUX_WINDOW_VERT_CNTL 0x02dc150 151#define RADEON_BASE_CODE 0x0f0b152#define RADEON_BIOS_0_SCRATCH 0x0010153# define RADEON_FP_PANEL_SCALABLE (1 << 16)154# define RADEON_FP_PANEL_SCALE_EN (1 << 17)155# define RADEON_FP_CHIP_SCALE_EN (1 << 18)156# define RADEON_DRIVER_BRIGHTNESS_EN (1 << 26)157# define RADEON_DISPLAY_ROT_MASK (3 << 28)158# define RADEON_DISPLAY_ROT_00 (0 << 28)159# define RADEON_DISPLAY_ROT_90 (1 << 28)160# define RADEON_DISPLAY_ROT_180 (2 << 28)161# define RADEON_DISPLAY_ROT_270 (3 << 28)162#define RADEON_BIOS_1_SCRATCH 0x0014163#define RADEON_BIOS_2_SCRATCH 0x0018164#define RADEON_BIOS_3_SCRATCH 0x001c165#define RADEON_BIOS_4_SCRATCH 0x0020166# define RADEON_CRT1_ATTACHED_MASK (3 << 0)167# define RADEON_CRT1_ATTACHED_MONO (1 << 0)168# define RADEON_CRT1_ATTACHED_COLOR (2 << 0)169# define RADEON_LCD1_ATTACHED (1 << 2)170# define RADEON_DFP1_ATTACHED (1 << 3)171# define RADEON_TV1_ATTACHED_MASK (3 << 4)172# define RADEON_TV1_ATTACHED_COMP (1 << 4)173# define RADEON_TV1_ATTACHED_SVIDEO (2 << 4)174# define RADEON_CRT2_ATTACHED_MASK (3 << 8)175# define RADEON_CRT2_ATTACHED_MONO (1 << 8)176# define RADEON_CRT2_ATTACHED_COLOR (2 << 8)177# define RADEON_DFP2_ATTACHED (1 << 11)178#define RADEON_BIOS_5_SCRATCH 0x0024179# define RADEON_LCD1_ON (1 << 0)180# define RADEON_CRT1_ON (1 << 1)181# define RADEON_TV1_ON (1 << 2)182# define RADEON_DFP1_ON (1 << 3)183# define RADEON_CRT2_ON (1 << 5)184# define RADEON_CV1_ON (1 << 6)185# define RADEON_DFP2_ON (1 << 7)186# define RADEON_LCD1_CRTC_MASK (1 << 8)187# define RADEON_LCD1_CRTC_SHIFT 8188# define RADEON_CRT1_CRTC_MASK (1 << 9)189# define RADEON_CRT1_CRTC_SHIFT 9190# define RADEON_TV1_CRTC_MASK (1 << 10)191# define RADEON_TV1_CRTC_SHIFT 10192# define RADEON_DFP1_CRTC_MASK (1 << 11)193# define RADEON_DFP1_CRTC_SHIFT 11194# define RADEON_CRT2_CRTC_MASK (1 << 12)195# define RADEON_CRT2_CRTC_SHIFT 12196# define RADEON_CV1_CRTC_MASK (1 << 13)197# define RADEON_CV1_CRTC_SHIFT 13198# define RADEON_DFP2_CRTC_MASK (1 << 14)199# define RADEON_DFP2_CRTC_SHIFT 14200# define RADEON_ACC_REQ_LCD1 (1 << 16)201# define RADEON_ACC_REQ_CRT1 (1 << 17)202# define RADEON_ACC_REQ_TV1 (1 << 18)203# define RADEON_ACC_REQ_DFP1 (1 << 19)204# define RADEON_ACC_REQ_CRT2 (1 << 21)205# define RADEON_ACC_REQ_TV2 (1 << 22)206# define RADEON_ACC_REQ_DFP2 (1 << 23)207#define RADEON_BIOS_6_SCRATCH 0x0028208# define RADEON_ACC_MODE_CHANGE (1 << 2)209# define RADEON_EXT_DESKTOP_MODE (1 << 3)210# define RADEON_LCD_DPMS_ON (1 << 20)211# define RADEON_CRT_DPMS_ON (1 << 21)212# define RADEON_TV_DPMS_ON (1 << 22)213# define RADEON_DFP_DPMS_ON (1 << 23)214# define RADEON_DPMS_MASK (3 << 24)215# define RADEON_DPMS_ON (0 << 24)216# define RADEON_DPMS_STANDBY (1 << 24)217# define RADEON_DPMS_SUSPEND (2 << 24)218# define RADEON_DPMS_OFF (3 << 24)219# define RADEON_SCREEN_BLANKING (1 << 26)220# define RADEON_DRIVER_CRITICAL (1 << 27)221# define RADEON_DISPLAY_SWITCHING_DIS (1 << 30)222#define RADEON_BIOS_7_SCRATCH 0x002c223# define RADEON_SYS_HOTKEY (1 << 10)224# define RADEON_DRV_LOADED (1 << 12)225#define RADEON_BIOS_ROM 0x0f30 /* PCI */226#define RADEON_BIST 0x0f0f /* PCI */227#define RADEON_BRUSH_DATA0 0x1480228#define RADEON_BRUSH_DATA1 0x1484229#define RADEON_BRUSH_DATA10 0x14a8230#define RADEON_BRUSH_DATA11 0x14ac231#define RADEON_BRUSH_DATA12 0x14b0232#define RADEON_BRUSH_DATA13 0x14b4233#define RADEON_BRUSH_DATA14 0x14b8234#define RADEON_BRUSH_DATA15 0x14bc235#define RADEON_BRUSH_DATA16 0x14c0236#define RADEON_BRUSH_DATA17 0x14c4237#define RADEON_BRUSH_DATA18 0x14c8238#define RADEON_BRUSH_DATA19 0x14cc239#define RADEON_BRUSH_DATA2 0x1488240#define RADEON_BRUSH_DATA20 0x14d0241#define RADEON_BRUSH_DATA21 0x14d4242#define RADEON_BRUSH_DATA22 0x14d8243#define RADEON_BRUSH_DATA23 0x14dc244#define RADEON_BRUSH_DATA24 0x14e0245#define RADEON_BRUSH_DATA25 0x14e4246#define RADEON_BRUSH_DATA26 0x14e8247#define RADEON_BRUSH_DATA27 0x14ec248#define RADEON_BRUSH_DATA28 0x14f0249#define RADEON_BRUSH_DATA29 0x14f4250#define RADEON_BRUSH_DATA3 0x148c251#define RADEON_BRUSH_DATA30 0x14f8252#define RADEON_BRUSH_DATA31 0x14fc253#define RADEON_BRUSH_DATA32 0x1500254#define RADEON_BRUSH_DATA33 0x1504255#define RADEON_BRUSH_DATA34 0x1508256#define RADEON_BRUSH_DATA35 0x150c257#define RADEON_BRUSH_DATA36 0x1510258#define RADEON_BRUSH_DATA37 0x1514259#define RADEON_BRUSH_DATA38 0x1518260#define RADEON_BRUSH_DATA39 0x151c261#define RADEON_BRUSH_DATA4 0x1490262#define RADEON_BRUSH_DATA40 0x1520263#define RADEON_BRUSH_DATA41 0x1524264#define RADEON_BRUSH_DATA42 0x1528265#define RADEON_BRUSH_DATA43 0x152c266#define RADEON_BRUSH_DATA44 0x1530267#define RADEON_BRUSH_DATA45 0x1534268#define RADEON_BRUSH_DATA46 0x1538269#define RADEON_BRUSH_DATA47 0x153c270#define RADEON_BRUSH_DATA48 0x1540271#define RADEON_BRUSH_DATA49 0x1544272#define RADEON_BRUSH_DATA5 0x1494273#define RADEON_BRUSH_DATA50 0x1548274#define RADEON_BRUSH_DATA51 0x154c275#define RADEON_BRUSH_DATA52 0x1550276#define RADEON_BRUSH_DATA53 0x1554277#define RADEON_BRUSH_DATA54 0x1558278#define RADEON_BRUSH_DATA55 0x155c279#define RADEON_BRUSH_DATA56 0x1560280#define RADEON_BRUSH_DATA57 0x1564281#define RADEON_BRUSH_DATA58 0x1568282#define RADEON_BRUSH_DATA59 0x156c283#define RADEON_BRUSH_DATA6 0x1498284#define RADEON_BRUSH_DATA60 0x1570285#define RADEON_BRUSH_DATA61 0x1574286#define RADEON_BRUSH_DATA62 0x1578287#define RADEON_BRUSH_DATA63 0x157c288#define RADEON_BRUSH_DATA7 0x149c289#define RADEON_BRUSH_DATA8 0x14a0290#define RADEON_BRUSH_DATA9 0x14a4291#define RADEON_BRUSH_SCALE 0x1470292#define RADEON_BRUSH_Y_X 0x1474293#define RADEON_BUS_CNTL 0x0030294# define RADEON_BUS_MASTER_DIS (1 << 6)295# define RADEON_BUS_BIOS_DIS_ROM (1 << 12)296# define RS600_BUS_MASTER_DIS (1 << 14)297# define RS600_MSI_REARM (1 << 20) /* rs600/rs690/rs740 */298# define RADEON_BUS_RD_DISCARD_EN (1 << 24)299# define RADEON_BUS_RD_ABORT_EN (1 << 25)300# define RADEON_BUS_MSTR_DISCONNECT_EN (1 << 28)301# define RADEON_BUS_WRT_BURST (1 << 29)302# define RADEON_BUS_READ_BURST (1 << 30)303#define RADEON_BUS_CNTL1 0x0034304# define RADEON_BUS_WAIT_ON_LOCK_EN (1 << 4)305#define RV370_BUS_CNTL 0x004c306# define RV370_BUS_BIOS_DIS_ROM (1 << 2)307/* rv370/rv380, rv410, r423/r430/r480, r5xx */308#define RADEON_MSI_REARM_EN 0x0160309# define RV370_MSI_REARM_EN (1 << 0)310 311/* #define RADEON_PCIE_INDEX 0x0030 */312/* #define RADEON_PCIE_DATA 0x0034 */313#define RADEON_PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE */314# define RADEON_PCIE_LC_LINK_WIDTH_SHIFT 0315# define RADEON_PCIE_LC_LINK_WIDTH_MASK 0x7316# define RADEON_PCIE_LC_LINK_WIDTH_X0 0317# define RADEON_PCIE_LC_LINK_WIDTH_X1 1318# define RADEON_PCIE_LC_LINK_WIDTH_X2 2319# define RADEON_PCIE_LC_LINK_WIDTH_X4 3320# define RADEON_PCIE_LC_LINK_WIDTH_X8 4321# define RADEON_PCIE_LC_LINK_WIDTH_X12 5322# define RADEON_PCIE_LC_LINK_WIDTH_X16 6323# define RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT 4324# define RADEON_PCIE_LC_LINK_WIDTH_RD_MASK 0x70325# define RADEON_PCIE_LC_RECONFIG_NOW (1 << 8)326# define RADEON_PCIE_LC_RECONFIG_LATER (1 << 9)327# define RADEON_PCIE_LC_SHORT_RECONFIG_EN (1 << 10)328# define R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)329# define R600_PCIE_LC_RENEGOTIATION_SUPPORT (1 << 9)330# define R600_PCIE_LC_RENEGOTIATE_EN (1 << 10)331# define R600_PCIE_LC_SHORT_RECONFIG_EN (1 << 11)332# define R600_PCIE_LC_UPCONFIGURE_SUPPORT (1 << 12)333# define R600_PCIE_LC_UPCONFIGURE_DIS (1 << 13)334 335#define R600_TARGET_AND_CURRENT_PROFILE_INDEX 0x70c336#define R700_TARGET_AND_CURRENT_PROFILE_INDEX 0x66c337 338#define RADEON_CACHE_CNTL 0x1724339#define RADEON_CACHE_LINE 0x0f0c /* PCI */340#define RADEON_CAPABILITIES_ID 0x0f50 /* PCI */341#define RADEON_CAPABILITIES_PTR 0x0f34 /* PCI */342#define RADEON_CLK_PIN_CNTL 0x0001 /* PLL */343# define RADEON_DONT_USE_XTALIN (1 << 4)344# define RADEON_SCLK_DYN_START_CNTL (1 << 15)345#define RADEON_CLOCK_CNTL_DATA 0x000c346#define RADEON_CLOCK_CNTL_INDEX 0x0008347# define RADEON_PLL_WR_EN (1 << 7)348# define RADEON_PLL_DIV_SEL (3 << 8)349# define RADEON_PLL2_DIV_SEL_MASK (~(3 << 8))350#define RADEON_CLK_PWRMGT_CNTL 0x0014351# define RADEON_ENGIN_DYNCLK_MODE (1 << 12)352# define RADEON_ACTIVE_HILO_LAT_MASK (3 << 13)353# define RADEON_ACTIVE_HILO_LAT_SHIFT 13354# define RADEON_DISP_DYN_STOP_LAT_MASK (1 << 12)355# define RADEON_MC_BUSY (1 << 16)356# define RADEON_DLL_READY (1 << 19)357# define RADEON_CG_NO1_DEBUG_0 (1 << 24)358# define RADEON_CG_NO1_DEBUG_MASK (0x1f << 24)359# define RADEON_DYN_STOP_MODE_MASK (7 << 21)360# define RADEON_TVPLL_PWRMGT_OFF (1 << 30)361# define RADEON_TVCLK_TURNOFF (1 << 31)362#define RADEON_PLL_PWRMGT_CNTL 0x0015 /* PLL */363# define RADEON_PM_MODE_SEL (1 << 13)364# define RADEON_TCL_BYPASS_DISABLE (1 << 20)365#define RADEON_CLR_CMP_CLR_3D 0x1a24366#define RADEON_CLR_CMP_CLR_DST 0x15c8367#define RADEON_CLR_CMP_CLR_SRC 0x15c4368#define RADEON_CLR_CMP_CNTL 0x15c0369# define RADEON_SRC_CMP_EQ_COLOR (4 << 0)370# define RADEON_SRC_CMP_NEQ_COLOR (5 << 0)371# define RADEON_CLR_CMP_SRC_SOURCE (1 << 24)372#define RADEON_CLR_CMP_MASK 0x15cc373# define RADEON_CLR_CMP_MSK 0xffffffff374#define RADEON_CLR_CMP_MASK_3D 0x1A28375#define RADEON_COMMAND 0x0f04 /* PCI */376#define RADEON_COMPOSITE_SHADOW_ID 0x1a0c377#define RADEON_CONFIG_APER_0_BASE 0x0100378#define RADEON_CONFIG_APER_1_BASE 0x0104379#define RADEON_CONFIG_APER_SIZE 0x0108380#define RADEON_CONFIG_BONDS 0x00e8381#define RADEON_CONFIG_CNTL 0x00e0382# define RADEON_CFG_VGA_RAM_EN (1 << 8)383# define RADEON_CFG_VGA_IO_DIS (1 << 9)384# define RADEON_CFG_ATI_REV_A11 (0 << 16)385# define RADEON_CFG_ATI_REV_A12 (1 << 16)386# define RADEON_CFG_ATI_REV_A13 (2 << 16)387# define RADEON_CFG_ATI_REV_ID_MASK (0xf << 16)388#define RADEON_CONFIG_MEMSIZE 0x00f8389#define RADEON_CONFIG_MEMSIZE_EMBEDDED 0x0114390#define RADEON_CONFIG_REG_1_BASE 0x010c391#define RADEON_CONFIG_REG_APER_SIZE 0x0110392#define RADEON_CONFIG_XSTRAP 0x00e4393#define RADEON_CONSTANT_COLOR_C 0x1d34394# define RADEON_CONSTANT_COLOR_MASK 0x00ffffff395# define RADEON_CONSTANT_COLOR_ONE 0x00ffffff396# define RADEON_CONSTANT_COLOR_ZERO 0x00000000397#define RADEON_CRC_CMDFIFO_ADDR 0x0740398#define RADEON_CRC_CMDFIFO_DOUT 0x0744399#define RADEON_GRPH_BUFFER_CNTL 0x02f0400# define RADEON_GRPH_START_REQ_MASK (0x7f)401# define RADEON_GRPH_START_REQ_SHIFT 0402# define RADEON_GRPH_STOP_REQ_MASK (0x7f<<8)403# define RADEON_GRPH_STOP_REQ_SHIFT 8404# define RADEON_GRPH_CRITICAL_POINT_MASK (0x7f<<16)405# define RADEON_GRPH_CRITICAL_POINT_SHIFT 16406# define RADEON_GRPH_CRITICAL_CNTL (1<<28)407# define RADEON_GRPH_BUFFER_SIZE (1<<29)408# define RADEON_GRPH_CRITICAL_AT_SOF (1<<30)409# define RADEON_GRPH_STOP_CNTL (1<<31)410#define RADEON_GRPH2_BUFFER_CNTL 0x03f0411# define RADEON_GRPH2_START_REQ_MASK (0x7f)412# define RADEON_GRPH2_START_REQ_SHIFT 0413# define RADEON_GRPH2_STOP_REQ_MASK (0x7f<<8)414# define RADEON_GRPH2_STOP_REQ_SHIFT 8415# define RADEON_GRPH2_CRITICAL_POINT_MASK (0x7f<<16)416# define RADEON_GRPH2_CRITICAL_POINT_SHIFT 16417# define RADEON_GRPH2_CRITICAL_CNTL (1<<28)418# define RADEON_GRPH2_BUFFER_SIZE (1<<29)419# define RADEON_GRPH2_CRITICAL_AT_SOF (1<<30)420# define RADEON_GRPH2_STOP_CNTL (1<<31)421#define RADEON_CRTC_CRNT_FRAME 0x0214422#define RADEON_CRTC_EXT_CNTL 0x0054423# define RADEON_CRTC_VGA_XOVERSCAN (1 << 0)424# define RADEON_VGA_ATI_LINEAR (1 << 3)425# define RADEON_XCRT_CNT_EN (1 << 6)426# define RADEON_CRTC_HSYNC_DIS (1 << 8)427# define RADEON_CRTC_VSYNC_DIS (1 << 9)428# define RADEON_CRTC_DISPLAY_DIS (1 << 10)429# define RADEON_CRTC_SYNC_TRISTAT (1 << 11)430# define RADEON_CRTC_CRT_ON (1 << 15)431#define RADEON_CRTC_EXT_CNTL_DPMS_BYTE 0x0055432# define RADEON_CRTC_HSYNC_DIS_BYTE (1 << 0)433# define RADEON_CRTC_VSYNC_DIS_BYTE (1 << 1)434# define RADEON_CRTC_DISPLAY_DIS_BYTE (1 << 2)435#define RADEON_CRTC_GEN_CNTL 0x0050436# define RADEON_CRTC_DBL_SCAN_EN (1 << 0)437# define RADEON_CRTC_INTERLACE_EN (1 << 1)438# define RADEON_CRTC_CSYNC_EN (1 << 4)439# define RADEON_CRTC_ICON_EN (1 << 15)440# define RADEON_CRTC_CUR_EN (1 << 16)441# define RADEON_CRTC_VSTAT_MODE_MASK (3 << 17)442# define RADEON_CRTC_CUR_MODE_MASK (7 << 20)443# define RADEON_CRTC_CUR_MODE_SHIFT 20444# define RADEON_CRTC_CUR_MODE_MONO 0445# define RADEON_CRTC_CUR_MODE_24BPP 2446# define RADEON_CRTC_EXT_DISP_EN (1 << 24)447# define RADEON_CRTC_EN (1 << 25)448# define RADEON_CRTC_DISP_REQ_EN_B (1 << 26)449#define RADEON_CRTC2_GEN_CNTL 0x03f8450# define RADEON_CRTC2_DBL_SCAN_EN (1 << 0)451# define RADEON_CRTC2_INTERLACE_EN (1 << 1)452# define RADEON_CRTC2_SYNC_TRISTAT (1 << 4)453# define RADEON_CRTC2_HSYNC_TRISTAT (1 << 5)454# define RADEON_CRTC2_VSYNC_TRISTAT (1 << 6)455# define RADEON_CRTC2_CRT2_ON (1 << 7)456# define RADEON_CRTC2_PIX_WIDTH_SHIFT 8457# define RADEON_CRTC2_PIX_WIDTH_MASK (0xf << 8)458# define RADEON_CRTC2_ICON_EN (1 << 15)459# define RADEON_CRTC2_CUR_EN (1 << 16)460# define RADEON_CRTC2_CUR_MODE_MASK (7 << 20)461# define RADEON_CRTC2_DISP_DIS (1 << 23)462# define RADEON_CRTC2_EN (1 << 25)463# define RADEON_CRTC2_DISP_REQ_EN_B (1 << 26)464# define RADEON_CRTC2_CSYNC_EN (1 << 27)465# define RADEON_CRTC2_HSYNC_DIS (1 << 28)466# define RADEON_CRTC2_VSYNC_DIS (1 << 29)467#define RADEON_CRTC_MORE_CNTL 0x27c468# define RADEON_CRTC_AUTO_HORZ_CENTER_EN (1<<2)469# define RADEON_CRTC_AUTO_VERT_CENTER_EN (1<<3)470# define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4)471# define RADEON_CRTC_V_CUTOFF_ACTIVE_EN (1<<5)472#define RADEON_CRTC_GUI_TRIG_VLINE 0x0218473#define RADEON_CRTC_H_SYNC_STRT_WID 0x0204474# define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0)475# define RADEON_CRTC_H_SYNC_STRT_CHAR (0x3ff << 3)476# define RADEON_CRTC_H_SYNC_STRT_CHAR_SHIFT 3477# define RADEON_CRTC_H_SYNC_WID (0x3f << 16)478# define RADEON_CRTC_H_SYNC_WID_SHIFT 16479# define RADEON_CRTC_H_SYNC_POL (1 << 23)480#define RADEON_CRTC2_H_SYNC_STRT_WID 0x0304481# define RADEON_CRTC2_H_SYNC_STRT_PIX (0x07 << 0)482# define RADEON_CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3)483# define RADEON_CRTC2_H_SYNC_STRT_CHAR_SHIFT 3484# define RADEON_CRTC2_H_SYNC_WID (0x3f << 16)485# define RADEON_CRTC2_H_SYNC_WID_SHIFT 16486# define RADEON_CRTC2_H_SYNC_POL (1 << 23)487#define RADEON_CRTC_H_TOTAL_DISP 0x0200488# define RADEON_CRTC_H_TOTAL (0x03ff << 0)489# define RADEON_CRTC_H_TOTAL_SHIFT 0490# define RADEON_CRTC_H_DISP (0x01ff << 16)491# define RADEON_CRTC_H_DISP_SHIFT 16492#define RADEON_CRTC2_H_TOTAL_DISP 0x0300493# define RADEON_CRTC2_H_TOTAL (0x03ff << 0)494# define RADEON_CRTC2_H_TOTAL_SHIFT 0495# define RADEON_CRTC2_H_DISP (0x01ff << 16)496# define RADEON_CRTC2_H_DISP_SHIFT 16497 498#define RADEON_CRTC_OFFSET_RIGHT 0x0220499#define RADEON_CRTC_OFFSET 0x0224500# define RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET (1<<30)501# define RADEON_CRTC_OFFSET__OFFSET_LOCK (1<<31)502 503#define RADEON_CRTC2_OFFSET 0x0324504# define RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET (1<<30)505# define RADEON_CRTC2_OFFSET__OFFSET_LOCK (1<<31)506#define RADEON_CRTC_OFFSET_CNTL 0x0228507# define RADEON_CRTC_TILE_LINE_SHIFT 0508# define RADEON_CRTC_TILE_LINE_RIGHT_SHIFT 4509# define R300_CRTC_X_Y_MODE_EN_RIGHT (1 << 6)510# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_MASK (3 << 7)511# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_AUTO (0 << 7)512# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_SINGLE (1 << 7)513# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DOUBLE (2 << 7)514# define R300_CRTC_MICRO_TILE_BUFFER_RIGHT_DIS (3 << 7)515# define R300_CRTC_X_Y_MODE_EN (1 << 9)516# define R300_CRTC_MICRO_TILE_BUFFER_MASK (3 << 10)517# define R300_CRTC_MICRO_TILE_BUFFER_AUTO (0 << 10)518# define R300_CRTC_MICRO_TILE_BUFFER_SINGLE (1 << 10)519# define R300_CRTC_MICRO_TILE_BUFFER_DOUBLE (2 << 10)520# define R300_CRTC_MICRO_TILE_BUFFER_DIS (3 << 10)521# define R300_CRTC_MICRO_TILE_EN_RIGHT (1 << 12)522# define R300_CRTC_MICRO_TILE_EN (1 << 13)523# define R300_CRTC_MACRO_TILE_EN_RIGHT (1 << 14)524# define R300_CRTC_MACRO_TILE_EN (1 << 15)525# define RADEON_CRTC_TILE_EN_RIGHT (1 << 14)526# define RADEON_CRTC_TILE_EN (1 << 15)527# define RADEON_CRTC_OFFSET_FLIP_CNTL (1 << 16)528# define RADEON_CRTC_STEREO_OFFSET_EN (1 << 17)529# define RADEON_CRTC_GUI_TRIG_OFFSET_LEFT_EN (1 << 28)530# define RADEON_CRTC_GUI_TRIG_OFFSET_RIGHT_EN (1 << 29)531 532#define R300_CRTC_TILE_X0_Y0 0x0350533#define R300_CRTC2_TILE_X0_Y0 0x0358534 535#define RADEON_CRTC2_OFFSET_CNTL 0x0328536# define RADEON_CRTC2_OFFSET_FLIP_CNTL (1 << 16)537# define RADEON_CRTC2_TILE_EN (1 << 15)538#define RADEON_CRTC_PITCH 0x022c539# define RADEON_CRTC_PITCH__SHIFT 0540# define RADEON_CRTC_PITCH__RIGHT_SHIFT 16541 542#define RADEON_CRTC2_PITCH 0x032c543#define RADEON_CRTC_STATUS 0x005c544# define RADEON_CRTC_VBLANK_CUR (1 << 0)545# define RADEON_CRTC_VBLANK_SAVE (1 << 1)546# define RADEON_CRTC_VBLANK_SAVE_CLEAR (1 << 1)547#define RADEON_CRTC2_STATUS 0x03fc548# define RADEON_CRTC2_VBLANK_CUR (1 << 0)549# define RADEON_CRTC2_VBLANK_SAVE (1 << 1)550# define RADEON_CRTC2_VBLANK_SAVE_CLEAR (1 << 1)551#define RADEON_CRTC_V_SYNC_STRT_WID 0x020c552# define RADEON_CRTC_V_SYNC_STRT (0x7ff << 0)553# define RADEON_CRTC_V_SYNC_STRT_SHIFT 0554# define RADEON_CRTC_V_SYNC_WID (0x1f << 16)555# define RADEON_CRTC_V_SYNC_WID_SHIFT 16556# define RADEON_CRTC_V_SYNC_POL (1 << 23)557#define RADEON_CRTC2_V_SYNC_STRT_WID 0x030c558# define RADEON_CRTC2_V_SYNC_STRT (0x7ff << 0)559# define RADEON_CRTC2_V_SYNC_STRT_SHIFT 0560# define RADEON_CRTC2_V_SYNC_WID (0x1f << 16)561# define RADEON_CRTC2_V_SYNC_WID_SHIFT 16562# define RADEON_CRTC2_V_SYNC_POL (1 << 23)563#define RADEON_CRTC_V_TOTAL_DISP 0x0208564# define RADEON_CRTC_V_TOTAL (0x07ff << 0)565# define RADEON_CRTC_V_TOTAL_SHIFT 0566# define RADEON_CRTC_V_DISP (0x07ff << 16)567# define RADEON_CRTC_V_DISP_SHIFT 16568#define RADEON_CRTC2_V_TOTAL_DISP 0x0308569# define RADEON_CRTC2_V_TOTAL (0x07ff << 0)570# define RADEON_CRTC2_V_TOTAL_SHIFT 0571# define RADEON_CRTC2_V_DISP (0x07ff << 16)572# define RADEON_CRTC2_V_DISP_SHIFT 16573#define RADEON_CRTC_VLINE_CRNT_VLINE 0x0210574# define RADEON_CRTC_CRNT_VLINE_MASK (0x7ff << 16)575#define RADEON_CRTC2_CRNT_FRAME 0x0314576#define RADEON_CRTC2_GUI_TRIG_VLINE 0x0318577#define RADEON_CRTC2_VLINE_CRNT_VLINE 0x0310578#define RADEON_CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */579#define RADEON_CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */580#define RADEON_CUR_CLR0 0x026c581#define RADEON_CUR_CLR1 0x0270582#define RADEON_CUR_HORZ_VERT_OFF 0x0268583#define RADEON_CUR_HORZ_VERT_POSN 0x0264584#define RADEON_CUR_OFFSET 0x0260585# define RADEON_CUR_LOCK (1 << 31)586#define RADEON_CUR2_CLR0 0x036c587#define RADEON_CUR2_CLR1 0x0370588#define RADEON_CUR2_HORZ_VERT_OFF 0x0368589#define RADEON_CUR2_HORZ_VERT_POSN 0x0364590#define RADEON_CUR2_OFFSET 0x0360591# define RADEON_CUR2_LOCK (1 << 31)592 593#define RADEON_DAC_CNTL 0x0058594# define RADEON_DAC_RANGE_CNTL (3 << 0)595# define RADEON_DAC_RANGE_CNTL_PS2 (2 << 0)596# define RADEON_DAC_RANGE_CNTL_MASK 0x03597# define RADEON_DAC_BLANKING (1 << 2)598# define RADEON_DAC_CMP_EN (1 << 3)599# define RADEON_DAC_CMP_OUTPUT (1 << 7)600# define RADEON_DAC_8BIT_EN (1 << 8)601# define RADEON_DAC_TVO_EN (1 << 10)602# define RADEON_DAC_VGA_ADR_EN (1 << 13)603# define RADEON_DAC_PDWN (1 << 15)604# define RADEON_DAC_MASK_ALL (0xff << 24)605#define RADEON_DAC_CNTL2 0x007c606# define RADEON_DAC2_TV_CLK_SEL (0 << 1)607# define RADEON_DAC2_DAC_CLK_SEL (1 << 0)608# define RADEON_DAC2_DAC2_CLK_SEL (1 << 1)609# define RADEON_DAC2_PALETTE_ACC_CTL (1 << 5)610# define RADEON_DAC2_CMP_EN (1 << 7)611# define RADEON_DAC2_CMP_OUT_R (1 << 8)612# define RADEON_DAC2_CMP_OUT_G (1 << 9)613# define RADEON_DAC2_CMP_OUT_B (1 << 10)614# define RADEON_DAC2_CMP_OUTPUT (1 << 11)615#define RADEON_DAC_EXT_CNTL 0x0280616# define RADEON_DAC2_FORCE_BLANK_OFF_EN (1 << 0)617# define RADEON_DAC2_FORCE_DATA_EN (1 << 1)618# define RADEON_DAC_FORCE_BLANK_OFF_EN (1 << 4)619# define RADEON_DAC_FORCE_DATA_EN (1 << 5)620# define RADEON_DAC_FORCE_DATA_SEL_MASK (3 << 6)621# define RADEON_DAC_FORCE_DATA_SEL_R (0 << 6)622# define RADEON_DAC_FORCE_DATA_SEL_G (1 << 6)623# define RADEON_DAC_FORCE_DATA_SEL_B (2 << 6)624# define RADEON_DAC_FORCE_DATA_SEL_RGB (3 << 6)625# define RADEON_DAC_FORCE_DATA_MASK 0x0003ff00626# define RADEON_DAC_FORCE_DATA_SHIFT 8627#define RADEON_DAC_MACRO_CNTL 0x0d04628# define RADEON_DAC_PDWN_R (1 << 16)629# define RADEON_DAC_PDWN_G (1 << 17)630# define RADEON_DAC_PDWN_B (1 << 18)631#define RADEON_DISP_PWR_MAN 0x0d08632# define RADEON_DISP_PWR_MAN_D3_CRTC_EN (1 << 0)633# define RADEON_DISP_PWR_MAN_D3_CRTC2_EN (1 << 4)634# define RADEON_DISP_PWR_MAN_DPMS_ON (0 << 8)635# define RADEON_DISP_PWR_MAN_DPMS_STANDBY (1 << 8)636# define RADEON_DISP_PWR_MAN_DPMS_SUSPEND (2 << 8)637# define RADEON_DISP_PWR_MAN_DPMS_OFF (3 << 8)638# define RADEON_DISP_D3_RST (1 << 16)639# define RADEON_DISP_D3_REG_RST (1 << 17)640# define RADEON_DISP_D3_GRPH_RST (1 << 18)641# define RADEON_DISP_D3_SUBPIC_RST (1 << 19)642# define RADEON_DISP_D3_OV0_RST (1 << 20)643# define RADEON_DISP_D1D2_GRPH_RST (1 << 21)644# define RADEON_DISP_D1D2_SUBPIC_RST (1 << 22)645# define RADEON_DISP_D1D2_OV0_RST (1 << 23)646# define RADEON_DIG_TMDS_ENABLE_RST (1 << 24)647# define RADEON_TV_ENABLE_RST (1 << 25)648# define RADEON_AUTO_PWRUP_EN (1 << 26)649#define RADEON_TV_DAC_CNTL 0x088c650# define RADEON_TV_DAC_NBLANK (1 << 0)651# define RADEON_TV_DAC_NHOLD (1 << 1)652# define RADEON_TV_DAC_PEDESTAL (1 << 2)653# define RADEON_TV_MONITOR_DETECT_EN (1 << 4)654# define RADEON_TV_DAC_CMPOUT (1 << 5)655# define RADEON_TV_DAC_STD_MASK (3 << 8)656# define RADEON_TV_DAC_STD_PAL (0 << 8)657# define RADEON_TV_DAC_STD_NTSC (1 << 8)658# define RADEON_TV_DAC_STD_PS2 (2 << 8)659# define RADEON_TV_DAC_STD_RS343 (3 << 8)660# define RADEON_TV_DAC_BGSLEEP (1 << 6)661# define RADEON_TV_DAC_BGADJ_MASK (0xf << 16)662# define RADEON_TV_DAC_BGADJ_SHIFT 16663# define RADEON_TV_DAC_DACADJ_MASK (0xf << 20)664# define RADEON_TV_DAC_DACADJ_SHIFT 20665# define RADEON_TV_DAC_RDACPD (1 << 24)666# define RADEON_TV_DAC_GDACPD (1 << 25)667# define RADEON_TV_DAC_BDACPD (1 << 26)668# define RADEON_TV_DAC_RDACDET (1 << 29)669# define RADEON_TV_DAC_GDACDET (1 << 30)670# define RADEON_TV_DAC_BDACDET (1 << 31)671# define R420_TV_DAC_DACADJ_MASK (0x1f << 20)672# define R420_TV_DAC_RDACPD (1 << 25)673# define R420_TV_DAC_GDACPD (1 << 26)674# define R420_TV_DAC_BDACPD (1 << 27)675# define R420_TV_DAC_TVENABLE (1 << 28)676#define RADEON_DISP_HW_DEBUG 0x0d14677# define RADEON_CRT2_DISP1_SEL (1 << 5)678#define RADEON_DISP_OUTPUT_CNTL 0x0d64679# define RADEON_DISP_DAC_SOURCE_MASK 0x03680# define RADEON_DISP_DAC2_SOURCE_MASK 0x0c681# define RADEON_DISP_DAC_SOURCE_CRTC2 0x01682# define RADEON_DISP_DAC_SOURCE_RMX 0x02683# define RADEON_DISP_DAC_SOURCE_LTU 0x03684# define RADEON_DISP_DAC2_SOURCE_CRTC2 0x04685# define RADEON_DISP_TVDAC_SOURCE_MASK (0x03 << 2)686# define RADEON_DISP_TVDAC_SOURCE_CRTC 0x0687# define RADEON_DISP_TVDAC_SOURCE_CRTC2 (0x01 << 2)688# define RADEON_DISP_TVDAC_SOURCE_RMX (0x02 << 2)689# define RADEON_DISP_TVDAC_SOURCE_LTU (0x03 << 2)690# define RADEON_DISP_TRANS_MATRIX_MASK (0x03 << 4)691# define RADEON_DISP_TRANS_MATRIX_ALPHA_MSB (0x00 << 4)692# define RADEON_DISP_TRANS_MATRIX_GRAPHICS (0x01 << 4)693# define RADEON_DISP_TRANS_MATRIX_VIDEO (0x02 << 4)694# define RADEON_DISP_TV_SOURCE_CRTC (1 << 16) /* crtc1 or crtc2 */695# define RADEON_DISP_TV_SOURCE_LTU (0 << 16) /* linear transform unit */696#define RADEON_DISP_TV_OUT_CNTL 0x0d6c697# define RADEON_DISP_TV_PATH_SRC_CRTC2 (1 << 16)698# define RADEON_DISP_TV_PATH_SRC_CRTC1 (0 << 16)699#define RADEON_DAC_CRC_SIG 0x02cc700#define RADEON_DAC_DATA 0x03c9 /* VGA */701#define RADEON_DAC_MASK 0x03c6 /* VGA */702#define RADEON_DAC_R_INDEX 0x03c7 /* VGA */703#define RADEON_DAC_W_INDEX 0x03c8 /* VGA */704#define RADEON_DDA_CONFIG 0x02e0705#define RADEON_DDA_ON_OFF 0x02e4706#define RADEON_DEFAULT_OFFSET 0x16e0707#define RADEON_DEFAULT_PITCH 0x16e4708#define RADEON_DEFAULT_SC_BOTTOM_RIGHT 0x16e8709# define RADEON_DEFAULT_SC_RIGHT_MAX (0x1fff << 0)710# define RADEON_DEFAULT_SC_BOTTOM_MAX (0x1fff << 16)711#define RADEON_DESTINATION_3D_CLR_CMP_VAL 0x1820712#define RADEON_DESTINATION_3D_CLR_CMP_MSK 0x1824713#define RADEON_DEVICE_ID 0x0f02 /* PCI */714#define RADEON_DISP_MISC_CNTL 0x0d00715# define RADEON_SOFT_RESET_GRPH_PP (1 << 0)716#define RADEON_DISP_MERGE_CNTL 0x0d60717# define RADEON_DISP_ALPHA_MODE_MASK 0x03718# define RADEON_DISP_ALPHA_MODE_KEY 0719# define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1720# define RADEON_DISP_ALPHA_MODE_GLOBAL 2721# define RADEON_DISP_RGB_OFFSET_EN (1 << 8)722# define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16)723# define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24)724# define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9)725#define RADEON_DISP2_MERGE_CNTL 0x0d68726# define RADEON_DISP2_RGB_OFFSET_EN (1 << 8)727#define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80728#define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84729#define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88730#define RADEON_DISP_LIN_TRANS_GRPH_D 0x0d8c731#define RADEON_DISP_LIN_TRANS_GRPH_E 0x0d90732#define RADEON_DISP_LIN_TRANS_GRPH_F 0x0d98733#define RADEON_DP_BRUSH_BKGD_CLR 0x1478734#define RADEON_DP_BRUSH_FRGD_CLR 0x147c735#define RADEON_DP_CNTL 0x16c0736# define RADEON_DST_X_LEFT_TO_RIGHT (1 << 0)737# define RADEON_DST_Y_TOP_TO_BOTTOM (1 << 1)738# define RADEON_DP_DST_TILE_LINEAR (0 << 3)739# define RADEON_DP_DST_TILE_MACRO (1 << 3)740# define RADEON_DP_DST_TILE_MICRO (2 << 3)741# define RADEON_DP_DST_TILE_BOTH (3 << 3)742#define RADEON_DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0743# define RADEON_DST_Y_MAJOR (1 << 2)744# define RADEON_DST_Y_DIR_TOP_TO_BOTTOM (1 << 15)745# define RADEON_DST_X_DIR_LEFT_TO_RIGHT (1 << 31)746#define RADEON_DP_DATATYPE 0x16c4747# define RADEON_HOST_BIG_ENDIAN_EN (1 << 29)748#define RADEON_DP_GUI_MASTER_CNTL 0x146c749# define RADEON_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)750# define RADEON_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)751# define RADEON_GMC_SRC_CLIPPING (1 << 2)752# define RADEON_GMC_DST_CLIPPING (1 << 3)753# define RADEON_GMC_BRUSH_DATATYPE_MASK (0x0f << 4)754# define RADEON_GMC_BRUSH_8X8_MONO_FG_BG (0 << 4)755# define RADEON_GMC_BRUSH_8X8_MONO_FG_LA (1 << 4)756# define RADEON_GMC_BRUSH_1X8_MONO_FG_BG (4 << 4)757# define RADEON_GMC_BRUSH_1X8_MONO_FG_LA (5 << 4)758# define RADEON_GMC_BRUSH_32x1_MONO_FG_BG (6 << 4)759# define RADEON_GMC_BRUSH_32x1_MONO_FG_LA (7 << 4)760# define RADEON_GMC_BRUSH_32x32_MONO_FG_BG (8 << 4)761# define RADEON_GMC_BRUSH_32x32_MONO_FG_LA (9 << 4)762# define RADEON_GMC_BRUSH_8x8_COLOR (10 << 4)763# define RADEON_GMC_BRUSH_1X8_COLOR (12 << 4)764# define RADEON_GMC_BRUSH_SOLID_COLOR (13 << 4)765# define RADEON_GMC_BRUSH_NONE (15 << 4)766# define RADEON_GMC_DST_8BPP_CI (2 << 8)767# define RADEON_GMC_DST_15BPP (3 << 8)768# define RADEON_GMC_DST_16BPP (4 << 8)769# define RADEON_GMC_DST_24BPP (5 << 8)770# define RADEON_GMC_DST_32BPP (6 << 8)771# define RADEON_GMC_DST_8BPP_RGB (7 << 8)772# define RADEON_GMC_DST_Y8 (8 << 8)773# define RADEON_GMC_DST_RGB8 (9 << 8)774# define RADEON_GMC_DST_VYUY (11 << 8)775# define RADEON_GMC_DST_YVYU (12 << 8)776# define RADEON_GMC_DST_AYUV444 (14 << 8)777# define RADEON_GMC_DST_ARGB4444 (15 << 8)778# define RADEON_GMC_DST_DATATYPE_MASK (0x0f << 8)779# define RADEON_GMC_DST_DATATYPE_SHIFT 8780# define RADEON_GMC_SRC_DATATYPE_MASK (3 << 12)781# define RADEON_GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12)782# define RADEON_GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12)783# define RADEON_GMC_SRC_DATATYPE_COLOR (3 << 12)784# define RADEON_GMC_BYTE_PIX_ORDER (1 << 14)785# define RADEON_GMC_BYTE_MSB_TO_LSB (0 << 14)786# define RADEON_GMC_BYTE_LSB_TO_MSB (1 << 14)787# define RADEON_GMC_CONVERSION_TEMP (1 << 15)788# define RADEON_GMC_CONVERSION_TEMP_6500 (0 << 15)789# define RADEON_GMC_CONVERSION_TEMP_9300 (1 << 15)790# define RADEON_GMC_ROP3_MASK (0xff << 16)791# define RADEON_DP_SRC_SOURCE_MASK (7 << 24)792# define RADEON_DP_SRC_SOURCE_MEMORY (2 << 24)793# define RADEON_DP_SRC_SOURCE_HOST_DATA (3 << 24)794# define RADEON_GMC_3D_FCN_EN (1 << 27)795# define RADEON_GMC_CLR_CMP_CNTL_DIS (1 << 28)796# define RADEON_GMC_AUX_CLIP_DIS (1 << 29)797# define RADEON_GMC_WR_MSK_DIS (1 << 30)798# define RADEON_GMC_LD_BRUSH_Y_X (1 << 31)799# define RADEON_ROP3_ZERO 0x00000000800# define RADEON_ROP3_DSa 0x00880000801# define RADEON_ROP3_SDna 0x00440000802# define RADEON_ROP3_S 0x00cc0000803# define RADEON_ROP3_DSna 0x00220000804# define RADEON_ROP3_D 0x00aa0000805# define RADEON_ROP3_DSx 0x00660000806# define RADEON_ROP3_DSo 0x00ee0000807# define RADEON_ROP3_DSon 0x00110000808# define RADEON_ROP3_DSxn 0x00990000809# define RADEON_ROP3_Dn 0x00550000810# define RADEON_ROP3_SDno 0x00dd0000811# define RADEON_ROP3_Sn 0x00330000812# define RADEON_ROP3_DSno 0x00bb0000813# define RADEON_ROP3_DSan 0x00770000814# define RADEON_ROP3_ONE 0x00ff0000815# define RADEON_ROP3_DPa 0x00a00000816# define RADEON_ROP3_PDna 0x00500000817# define RADEON_ROP3_P 0x00f00000818# define RADEON_ROP3_DPna 0x000a0000819# define RADEON_ROP3_D 0x00aa0000820# define RADEON_ROP3_DPx 0x005a0000821# define RADEON_ROP3_DPo 0x00fa0000822# define RADEON_ROP3_DPon 0x00050000823# define RADEON_ROP3_PDxn 0x00a50000824# define RADEON_ROP3_PDno 0x00f50000825# define RADEON_ROP3_Pn 0x000f0000826# define RADEON_ROP3_DPno 0x00af0000827# define RADEON_ROP3_DPan 0x005f0000828#define RADEON_DP_GUI_MASTER_CNTL_C 0x1c84829#define RADEON_DP_MIX 0x16c8830#define RADEON_DP_SRC_BKGD_CLR 0x15dc831#define RADEON_DP_SRC_FRGD_CLR 0x15d8832#define RADEON_DP_WRITE_MASK 0x16cc833#define RADEON_DST_BRES_DEC 0x1630834#define RADEON_DST_BRES_ERR 0x1628835#define RADEON_DST_BRES_INC 0x162c836#define RADEON_DST_BRES_LNTH 0x1634837#define RADEON_DST_BRES_LNTH_SUB 0x1638838#define RADEON_DST_HEIGHT 0x1410839#define RADEON_DST_HEIGHT_WIDTH 0x143c840#define RADEON_DST_HEIGHT_WIDTH_8 0x158c841#define RADEON_DST_HEIGHT_WIDTH_BW 0x15b4842#define RADEON_DST_HEIGHT_Y 0x15a0843#define RADEON_DST_LINE_START 0x1600844#define RADEON_DST_LINE_END 0x1604845#define RADEON_DST_LINE_PATCOUNT 0x1608846# define RADEON_BRES_CNTL_SHIFT 8847#define RADEON_DST_OFFSET 0x1404848#define RADEON_DST_PITCH 0x1408849#define RADEON_DST_PITCH_OFFSET 0x142c850#define RADEON_DST_PITCH_OFFSET_C 0x1c80851# define RADEON_PITCH_SHIFT 21852# define RADEON_DST_TILE_LINEAR (0 << 30)853# define RADEON_DST_TILE_MACRO (1 << 30)854# define RADEON_DST_TILE_MICRO (2 << 30)855# define RADEON_DST_TILE_BOTH (3 << 30)856#define RADEON_DST_WIDTH 0x140c857#define RADEON_DST_WIDTH_HEIGHT 0x1598858#define RADEON_DST_WIDTH_X 0x1588859#define RADEON_DST_WIDTH_X_INCY 0x159c860#define RADEON_DST_X 0x141c861#define RADEON_DST_X_SUB 0x15a4862#define RADEON_DST_X_Y 0x1594863#define RADEON_DST_Y 0x1420864#define RADEON_DST_Y_SUB 0x15a8865#define RADEON_DST_Y_X 0x1438866 867#define RADEON_FCP_CNTL 0x0910868# define RADEON_FCP0_SRC_PCICLK 0869# define RADEON_FCP0_SRC_PCLK 1870# define RADEON_FCP0_SRC_PCLKb 2871# define RADEON_FCP0_SRC_HREF 3872# define RADEON_FCP0_SRC_GND 4873# define RADEON_FCP0_SRC_HREFb 5874#define RADEON_FLUSH_1 0x1704875#define RADEON_FLUSH_2 0x1708876#define RADEON_FLUSH_3 0x170c877#define RADEON_FLUSH_4 0x1710878#define RADEON_FLUSH_5 0x1714879#define RADEON_FLUSH_6 0x1718880#define RADEON_FLUSH_7 0x171c881#define RADEON_FOG_3D_TABLE_START 0x1810882#define RADEON_FOG_3D_TABLE_END 0x1814883#define RADEON_FOG_3D_TABLE_DENSITY 0x181c884#define RADEON_FOG_TABLE_INDEX 0x1a14885#define RADEON_FOG_TABLE_DATA 0x1a18886#define RADEON_FP_CRTC_H_TOTAL_DISP 0x0250887#define RADEON_FP_CRTC_V_TOTAL_DISP 0x0254888# define RADEON_FP_CRTC_H_TOTAL_MASK 0x000003ff889# define RADEON_FP_CRTC_H_DISP_MASK 0x01ff0000890# define RADEON_FP_CRTC_V_TOTAL_MASK 0x00000fff891# define RADEON_FP_CRTC_V_DISP_MASK 0x0fff0000892# define RADEON_FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8893# define RADEON_FP_H_SYNC_WID_MASK 0x003f0000894# define RADEON_FP_V_SYNC_STRT_MASK 0x00000fff895# define RADEON_FP_V_SYNC_WID_MASK 0x001f0000896# define RADEON_FP_CRTC_H_TOTAL_SHIFT 0x00000000897# define RADEON_FP_CRTC_H_DISP_SHIFT 0x00000010898# define RADEON_FP_CRTC_V_TOTAL_SHIFT 0x00000000899# define RADEON_FP_CRTC_V_DISP_SHIFT 0x00000010900# define RADEON_FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003901# define RADEON_FP_H_SYNC_WID_SHIFT 0x00000010902# define RADEON_FP_V_SYNC_STRT_SHIFT 0x00000000903# define RADEON_FP_V_SYNC_WID_SHIFT 0x00000010904#define RADEON_FP_GEN_CNTL 0x0284905# define RADEON_FP_FPON (1 << 0)906# define RADEON_FP_BLANK_EN (1 << 1)907# define RADEON_FP_TMDS_EN (1 << 2)908# define RADEON_FP_PANEL_FORMAT (1 << 3)909# define RADEON_FP_EN_TMDS (1 << 7)910# define RADEON_FP_DETECT_SENSE (1 << 8)911# define RADEON_FP_DETECT_INT_POL (1 << 9)912# define R200_FP_SOURCE_SEL_MASK (3 << 10)913# define R200_FP_SOURCE_SEL_CRTC1 (0 << 10)914# define R200_FP_SOURCE_SEL_CRTC2 (1 << 10)915# define R200_FP_SOURCE_SEL_RMX (2 << 10)916# define R200_FP_SOURCE_SEL_TRANS (3 << 10)917# define RADEON_FP_SEL_CRTC1 (0 << 13)918# define RADEON_FP_SEL_CRTC2 (1 << 13)919# define R300_HPD_SEL(x) ((x) << 13)920# define RADEON_FP_CRTC_DONT_SHADOW_HPAR (1 << 15)921# define RADEON_FP_CRTC_DONT_SHADOW_VPAR (1 << 16)922# define RADEON_FP_CRTC_DONT_SHADOW_HEND (1 << 17)923# define RADEON_FP_CRTC_USE_SHADOW_VEND (1 << 18)924# define RADEON_FP_RMX_HVSYNC_CONTROL_EN (1 << 20)925# define RADEON_FP_DFP_SYNC_SEL (1 << 21)926# define RADEON_FP_CRTC_LOCK_8DOT (1 << 22)927# define RADEON_FP_CRT_SYNC_SEL (1 << 23)928# define RADEON_FP_USE_SHADOW_EN (1 << 24)929# define RADEON_FP_CRT_SYNC_ALT (1 << 26)930#define RADEON_FP2_GEN_CNTL 0x0288931# define RADEON_FP2_BLANK_EN (1 << 1)932# define RADEON_FP2_ON (1 << 2)933# define RADEON_FP2_PANEL_FORMAT (1 << 3)934# define RADEON_FP2_DETECT_SENSE (1 << 8)935# define RADEON_FP2_DETECT_INT_POL (1 << 9)936# define R200_FP2_SOURCE_SEL_MASK (3 << 10)937# define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10)938# define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10)939# define R200_FP2_SOURCE_SEL_RMX (2 << 10)940# define R200_FP2_SOURCE_SEL_TRANS_UNIT (3 << 10)941# define RADEON_FP2_SRC_SEL_MASK (3 << 13)942# define RADEON_FP2_SRC_SEL_CRTC2 (1 << 13)943# define RADEON_FP2_FP_POL (1 << 16)944# define RADEON_FP2_LP_POL (1 << 17)945# define RADEON_FP2_SCK_POL (1 << 18)946# define RADEON_FP2_LCD_CNTL_MASK (7 << 19)947# define RADEON_FP2_PAD_FLOP_EN (1 << 22)948# define RADEON_FP2_CRC_EN (1 << 23)949# define RADEON_FP2_CRC_READ_EN (1 << 24)950# define RADEON_FP2_DVO_EN (1 << 25)951# define RADEON_FP2_DVO_RATE_SEL_SDR (1 << 26)952# define R200_FP2_DVO_RATE_SEL_SDR (1 << 27)953# define R300_FP2_DVO_CLOCK_MODE_SINGLE (1 << 28)954# define R300_FP2_DVO_DUAL_CHANNEL_EN (1 << 29)955#define RADEON_FP_H_SYNC_STRT_WID 0x02c4956#define RADEON_FP_H2_SYNC_STRT_WID 0x03c4957#define RADEON_FP_HORZ_STRETCH 0x028c958#define RADEON_FP_HORZ2_STRETCH 0x038c959# define RADEON_HORZ_STRETCH_RATIO_MASK 0xffff960# define RADEON_HORZ_STRETCH_RATIO_MAX 4096961# define RADEON_HORZ_PANEL_SIZE (0x1ff << 16)962# define RADEON_HORZ_PANEL_SHIFT 16963# define RADEON_HORZ_STRETCH_PIXREP (0 << 25)964# define RADEON_HORZ_STRETCH_BLEND (1 << 26)965# define RADEON_HORZ_STRETCH_ENABLE (1 << 25)966# define RADEON_HORZ_AUTO_RATIO (1 << 27)967# define RADEON_HORZ_FP_LOOP_STRETCH (0x7 << 28)968# define RADEON_HORZ_AUTO_RATIO_INC (1 << 31)969#define RADEON_FP_HORZ_VERT_ACTIVE 0x0278970#define RADEON_FP_V_SYNC_STRT_WID 0x02c8971#define RADEON_FP_VERT_STRETCH 0x0290972#define RADEON_FP_V2_SYNC_STRT_WID 0x03c8973#define RADEON_FP_VERT2_STRETCH 0x0390974# define RADEON_VERT_PANEL_SIZE (0xfff << 12)975# define RADEON_VERT_PANEL_SHIFT 12976# define RADEON_VERT_STRETCH_RATIO_MASK 0xfff977# define RADEON_VERT_STRETCH_RATIO_SHIFT 0978# define RADEON_VERT_STRETCH_RATIO_MAX 4096979# define RADEON_VERT_STRETCH_ENABLE (1 << 25)980# define RADEON_VERT_STRETCH_LINEREP (0 << 26)981# define RADEON_VERT_STRETCH_BLEND (1 << 26)982# define RADEON_VERT_AUTO_RATIO_EN (1 << 27)983# define RADEON_VERT_AUTO_RATIO_INC (1 << 31)984# define RADEON_VERT_STRETCH_RESERVED 0x71000000985#define RS400_FP_2ND_GEN_CNTL 0x0384986# define RS400_FP_2ND_ON (1 << 0)987# define RS400_FP_2ND_BLANK_EN (1 << 1)988# define RS400_TMDS_2ND_EN (1 << 2)989# define RS400_PANEL_FORMAT_2ND (1 << 3)990# define RS400_FP_2ND_EN_TMDS (1 << 7)991# define RS400_FP_2ND_DETECT_SENSE (1 << 8)992# define RS400_FP_2ND_SOURCE_SEL_MASK (3 << 10)993# define RS400_FP_2ND_SOURCE_SEL_CRTC1 (0 << 10)994# define RS400_FP_2ND_SOURCE_SEL_CRTC2 (1 << 10)995# define RS400_FP_2ND_SOURCE_SEL_RMX (2 << 10)996# define RS400_FP_2ND_DETECT_EN (1 << 12)997# define RS400_HPD_2ND_SEL (1 << 13)998#define RS400_FP2_2_GEN_CNTL 0x0388999# define RS400_FP2_2_BLANK_EN (1 << 1)1000# define RS400_FP2_2_ON (1 << 2)1001# define RS400_FP2_2_PANEL_FORMAT (1 << 3)1002# define RS400_FP2_2_DETECT_SENSE (1 << 8)1003# define RS400_FP2_2_SOURCE_SEL_MASK (3 << 10)1004# define RS400_FP2_2_SOURCE_SEL_CRTC1 (0 << 10)1005# define RS400_FP2_2_SOURCE_SEL_CRTC2 (1 << 10)1006# define RS400_FP2_2_SOURCE_SEL_RMX (2 << 10)1007# define RS400_FP2_2_DVO2_EN (1 << 25)1008#define RS400_TMDS2_CNTL 0x03941009#define RS400_TMDS2_TRANSMITTER_CNTL 0x03a41010# define RS400_TMDS2_PLLEN (1 << 0)1011# define RS400_TMDS2_PLLRST (1 << 1)1012 1013#define RADEON_GEN_INT_CNTL 0x00401014# define RADEON_CRTC_VBLANK_MASK (1 << 0)1015# define RADEON_FP_DETECT_MASK (1 << 4)1016# define RADEON_CRTC2_VBLANK_MASK (1 << 9)1017# define RADEON_FP2_DETECT_MASK (1 << 10)1018# define RADEON_GUI_IDLE_MASK (1 << 19)1019# define RADEON_SW_INT_ENABLE (1 << 25)1020#define RADEON_GEN_INT_STATUS 0x00441021# define AVIVO_DISPLAY_INT_STATUS (1 << 0)1022# define RADEON_CRTC_VBLANK_STAT (1 << 0)1023# define RADEON_CRTC_VBLANK_STAT_ACK (1 << 0)1024# define RADEON_FP_DETECT_STAT (1 << 4)1025# define RADEON_FP_DETECT_STAT_ACK (1 << 4)1026# define RADEON_CRTC2_VBLANK_STAT (1 << 9)1027# define RADEON_CRTC2_VBLANK_STAT_ACK (1 << 9)1028# define RADEON_FP2_DETECT_STAT (1 << 10)1029# define RADEON_FP2_DETECT_STAT_ACK (1 << 10)1030# define RADEON_GUI_IDLE_STAT (1 << 19)1031# define RADEON_GUI_IDLE_STAT_ACK (1 << 19)1032# define RADEON_SW_INT_FIRE (1 << 26)1033# define RADEON_SW_INT_TEST (1 << 25)1034# define RADEON_SW_INT_TEST_ACK (1 << 25)1035#define RADEON_GENENB 0x03c3 /* VGA */1036#define RADEON_GENFC_RD 0x03ca /* VGA */1037#define RADEON_GENFC_WT 0x03da /* VGA, 0x03ba */1038#define RADEON_GENMO_RD 0x03cc /* VGA */1039#define RADEON_GENMO_WT 0x03c2 /* VGA */1040#define RADEON_GENS0 0x03c2 /* VGA */1041#define RADEON_GENS1 0x03da /* VGA, 0x03ba */1042#define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */ /* DDC3 */1043#define RADEON_GPIO_MONIDB 0x006c1044#define RADEON_GPIO_CRT2_DDC 0x006c1045#define RADEON_GPIO_DVI_DDC 0x0064 /* DDC2 */1046#define RADEON_GPIO_VGA_DDC 0x0060 /* DDC1 */1047# define RADEON_GPIO_A_0 (1 << 0)1048# define RADEON_GPIO_A_1 (1 << 1)1049# define RADEON_GPIO_Y_0 (1 << 8)1050# define RADEON_GPIO_Y_1 (1 << 9)1051# define RADEON_GPIO_Y_SHIFT_0 81052# define RADEON_GPIO_Y_SHIFT_1 91053# define RADEON_GPIO_EN_0 (1 << 16)1054# define RADEON_GPIO_EN_1 (1 << 17)1055# define RADEON_GPIO_MASK_0 (1 << 24) /*??*/1056# define RADEON_GPIO_MASK_1 (1 << 25) /*??*/1057#define RADEON_GRPH8_DATA 0x03cf /* VGA */1058#define RADEON_GRPH8_IDX 0x03ce /* VGA */1059#define RADEON_GUI_SCRATCH_REG0 0x15e01060#define RADEON_GUI_SCRATCH_REG1 0x15e41061#define RADEON_GUI_SCRATCH_REG2 0x15e81062#define RADEON_GUI_SCRATCH_REG3 0x15ec1063#define RADEON_GUI_SCRATCH_REG4 0x15f01064#define RADEON_GUI_SCRATCH_REG5 0x15f41065 1066#define RADEON_HEADER 0x0f0e /* PCI */1067#define RADEON_HOST_DATA0 0x17c01068#define RADEON_HOST_DATA1 0x17c41069#define RADEON_HOST_DATA2 0x17c81070#define RADEON_HOST_DATA3 0x17cc1071#define RADEON_HOST_DATA4 0x17d01072#define RADEON_HOST_DATA5 0x17d41073#define RADEON_HOST_DATA6 0x17d81074#define RADEON_HOST_DATA7 0x17dc1075#define RADEON_HOST_DATA_LAST 0x17e01076#define RADEON_HOST_PATH_CNTL 0x01301077# define RADEON_HP_LIN_RD_CACHE_DIS (1 << 24)1078# define RADEON_HDP_READ_BUFFER_INVALIDATE (1 << 27)1079# define RADEON_HDP_SOFT_RESET (1 << 26)1080# define RADEON_HDP_APER_CNTL (1 << 23)1081#define RADEON_HTOTAL_CNTL 0x0009 /* PLL */1082# define RADEON_HTOT_CNTL_VGA_EN (1 << 28)1083#define RADEON_HTOTAL2_CNTL 0x002e /* PLL */1084 1085 /* Multimedia I2C bus */1086#define RADEON_I2C_CNTL_0 0x00901087# define RADEON_I2C_DONE (1 << 0)1088# define RADEON_I2C_NACK (1 << 1)1089# define RADEON_I2C_HALT (1 << 2)1090# define RADEON_I2C_SOFT_RST (1 << 5)1091# define RADEON_I2C_DRIVE_EN (1 << 6)1092# define RADEON_I2C_DRIVE_SEL (1 << 7)1093# define RADEON_I2C_START (1 << 8)1094# define RADEON_I2C_STOP (1 << 9)1095# define RADEON_I2C_RECEIVE (1 << 10)1096# define RADEON_I2C_ABORT (1 << 11)1097# define RADEON_I2C_GO (1 << 12)1098# define RADEON_I2C_PRESCALE_SHIFT 161099#define RADEON_I2C_CNTL_1 0x00941100# define RADEON_I2C_DATA_COUNT_SHIFT 01101# define RADEON_I2C_ADDR_COUNT_SHIFT 41102# define RADEON_I2C_INTRA_BYTE_DELAY_SHIFT 81103# define RADEON_I2C_SEL (1 << 16)1104# define RADEON_I2C_EN (1 << 17)1105# define RADEON_I2C_TIME_LIMIT_SHIFT 241106#define RADEON_I2C_DATA 0x00981107 1108#define RADEON_DVI_I2C_CNTL_0 0x02e01109# define R200_DVI_I2C_PIN_SEL(x) ((x) << 3)1110# define R200_SEL_DDC1 0 /* depends on asic */1111# define R200_SEL_DDC2 1 /* depends on asic */1112# define R200_SEL_DDC3 2 /* depends on asic */1113# define RADEON_SW_WANTS_TO_USE_DVI_I2C (1 << 13)1114# define RADEON_SW_CAN_USE_DVI_I2C (1 << 13)1115# define RADEON_SW_DONE_USING_DVI_I2C (1 << 14)1116# define RADEON_HW_NEEDS_DVI_I2C (1 << 14)1117# define RADEON_ABORT_HW_DVI_I2C (1 << 15)1118# define RADEON_HW_USING_DVI_I2C (1 << 15)1119#define RADEON_DVI_I2C_CNTL_1 0x02e41120#define RADEON_DVI_I2C_DATA 0x02e81121 1122#define RADEON_INTERRUPT_LINE 0x0f3c /* PCI */1123#define RADEON_INTERRUPT_PIN 0x0f3d /* PCI */1124#define RADEON_IO_BASE 0x0f14 /* PCI */1125 1126#define RADEON_LATENCY 0x0f0d /* PCI */1127#define RADEON_LEAD_BRES_DEC 0x16081128#define RADEON_LEAD_BRES_LNTH 0x161c1129#define RADEON_LEAD_BRES_LNTH_SUB 0x16241130#define RADEON_LVDS_GEN_CNTL 0x02d01131# define RADEON_LVDS_ON (1 << 0)1132# define RADEON_LVDS_DISPLAY_DIS (1 << 1)1133# define RADEON_LVDS_PANEL_TYPE (1 << 2)1134# define RADEON_LVDS_PANEL_FORMAT (1 << 3)1135# define RADEON_LVDS_NO_FM (0 << 4)1136# define RADEON_LVDS_2_GREY (1 << 4)1137# define RADEON_LVDS_4_GREY (2 << 4)1138# define RADEON_LVDS_RST_FM (1 << 6)1139# define RADEON_LVDS_EN (1 << 7)1140# define RADEON_LVDS_BL_MOD_LEVEL_SHIFT 81141# define RADEON_LVDS_BL_MOD_LEVEL_MASK (0xff << 8)1142# define RADEON_LVDS_BL_MOD_EN (1 << 16)1143# define RADEON_LVDS_BL_CLK_SEL (1 << 17)1144# define RADEON_LVDS_DIGON (1 << 18)1145# define RADEON_LVDS_BLON (1 << 19)1146# define RADEON_LVDS_FP_POL_LOW (1 << 20)1147# define RADEON_LVDS_LP_POL_LOW (1 << 21)1148# define RADEON_LVDS_DTM_POL_LOW (1 << 22)1149# define RADEON_LVDS_SEL_CRTC2 (1 << 23)1150# define RADEON_LVDS_FPDI_EN (1 << 27)1151# define RADEON_LVDS_HSYNC_DELAY_SHIFT 281152#define RADEON_LVDS_PLL_CNTL 0x02d41153# define RADEON_HSYNC_DELAY_SHIFT 281154# define RADEON_HSYNC_DELAY_MASK (0xf << 28)1155# define RADEON_LVDS_PLL_EN (1 << 16)1156# define RADEON_LVDS_PLL_RESET (1 << 17)1157# define R300_LVDS_SRC_SEL_MASK (3 << 18)1158# define R300_LVDS_SRC_SEL_CRTC1 (0 << 18)1159# define R300_LVDS_SRC_SEL_CRTC2 (1 << 18)1160# define R300_LVDS_SRC_SEL_RMX (2 << 18)1161#define RADEON_LVDS_SS_GEN_CNTL 0x02ec1162# define RADEON_LVDS_PWRSEQ_DELAY1_SHIFT 161163# define RADEON_LVDS_PWRSEQ_DELAY2_SHIFT 201164 1165#define RADEON_MAX_LATENCY 0x0f3f /* PCI */1166#define RADEON_DISPLAY_BASE_ADDR 0x23c1167#define RADEON_DISPLAY2_BASE_ADDR 0x33c1168#define RADEON_OV0_BASE_ADDR 0x43c1169#define RADEON_NB_TOM 0x15c1170#define R300_MC_INIT_MISC_LAT_TIMER 0x1801171# define R300_MC_DISP0R_INIT_LAT_SHIFT 81172# define R300_MC_DISP0R_INIT_LAT_MASK 0xf1173# define R300_MC_DISP1R_INIT_LAT_SHIFT 121174# define R300_MC_DISP1R_INIT_LAT_MASK 0xf1175#define RADEON_MCLK_CNTL 0x0012 /* PLL */1176# define RADEON_MCLKA_SRC_SEL_MASK 0x71177# define RADEON_FORCEON_MCLKA (1 << 16)1178# define RADEON_FORCEON_MCLKB (1 << 17)1179# define RADEON_FORCEON_YCLKA (1 << 18)1180# define RADEON_FORCEON_YCLKB (1 << 19)1181# define RADEON_FORCEON_MC (1 << 20)1182# define RADEON_FORCEON_AIC (1 << 21)1183# define R300_DISABLE_MC_MCLKA (1 << 21)1184# define R300_DISABLE_MC_MCLKB (1 << 21)1185#define RADEON_MCLK_MISC 0x001f /* PLL */1186# define RADEON_MC_MCLK_MAX_DYN_STOP_LAT (1 << 12)1187# define RADEON_IO_MCLK_MAX_DYN_STOP_LAT (1 << 13)1188# define RADEON_MC_MCLK_DYN_ENABLE (1 << 14)1189# define RADEON_IO_MCLK_DYN_ENABLE (1 << 15)1190 1191#define RADEON_GPIOPAD_MASK 0x01981192#define RADEON_GPIOPAD_A 0x019c1193#define RADEON_GPIOPAD_EN 0x01a01194#define RADEON_GPIOPAD_Y 0x01a41195#define RADEON_MDGPIO_MASK 0x01a81196#define RADEON_MDGPIO_A 0x01ac1197#define RADEON_MDGPIO_EN 0x01b01198#define RADEON_MDGPIO_Y 0x01b41199 1200#define RADEON_MEM_ADDR_CONFIG 0x01481201#define RADEON_MEM_BASE 0x0f10 /* PCI */1202#define RADEON_MEM_CNTL 0x01401203# define RADEON_MEM_NUM_CHANNELS_MASK 0x011204# define RADEON_MEM_USE_B_CH_ONLY (1 << 1)1205# define RV100_HALF_MODE (1 << 3)1206# define R300_MEM_NUM_CHANNELS_MASK 0x031207# define R300_MEM_USE_CD_CH_ONLY (1 << 2)1208#define RADEON_MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */1209#define RADEON_MEM_INIT_LAT_TIMER 0x01541210#define RADEON_MEM_INTF_CNTL 0x014c1211#define RADEON_MEM_SDRAM_MODE_REG 0x01581212# define RADEON_SDRAM_MODE_MASK 0xffff00001213# define RADEON_B3MEM_RESET_MASK 0x6fffffff1214# define RADEON_MEM_CFG_TYPE_DDR (1 << 30)1215#define RADEON_MEM_STR_CNTL 0x01501216# define RADEON_MEM_PWRUP_COMPL_A (1 << 0)1217# define RADEON_MEM_PWRUP_COMPL_B (1 << 1)1218# define R300_MEM_PWRUP_COMPL_C (1 << 2)1219# define R300_MEM_PWRUP_COMPL_D (1 << 3)1220# define RADEON_MEM_PWRUP_COMPLETE 0x031221# define R300_MEM_PWRUP_COMPLETE 0x0f1222#define RADEON_MC_STATUS 0x01501223# define RADEON_MC_IDLE (1 << 2)1224# define R300_MC_IDLE (1 << 4)1225#define RADEON_MEM_VGA_RP_SEL 0x003c1226#define RADEON_MEM_VGA_WP_SEL 0x00381227#define RADEON_MIN_GRANT 0x0f3e /* PCI */1228#define RADEON_MM_DATA 0x00041229#define RADEON_MM_INDEX 0x00001230# define RADEON_MM_APER (1 << 31)1231#define RADEON_MPLL_CNTL 0x000e /* PLL */1232#define RADEON_MPP_TB_CONFIG 0x01c0 /* ? */1233#define RADEON_MPP_GP_CONFIG 0x01c8 /* ? */1234#define RADEON_SEPROM_CNTL1 0x01c01235# define RADEON_SCK_PRESCALE_SHIFT 241236# define RADEON_SCK_PRESCALE_MASK (0xff << 24)1237#define R300_MC_IND_INDEX 0x01f81238# define R300_MC_IND_ADDR_MASK 0x3f1239# define R300_MC_IND_WR_EN (1 << 8)1240#define R300_MC_IND_DATA 0x01fc1241#define R300_MC_READ_CNTL_AB 0x017c1242# define R300_MEM_RBS_POSITION_A_MASK 0x031243#define R300_MC_READ_CNTL_CD_mcind 0x241244# define R300_MEM_RBS_POSITION_C_MASK 0x031245 1246#define RADEON_N_VIF_COUNT 0x02481247 1248#define RADEON_OV0_AUTO_FLIP_CNTL 0x04701249# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x000000071250# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x000000081251# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x000000101252# define RADEON_OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x000000201253# define RADEON_OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x000000401254# define RADEON_OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x000003001255# define RADEON_OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x000100001256# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x000400001257# define RADEON_OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x000800001258# define RADEON_OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x008000001259 1260#define RADEON_OV0_COLOUR_CNTL 0x04E01261#define RADEON_OV0_DEINTERLACE_PATTERN 0x04741262#define RADEON_OV0_EXCLUSIVE_HORZ 0x04081263# define RADEON_EXCL_HORZ_START_MASK 0x000000ff1264# define RADEON_EXCL_HORZ_END_MASK 0x0000ff001265# define RADEON_EXCL_HORZ_BACK_PORCH_MASK 0x00ff00001266# define RADEON_EXCL_HORZ_EXCLUSIVE_EN 0x800000001267#define RADEON_OV0_EXCLUSIVE_VERT 0x040C1268# define RADEON_EXCL_VERT_START_MASK 0x000003ff1269# define RADEON_EXCL_VERT_END_MASK 0x03ff00001270#define RADEON_OV0_FILTER_CNTL 0x04A01271# define RADEON_FILTER_PROGRAMMABLE_COEF 0x01272# define RADEON_FILTER_HC_COEF_HORZ_Y 0x11273# define RADEON_FILTER_HC_COEF_HORZ_UV 0x21274# define RADEON_FILTER_HC_COEF_VERT_Y 0x41275# define RADEON_FILTER_HC_COEF_VERT_UV 0x81276# define RADEON_FILTER_HARDCODED_COEF 0xf1277# define RADEON_FILTER_COEF_MASK 0xf1278 1279#define RADEON_OV0_FOUR_TAP_COEF_0 0x04B01280#define RADEON_OV0_FOUR_TAP_COEF_1 0x04B41281#define RADEON_OV0_FOUR_TAP_COEF_2 0x04B81282#define RADEON_OV0_FOUR_TAP_COEF_3 0x04BC1283#define RADEON_OV0_FOUR_TAP_COEF_4 0x04C01284#define RADEON_OV0_FLAG_CNTL 0x04DC1285#define RADEON_OV0_GAMMA_000_00F 0x0d401286#define RADEON_OV0_GAMMA_010_01F 0x0d441287#define RADEON_OV0_GAMMA_020_03F 0x0d481288#define RADEON_OV0_GAMMA_040_07F 0x0d4c1289#define RADEON_OV0_GAMMA_080_0BF 0x0e001290#define RADEON_OV0_GAMMA_0C0_0FF 0x0e041291#define RADEON_OV0_GAMMA_100_13F 0x0e081292#define RADEON_OV0_GAMMA_140_17F 0x0e0c1293#define RADEON_OV0_GAMMA_180_1BF 0x0e101294#define RADEON_OV0_GAMMA_1C0_1FF 0x0e141295#define RADEON_OV0_GAMMA_200_23F 0x0e181296#define RADEON_OV0_GAMMA_240_27F 0x0e1c1297#define RADEON_OV0_GAMMA_280_2BF 0x0e201298#define RADEON_OV0_GAMMA_2C0_2FF 0x0e241299#define RADEON_OV0_GAMMA_300_33F 0x0e281300#define RADEON_OV0_GAMMA_340_37F 0x0e2c1301#define RADEON_OV0_GAMMA_380_3BF 0x0d501302#define RADEON_OV0_GAMMA_3C0_3FF 0x0d541303#define RADEON_OV0_GRAPHICS_KEY_CLR_LOW 0x04EC1304#define RADEON_OV0_GRAPHICS_KEY_CLR_HIGH 0x04F01305#define RADEON_OV0_H_INC 0x04801306#define RADEON_OV0_KEY_CNTL 0x04F41307# define RADEON_VIDEO_KEY_FN_MASK 0x00000003L1308# define RADEON_VIDEO_KEY_FN_FALSE 0x00000000L1309# define RADEON_VIDEO_KEY_FN_TRUE 0x00000001L1310# define RADEON_VIDEO_KEY_FN_EQ 0x00000002L1311# define RADEON_VIDEO_KEY_FN_NE 0x00000003L1312# define RADEON_GRAPHIC_KEY_FN_MASK 0x00000030L1313# define RADEON_GRAPHIC_KEY_FN_FALSE 0x00000000L1314# define RADEON_GRAPHIC_KEY_FN_TRUE 0x00000010L1315# define RADEON_GRAPHIC_KEY_FN_EQ 0x00000020L1316# define RADEON_GRAPHIC_KEY_FN_NE 0x00000030L1317# define RADEON_CMP_MIX_MASK 0x00000100L1318# define RADEON_CMP_MIX_OR 0x00000000L1319# define RADEON_CMP_MIX_AND 0x00000100L1320#define RADEON_OV0_LIN_TRANS_A 0x0d201321#define RADEON_OV0_LIN_TRANS_B 0x0d241322#define RADEON_OV0_LIN_TRANS_C 0x0d281323#define RADEON_OV0_LIN_TRANS_D 0x0d2c1324#define RADEON_OV0_LIN_TRANS_E 0x0d301325#define RADEON_OV0_LIN_TRANS_F 0x0d341326#define RADEON_OV0_P1_BLANK_LINES_AT_TOP 0x04301327# define RADEON_P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL1328# define RADEON_P1_ACTIVE_LINES_M1 0x0fff0000L1329#define RADEON_OV0_P1_H_ACCUM_INIT 0x04881330#define RADEON_OV0_P1_V_ACCUM_INIT 0x04281331# define RADEON_OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L1332# define RADEON_OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L1333#define RADEON_OV0_P1_X_START_END 0x04941334#define RADEON_OV0_P2_X_START_END 0x04981335#define RADEON_OV0_P23_BLANK_LINES_AT_TOP 0x04341336# define RADEON_P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL1337# define RADEON_P23_ACTIVE_LINES_M1 0x07ff0000L1338#define RADEON_OV0_P23_H_ACCUM_INIT 0x048C1339#define RADEON_OV0_P23_V_ACCUM_INIT 0x042C1340#define RADEON_OV0_P3_X_START_END 0x049C1341#define RADEON_OV0_REG_LOAD_CNTL 0x04101342# define RADEON_REG_LD_CTL_LOCK 0x00000001L1343# define RADEON_REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L1344# define RADEON_REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L1345# define RADEON_REG_LD_CTL_LOCK_READBACK 0x00000008L1346# define RADEON_REG_LD_CTL_FLIP_READBACK 0x00000010L1347#define RADEON_OV0_SCALE_CNTL 0x04201348# define RADEON_SCALER_HORZ_PICK_NEAREST 0x00000004L1349# define RADEON_SCALER_VERT_PICK_NEAREST 0x00000008L1350# define RADEON_SCALER_SIGNED_UV 0x00000010L1351# define RADEON_SCALER_GAMMA_SEL_MASK 0x00000060L1352# define RADEON_SCALER_GAMMA_SEL_BRIGHT 0x00000000L1353# define RADEON_SCALER_GAMMA_SEL_G22 0x00000020L1354# define RADEON_SCALER_GAMMA_SEL_G18 0x00000040L1355# define RADEON_SCALER_GAMMA_SEL_G14 0x00000060L1356# define RADEON_SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L1357# define RADEON_SCALER_SURFAC_FORMAT 0x00000f00L1358# define RADEON_SCALER_SOURCE_15BPP 0x00000300L1359# define RADEON_SCALER_SOURCE_16BPP 0x00000400L1360# define RADEON_SCALER_SOURCE_32BPP 0x00000600L1361# define RADEON_SCALER_SOURCE_YUV9 0x00000900L1362# define RADEON_SCALER_SOURCE_YUV12 0x00000A00L1363# define RADEON_SCALER_SOURCE_VYUY422 0x00000B00L1364# define RADEON_SCALER_SOURCE_YVYU422 0x00000C00L1365# define RADEON_SCALER_ADAPTIVE_DEINT 0x00001000L1366# define RADEON_SCALER_TEMPORAL_DEINT 0x00002000L1367# define RADEON_SCALER_CRTC_SEL 0x00004000L1368# define RADEON_SCALER_SMART_SWITCH 0x00008000L1369# define RADEON_SCALER_BURST_PER_PLANE 0x007F0000L1370# define RADEON_SCALER_DOUBLE_BUFFER 0x01000000L1371# define RADEON_SCALER_DIS_LIMIT 0x08000000L1372# define RADEON_SCALER_LIN_TRANS_BYPASS 0x10000000L1373# define RADEON_SCALER_INT_EMU 0x20000000L1374# define RADEON_SCALER_ENABLE 0x40000000L1375# define RADEON_SCALER_SOFT_RESET 0x80000000L1376#define RADEON_OV0_STEP_BY 0x04841377#define RADEON_OV0_TEST 0x04F81378#define RADEON_OV0_V_INC 0x04241379#define RADEON_OV0_VID_BUF_PITCH0_VALUE 0x04601380#define RADEON_OV0_VID_BUF_PITCH1_VALUE 0x04641381#define RADEON_OV0_VID_BUF0_BASE_ADRS 0x04401382# define RADEON_VIF_BUF0_PITCH_SEL 0x00000001L1383# define RADEON_VIF_BUF0_TILE_ADRS 0x00000002L1384# define RADEON_VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L1385# define RADEON_VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L1386#define RADEON_OV0_VID_BUF1_BASE_ADRS 0x04441387# define RADEON_VIF_BUF1_PITCH_SEL 0x00000001L1388# define RADEON_VIF_BUF1_TILE_ADRS 0x00000002L1389# define RADEON_VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L1390# define RADEON_VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L1391#define RADEON_OV0_VID_BUF2_BASE_ADRS 0x04481392# define RADEON_VIF_BUF2_PITCH_SEL 0x00000001L1393# define RADEON_VIF_BUF2_TILE_ADRS 0x00000002L1394# define RADEON_VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L1395# define RADEON_VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L1396#define RADEON_OV0_VID_BUF3_BASE_ADRS 0x044C1397#define RADEON_OV0_VID_BUF4_BASE_ADRS 0x04501398#define RADEON_OV0_VID_BUF5_BASE_ADRS 0x04541399#define RADEON_OV0_VIDEO_KEY_CLR_HIGH 0x04E81400#define RADEON_OV0_VIDEO_KEY_CLR_LOW 0x04E41401#define RADEON_OV0_Y_X_START 0x04001402#define RADEON_OV0_Y_X_END 0x04041403#define RADEON_OV1_Y_X_START 0x06001404#define RADEON_OV1_Y_X_END 0x06041405#define RADEON_OVR_CLR 0x02301406#define RADEON_OVR_WID_LEFT_RIGHT 0x02341407#define RADEON_OVR_WID_TOP_BOTTOM 0x02381408#define RADEON_OVR2_CLR 0x03301409#define RADEON_OVR2_WID_LEFT_RIGHT 0x03341410#define RADEON_OVR2_WID_TOP_BOTTOM 0x03381411 1412/* first capture unit */1413 1414#define RADEON_CAP0_BUF0_OFFSET 0x09201415#define RADEON_CAP0_BUF1_OFFSET 0x09241416#define RADEON_CAP0_BUF0_EVEN_OFFSET 0x09281417#define RADEON_CAP0_BUF1_EVEN_OFFSET 0x092C1418 1419#define RADEON_CAP0_BUF_PITCH 0x09301420#define RADEON_CAP0_V_WINDOW 0x09341421#define RADEON_CAP0_H_WINDOW 0x09381422#define RADEON_CAP0_VBI0_OFFSET 0x093C1423#define RADEON_CAP0_VBI1_OFFSET 0x09401424#define RADEON_CAP0_VBI_V_WINDOW 0x09441425#define RADEON_CAP0_VBI_H_WINDOW 0x09481426#define RADEON_CAP0_PORT_MODE_CNTL 0x094C1427#define RADEON_CAP0_TRIG_CNTL 0x09501428#define RADEON_CAP0_DEBUG 0x09541429#define RADEON_CAP0_CONFIG 0x09581430# define RADEON_CAP0_CONFIG_CONTINUOS 0x000000011431# define RADEON_CAP0_CONFIG_START_FIELD_EVEN 0x000000021432# define RADEON_CAP0_CONFIG_START_BUF_GET 0x000000041433# define RADEON_CAP0_CONFIG_START_BUF_SET 0x000000081434# define RADEON_CAP0_CONFIG_BUF_TYPE_ALT 0x000000101435# define RADEON_CAP0_CONFIG_BUF_TYPE_FRAME 0x000000201436# define RADEON_CAP0_CONFIG_ONESHOT_MODE_FRAME 0x000000401437# define RADEON_CAP0_CONFIG_BUF_MODE_DOUBLE 0x000000801438# define RADEON_CAP0_CONFIG_BUF_MODE_TRIPLE 0x000001001439# define RADEON_CAP0_CONFIG_MIRROR_EN 0x000002001440# define RADEON_CAP0_CONFIG_ONESHOT_MIRROR_EN 0x000004001441# define RADEON_CAP0_CONFIG_VIDEO_SIGNED_UV 0x000008001442# define RADEON_CAP0_CONFIG_ANC_DECODE_EN 0x000010001443# define RADEON_CAP0_CONFIG_VBI_EN 0x000020001444# define RADEON_CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x000040001445# define RADEON_CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x000080001446# define RADEON_CAP0_CONFIG_FAKE_FIELD_EN 0x000100001447# define RADEON_CAP0_CONFIG_ODD_ONE_MORE_LINE 0x000200001448# define RADEON_CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x000400001449# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_2 0x000800001450# define RADEON_CAP0_CONFIG_HORZ_DIVIDE_4 0x001000001451# define RADEON_CAP0_CONFIG_VERT_DIVIDE_2 0x002000001452# define RADEON_CAP0_CONFIG_VERT_DIVIDE_4 0x004000001453# define RADEON_CAP0_CONFIG_FORMAT_BROOKTREE 0x000000001454# define RADEON_CAP0_CONFIG_FORMAT_CCIR656 0x008000001455# define RADEON_CAP0_CONFIG_FORMAT_ZV 0x010000001456# define RADEON_CAP0_CONFIG_FORMAT_VIP 0x018000001457# define RADEON_CAP0_CONFIG_FORMAT_TRANSPORT 0x020000001458# define RADEON_CAP0_CONFIG_HORZ_DECIMATOR 0x040000001459# define RADEON_CAP0_CONFIG_VIDEO_IN_YVYU422 0x000000001460# define RADEON_CAP0_CONFIG_VIDEO_IN_VYUY422 0x200000001461# define RADEON_CAP0_CONFIG_VBI_DIVIDE_2 0x400000001462# define RADEON_CAP0_CONFIG_VBI_DIVIDE_4 0x800000001463#define RADEON_CAP0_ANC_ODD_OFFSET 0x095C1464#define RADEON_CAP0_ANC_EVEN_OFFSET 0x09601465#define RADEON_CAP0_ANC_H_WINDOW 0x09641466#define RADEON_CAP0_VIDEO_SYNC_TEST 0x09681467#define RADEON_CAP0_ONESHOT_BUF_OFFSET 0x096C1468#define RADEON_CAP0_BUF_STATUS 0x09701469/* #define RADEON_CAP0_DWNSC_XRATIO 0x0978 */1470/* #define RADEON_CAP0_XSHARPNESS 0x097C */1471#define RADEON_CAP0_VBI2_OFFSET 0x09801472#define RADEON_CAP0_VBI3_OFFSET 0x09841473#define RADEON_CAP0_ANC2_OFFSET 0x09881474#define RADEON_CAP0_ANC3_OFFSET 0x098C1475#define RADEON_VID_BUFFER_CONTROL 0x09001476 1477/* second capture unit */1478 1479#define RADEON_CAP1_BUF0_OFFSET 0x09901480#define RADEON_CAP1_BUF1_OFFSET 0x09941481#define RADEON_CAP1_BUF0_EVEN_OFFSET 0x09981482#define RADEON_CAP1_BUF1_EVEN_OFFSET 0x099C1483 1484#define RADEON_CAP1_BUF_PITCH 0x09A01485#define RADEON_CAP1_V_WINDOW 0x09A41486#define RADEON_CAP1_H_WINDOW 0x09A81487#define RADEON_CAP1_VBI_ODD_OFFSET 0x09AC1488#define RADEON_CAP1_VBI_EVEN_OFFSET 0x09B01489#define RADEON_CAP1_VBI_V_WINDOW 0x09B41490#define RADEON_CAP1_VBI_H_WINDOW 0x09B81491#define RADEON_CAP1_PORT_MODE_CNTL 0x09BC1492#define RADEON_CAP1_TRIG_CNTL 0x09C01493#define RADEON_CAP1_DEBUG 0x09C41494#define RADEON_CAP1_CONFIG 0x09C81495#define RADEON_CAP1_ANC_ODD_OFFSET 0x09CC1496#define RADEON_CAP1_ANC_EVEN_OFFSET 0x09D01497#define RADEON_CAP1_ANC_H_WINDOW 0x09D41498#define RADEON_CAP1_VIDEO_SYNC_TEST 0x09D81499#define RADEON_CAP1_ONESHOT_BUF_OFFSET 0x09DC1500#define RADEON_CAP1_BUF_STATUS 0x09E01501#define RADEON_CAP1_DWNSC_XRATIO 0x09E81502#define RADEON_CAP1_XSHARPNESS 0x09EC1503 1504/* misc multimedia registers */1505 1506#define RADEON_IDCT_RUNS 0x1F801507#define RADEON_IDCT_LEVELS 0x1F841508#define RADEON_IDCT_CONTROL 0x1FBC1509#define RADEON_IDCT_AUTH_CONTROL 0x1F881510#define RADEON_IDCT_AUTH 0x1F8C1511 1512#define RADEON_P2PLL_CNTL 0x002a /* P2PLL */1513# define RADEON_P2PLL_RESET (1 << 0)1514# define RADEON_P2PLL_SLEEP (1 << 1)1515# define RADEON_P2PLL_PVG_MASK (7 << 11)1516# define RADEON_P2PLL_PVG_SHIFT 111517# define RADEON_P2PLL_ATOMIC_UPDATE_EN (1 << 16)1518# define RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17)1519# define RADEON_P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18)1520#define RADEON_P2PLL_DIV_0 0x002c1521# define RADEON_P2PLL_FB0_DIV_MASK 0x07ff1522# define RADEON_P2PLL_POST0_DIV_MASK 0x000700001523#define RADEON_P2PLL_REF_DIV 0x002B /* PLL */1524# define RADEON_P2PLL_REF_DIV_MASK 0x03ff1525# define RADEON_P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */1526# define RADEON_P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */1527# define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18)1528# define R300_PPLL_REF_DIV_ACC_SHIFT 181529#define RADEON_PALETTE_DATA 0x00b41530#define RADEON_PALETTE_30_DATA 0x00b81531#define RADEON_PALETTE_INDEX 0x00b01532#define RADEON_PCI_GART_PAGE 0x017c1533#define RADEON_PIXCLKS_CNTL 0x002d1534# define RADEON_PIX2CLK_SRC_SEL_MASK 0x031535# define RADEON_PIX2CLK_SRC_SEL_CPUCLK 0x001536# define RADEON_PIX2CLK_SRC_SEL_PSCANCLK 0x011537# define RADEON_PIX2CLK_SRC_SEL_BYTECLK 0x021538# define RADEON_PIX2CLK_SRC_SEL_P2PLLCLK 0x031539# define RADEON_PIX2CLK_ALWAYS_ONb (1<<6)1540# define RADEON_PIX2CLK_DAC_ALWAYS_ONb (1<<7)1541# define RADEON_PIXCLK_TV_SRC_SEL (1 << 8)1542# define RADEON_DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9)1543# define R300_DVOCLK_ALWAYS_ONb (1 << 10)1544# define RADEON_PIXCLK_BLEND_ALWAYS_ONb (1 << 11)1545# define RADEON_PIXCLK_GV_ALWAYS_ONb (1 << 12)1546# define RADEON_PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13)1547# define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13)1548# define RADEON_PIXCLK_LVDS_ALWAYS_ONb (1 << 14)1549# define RADEON_PIXCLK_TMDS_ALWAYS_ONb (1 << 15)1550# define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16)1551# define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17)1552# define R300_P2G2CLK_ALWAYS_ONb (1 << 18)1553# define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19)1554# define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23)1555#define RADEON_PLANE_3D_MASK_C 0x1d441556#define RADEON_PLL_TEST_CNTL 0x0013 /* PLL */1557# define RADEON_PLL_MASK_READ_B (1 << 9)1558#define RADEON_PMI_CAP_ID 0x0f5c /* PCI */1559#define RADEON_PMI_DATA 0x0f63 /* PCI */1560#define RADEON_PMI_NXT_CAP_PTR 0x0f5d /* PCI */1561#define RADEON_PMI_PMC_REG 0x0f5e /* PCI */1562#define RADEON_PMI_PMCSR_REG 0x0f60 /* PCI */1563#define RADEON_PMI_REGISTER 0x0f5c /* PCI */1564#define RADEON_PPLL_CNTL 0x0002 /* PLL */1565# define RADEON_PPLL_RESET (1 << 0)1566# define RADEON_PPLL_SLEEP (1 << 1)1567# define RADEON_PPLL_PVG_MASK (7 << 11)1568# define RADEON_PPLL_PVG_SHIFT 111569# define RADEON_PPLL_ATOMIC_UPDATE_EN (1 << 16)1570# define RADEON_PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17)1571# define RADEON_PPLL_ATOMIC_UPDATE_VSYNC (1 << 18)1572#define RADEON_PPLL_DIV_0 0x0004 /* PLL */1573#define RADEON_PPLL_DIV_1 0x0005 /* PLL */1574#define RADEON_PPLL_DIV_2 0x0006 /* PLL */1575#define RADEON_PPLL_DIV_3 0x0007 /* PLL */1576# define RADEON_PPLL_FB3_DIV_MASK 0x07ff1577# define RADEON_PPLL_POST3_DIV_MASK 0x000700001578#define RADEON_PPLL_REF_DIV 0x0003 /* PLL */1579# define RADEON_PPLL_REF_DIV_MASK 0x03ff1580# define RADEON_PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */1581# define RADEON_PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */1582#define RADEON_PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */1583 1584#define RADEON_RBBM_GUICNTL 0x172c1585# define RADEON_HOST_DATA_SWAP_NONE (0 << 0)1586# define RADEON_HOST_DATA_SWAP_16BIT (1 << 0)1587# define RADEON_HOST_DATA_SWAP_32BIT (2 << 0)1588# define RADEON_HOST_DATA_SWAP_HDW (3 << 0)1589#define RADEON_RBBM_SOFT_RESET 0x00f01590# define RADEON_SOFT_RESET_CP (1 << 0)1591# define RADEON_SOFT_RESET_HI (1 << 1)1592# define RADEON_SOFT_RESET_SE (1 << 2)1593# define RADEON_SOFT_RESET_RE (1 << 3)1594# define RADEON_SOFT_RESET_PP (1 << 4)1595# define RADEON_SOFT_RESET_E2 (1 << 5)1596# define RADEON_SOFT_RESET_RB (1 << 6)1597# define RADEON_SOFT_RESET_HDP (1 << 7)1598#define RADEON_RBBM_STATUS 0x0e401599# define RADEON_RBBM_FIFOCNT_MASK 0x007f1600# define RADEON_RBBM_ACTIVE (1 << 31)1601#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c1602# define RADEON_RB2D_DC_FLUSH (3 << 0)1603# define RADEON_RB2D_DC_FREE (3 << 2)1604# define RADEON_RB2D_DC_FLUSH_ALL 0xf1605# define RADEON_RB2D_DC_BUSY (1 << 31)1606#define RADEON_RB2D_DSTCACHE_MODE 0x34281607#define RADEON_DSTCACHE_CTLSTAT 0x17141608 1609#define RADEON_RB3D_ZCACHE_MODE 0x32501610#define RADEON_RB3D_ZCACHE_CTLSTAT 0x32541611# define RADEON_RB3D_ZC_FLUSH_ALL 0x51612#define RADEON_RB3D_DSTCACHE_MODE 0x32581613# define RADEON_RB3D_DC_CACHE_ENABLE (0)1614# define RADEON_RB3D_DC_2D_CACHE_DISABLE (1)1615# define RADEON_RB3D_DC_3D_CACHE_DISABLE (2)1616# define RADEON_RB3D_DC_CACHE_DISABLE (3)1617# define RADEON_RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2)1618# define RADEON_RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2)1619# define RADEON_RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8)1620# define RADEON_RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8)1621# define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10)1622# define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10)1623# define RADEON_RB3D_DC_FORCE_RMW (1 << 16)1624# define RADEON_RB3D_DC_DISABLE_RI_FILL (1 << 24)1625# define RADEON_RB3D_DC_DISABLE_RI_READ (1 << 25)1626 1627#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325C1628# define RADEON_RB3D_DC_FLUSH (3 << 0)1629# define RADEON_RB3D_DC_FREE (3 << 2)1630# define RADEON_RB3D_DC_FLUSH_ALL 0xf1631# define RADEON_RB3D_DC_BUSY (1 << 31)1632 1633#define RADEON_REG_BASE 0x0f18 /* PCI */1634#define RADEON_REGPROG_INF 0x0f09 /* PCI */1635#define RADEON_REVISION_ID 0x0f08 /* PCI */1636 1637#define RADEON_SC_BOTTOM 0x164c1638#define RADEON_SC_BOTTOM_RIGHT 0x16f01639#define RADEON_SC_BOTTOM_RIGHT_C 0x1c8c1640#define RADEON_SC_LEFT 0x16401641#define RADEON_SC_RIGHT 0x16441642#define RADEON_SC_TOP 0x16481643#define RADEON_SC_TOP_LEFT 0x16ec1644#define RADEON_SC_TOP_LEFT_C 0x1c881645# define RADEON_SC_SIGN_MASK_LO 0x80001646# define RADEON_SC_SIGN_MASK_HI 0x800000001647#define RADEON_M_SPLL_REF_FB_DIV 0x000a /* PLL */1648# define RADEON_M_SPLL_REF_DIV_SHIFT 01649# define RADEON_M_SPLL_REF_DIV_MASK 0xff1650# define RADEON_MPLL_FB_DIV_SHIFT 81651# define RADEON_MPLL_FB_DIV_MASK 0xff1652# define RADEON_SPLL_FB_DIV_SHIFT 161653# define RADEON_SPLL_FB_DIV_MASK 0xff1654#define RADEON_SPLL_CNTL 0x000c /* PLL */1655# define RADEON_SPLL_SLEEP (1 << 0)1656# define RADEON_SPLL_RESET (1 << 1)1657# define RADEON_SPLL_PCP_MASK 0x71658# define RADEON_SPLL_PCP_SHIFT 81659# define RADEON_SPLL_PVG_MASK 0x71660# define RADEON_SPLL_PVG_SHIFT 111661# define RADEON_SPLL_PDC_MASK 0x31662# define RADEON_SPLL_PDC_SHIFT 141663#define RADEON_SCLK_CNTL 0x000d /* PLL */1664# define RADEON_SCLK_SRC_SEL_MASK 0x00071665# define RADEON_DYN_STOP_LAT_MASK 0x00007ff81666# define RADEON_CP_MAX_DYN_STOP_LAT 0x00081667# define RADEON_SCLK_FORCEON_MASK 0xffff80001668# define RADEON_SCLK_FORCE_DISP2 (1<<15)1669# define RADEON_SCLK_FORCE_CP (1<<16)1670# define RADEON_SCLK_FORCE_HDP (1<<17)1671# define RADEON_SCLK_FORCE_DISP1 (1<<18)1672# define RADEON_SCLK_FORCE_TOP (1<<19)1673# define RADEON_SCLK_FORCE_E2 (1<<20)1674# define RADEON_SCLK_FORCE_SE (1<<21)1675# define RADEON_SCLK_FORCE_IDCT (1<<22)1676# define RADEON_SCLK_FORCE_VIP (1<<23)1677# define RADEON_SCLK_FORCE_RE (1<<24)1678# define RADEON_SCLK_FORCE_PB (1<<25)1679# define RADEON_SCLK_FORCE_TAM (1<<26)1680# define RADEON_SCLK_FORCE_TDM (1<<27)1681# define RADEON_SCLK_FORCE_RB (1<<28)1682# define RADEON_SCLK_FORCE_TV_SCLK (1<<29)1683# define RADEON_SCLK_FORCE_SUBPIC (1<<30)1684# define RADEON_SCLK_FORCE_OV0 (1<<31)1685# define R300_SCLK_FORCE_VAP (1<<21)1686# define R300_SCLK_FORCE_SR (1<<25)1687# define R300_SCLK_FORCE_PX (1<<26)1688# define R300_SCLK_FORCE_TX (1<<27)1689# define R300_SCLK_FORCE_US (1<<28)1690# define R300_SCLK_FORCE_SU (1<<30)1691#define R300_SCLK_CNTL2 0x1e /* PLL */1692# define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10)1693# define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11)1694# define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12)1695# define R300_SCLK_FORCE_TCL (1<<13)1696# define R300_SCLK_FORCE_CBA (1<<14)1697# define R300_SCLK_FORCE_GA (1<<15)1698#define RADEON_SCLK_MORE_CNTL 0x0035 /* PLL */1699# define RADEON_SCLK_MORE_MAX_DYN_STOP_LAT 0x00071700# define RADEON_SCLK_MORE_FORCEON 0x07001701#define RADEON_SDRAM_MODE_REG 0x01581702#define RADEON_SEQ8_DATA 0x03c5 /* VGA */1703#define RADEON_SEQ8_IDX 0x03c4 /* VGA */1704#define RADEON_SNAPSHOT_F_COUNT 0x02441705#define RADEON_SNAPSHOT_VH_COUNTS 0x02401706#define RADEON_SNAPSHOT_VIF_COUNT 0x024c1707#define RADEON_SRC_OFFSET 0x15ac1708#define RADEON_SRC_PITCH 0x15b01709#define RADEON_SRC_PITCH_OFFSET 0x14281710#define RADEON_SRC_SC_BOTTOM 0x165c1711#define RADEON_SRC_SC_BOTTOM_RIGHT 0x16f41712#define RADEON_SRC_SC_RIGHT 0x16541713#define RADEON_SRC_X 0x14141714#define RADEON_SRC_X_Y 0x15901715#define RADEON_SRC_Y 0x14181716#define RADEON_SRC_Y_X 0x14341717#define RADEON_STATUS 0x0f06 /* PCI */1718#define RADEON_SUBPIC_CNTL 0x0540 /* ? */1719#define RADEON_SUB_CLASS 0x0f0a /* PCI */1720#define RADEON_SURFACE_CNTL 0x0b001721# define RADEON_SURF_TRANSLATION_DIS (1 << 8)1722# define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20)1723# define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21)1724# define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22)1725# define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23)1726#define RADEON_SURFACE0_INFO 0x0b0c1727# define RADEON_SURF_TILE_COLOR_MACRO (0 << 16)1728# define RADEON_SURF_TILE_COLOR_BOTH (1 << 16)1729# define RADEON_SURF_TILE_DEPTH_32BPP (2 << 16)1730# define RADEON_SURF_TILE_DEPTH_16BPP (3 << 16)1731# define R200_SURF_TILE_NONE (0 << 16)1732# define R200_SURF_TILE_COLOR_MACRO (1 << 16)1733# define R200_SURF_TILE_COLOR_MICRO (2 << 16)1734# define R200_SURF_TILE_COLOR_BOTH (3 << 16)1735# define R200_SURF_TILE_DEPTH_32BPP (4 << 16)1736# define R200_SURF_TILE_DEPTH_16BPP (5 << 16)1737# define R300_SURF_TILE_NONE (0 << 16)1738# define R300_SURF_TILE_COLOR_MACRO (1 << 16)1739# define R300_SURF_TILE_DEPTH_32BPP (2 << 16)1740# define RADEON_SURF_AP0_SWP_16BPP (1 << 20)1741# define RADEON_SURF_AP0_SWP_32BPP (1 << 21)1742# define RADEON_SURF_AP1_SWP_16BPP (1 << 22)1743# define RADEON_SURF_AP1_SWP_32BPP (1 << 23)1744#define RADEON_SURFACE0_LOWER_BOUND 0x0b041745#define RADEON_SURFACE0_UPPER_BOUND 0x0b081746#define RADEON_SURFACE1_INFO 0x0b1c1747#define RADEON_SURFACE1_LOWER_BOUND 0x0b141748#define RADEON_SURFACE1_UPPER_BOUND 0x0b181749#define RADEON_SURFACE2_INFO 0x0b2c1750#define RADEON_SURFACE2_LOWER_BOUND 0x0b241751#define RADEON_SURFACE2_UPPER_BOUND 0x0b281752#define RADEON_SURFACE3_INFO 0x0b3c1753#define RADEON_SURFACE3_LOWER_BOUND 0x0b341754#define RADEON_SURFACE3_UPPER_BOUND 0x0b381755#define RADEON_SURFACE4_INFO 0x0b4c1756#define RADEON_SURFACE4_LOWER_BOUND 0x0b441757#define RADEON_SURFACE4_UPPER_BOUND 0x0b481758#define RADEON_SURFACE5_INFO 0x0b5c1759#define RADEON_SURFACE5_LOWER_BOUND 0x0b541760#define RADEON_SURFACE5_UPPER_BOUND 0x0b581761#define RADEON_SURFACE6_INFO 0x0b6c1762#define RADEON_SURFACE6_LOWER_BOUND 0x0b641763#define RADEON_SURFACE6_UPPER_BOUND 0x0b681764#define RADEON_SURFACE7_INFO 0x0b7c1765#define RADEON_SURFACE7_LOWER_BOUND 0x0b741766#define RADEON_SURFACE7_UPPER_BOUND 0x0b781767#define RADEON_SW_SEMAPHORE 0x013c1768 1769#define RADEON_TEST_DEBUG_CNTL 0x01201770#define RADEON_TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x000000011771 1772#define RADEON_TEST_DEBUG_MUX 0x01241773#define RADEON_TEST_DEBUG_OUT 0x012c1774#define RADEON_TMDS_PLL_CNTL 0x02a81775#define RADEON_TMDS_TRANSMITTER_CNTL 0x02a41776# define RADEON_TMDS_TRANSMITTER_PLLEN 11777# define RADEON_TMDS_TRANSMITTER_PLLRST 21778#define RADEON_TRAIL_BRES_DEC 0x16141779#define RADEON_TRAIL_BRES_ERR 0x160c1780#define RADEON_TRAIL_BRES_INC 0x16101781#define RADEON_TRAIL_X 0x16181782#define RADEON_TRAIL_X_SUB 0x16201783 1784#define RADEON_VCLK_ECP_CNTL 0x0008 /* PLL */1785# define RADEON_VCLK_SRC_SEL_MASK 0x031786# define RADEON_VCLK_SRC_SEL_CPUCLK 0x001787# define RADEON_VCLK_SRC_SEL_PSCANCLK 0x011788# define RADEON_VCLK_SRC_SEL_BYTECLK 0x021789# define RADEON_VCLK_SRC_SEL_PPLLCLK 0x031790# define RADEON_PIXCLK_ALWAYS_ONb (1<<6)1791# define RADEON_PIXCLK_DAC_ALWAYS_ONb (1<<7)1792# define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23)1793 1794#define RADEON_VENDOR_ID 0x0f00 /* PCI */1795#define RADEON_VGA_DDA_CONFIG 0x02e81796#define RADEON_VGA_DDA_ON_OFF 0x02ec1797#define RADEON_VID_BUFFER_CONTROL 0x09001798#define RADEON_VIDEOMUX_CNTL 0x01901799 1800/* VIP bus */1801#define RADEON_VIPH_CH0_DATA 0x0c001802#define RADEON_VIPH_CH1_DATA 0x0c041803#define RADEON_VIPH_CH2_DATA 0x0c081804#define RADEON_VIPH_CH3_DATA 0x0c0c1805#define RADEON_VIPH_CH0_ADDR 0x0c101806#define RADEON_VIPH_CH1_ADDR 0x0c141807#define RADEON_VIPH_CH2_ADDR 0x0c181808#define RADEON_VIPH_CH3_ADDR 0x0c1c1809#define RADEON_VIPH_CH0_SBCNT 0x0c201810#define RADEON_VIPH_CH1_SBCNT 0x0c241811#define RADEON_VIPH_CH2_SBCNT 0x0c281812#define RADEON_VIPH_CH3_SBCNT 0x0c2c1813#define RADEON_VIPH_CH0_ABCNT 0x0c301814#define RADEON_VIPH_CH1_ABCNT 0x0c341815#define RADEON_VIPH_CH2_ABCNT 0x0c381816#define RADEON_VIPH_CH3_ABCNT 0x0c3c1817#define RADEON_VIPH_CONTROL 0x0c401818# define RADEON_VIP_BUSY 01819# define RADEON_VIP_IDLE 11820# define RADEON_VIP_RESET 21821# define RADEON_VIPH_EN (1 << 21)1822#define RADEON_VIPH_DV_LAT 0x0c441823#define RADEON_VIPH_BM_CHUNK 0x0c481824#define RADEON_VIPH_DV_INT 0x0c4c1825#define RADEON_VIPH_TIMEOUT_STAT 0x0c501826#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x000000101827#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x000000101828#define RADEON_VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x010000001829 1830#define RADEON_VIPH_REG_DATA 0x00841831#define RADEON_VIPH_REG_ADDR 0x00801832 1833 1834#define RADEON_WAIT_UNTIL 0x17201835# define RADEON_WAIT_CRTC_PFLIP (1 << 0)1836# define RADEON_WAIT_RE_CRTC_VLINE (1 << 1)1837# define RADEON_WAIT_FE_CRTC_VLINE (1 << 2)1838# define RADEON_WAIT_CRTC_VLINE (1 << 3)1839# define RADEON_WAIT_DMA_VID_IDLE (1 << 8)1840# define RADEON_WAIT_DMA_GUI_IDLE (1 << 9)1841# define RADEON_WAIT_CMDFIFO (1 << 10) /* wait for CMDFIFO_ENTRIES */1842# define RADEON_WAIT_OV0_FLIP (1 << 11)1843# define RADEON_WAIT_AGP_FLUSH (1 << 13)1844# define RADEON_WAIT_2D_IDLE (1 << 14)1845# define RADEON_WAIT_3D_IDLE (1 << 15)1846# define RADEON_WAIT_2D_IDLECLEAN (1 << 16)1847# define RADEON_WAIT_3D_IDLECLEAN (1 << 17)1848# define RADEON_WAIT_HOST_IDLECLEAN (1 << 18)1849# define RADEON_CMDFIFO_ENTRIES_SHIFT 101850# define RADEON_CMDFIFO_ENTRIES_MASK 0x7f1851# define RADEON_WAIT_VAP_IDLE (1 << 28)1852# define RADEON_WAIT_BOTH_CRTC_PFLIP (1 << 30)1853# define RADEON_ENG_DISPLAY_SELECT_CRTC0 (0 << 31)1854# define RADEON_ENG_DISPLAY_SELECT_CRTC1 (1 << 31)1855 1856#define RADEON_X_MPLL_REF_FB_DIV 0x000a /* PLL */1857#define RADEON_XCLK_CNTL 0x000d /* PLL */1858#define RADEON_XDLL_CNTL 0x000c /* PLL */1859#define RADEON_XPLL_CNTL 0x000b /* PLL */1860 1861 1862 1863 /* Registers for 3D/TCL */1864#define RADEON_PP_BORDER_COLOR_0 0x1d401865#define RADEON_PP_BORDER_COLOR_1 0x1d441866#define RADEON_PP_BORDER_COLOR_2 0x1d481867#define RADEON_PP_CNTL 0x1c381868# define RADEON_STIPPLE_ENABLE (1 << 0)1869# define RADEON_SCISSOR_ENABLE (1 << 1)1870# define RADEON_PATTERN_ENABLE (1 << 2)1871# define RADEON_SHADOW_ENABLE (1 << 3)1872# define RADEON_TEX_ENABLE_MASK (0xf << 4)1873# define RADEON_TEX_0_ENABLE (1 << 4)1874# define RADEON_TEX_1_ENABLE (1 << 5)1875# define RADEON_TEX_2_ENABLE (1 << 6)1876# define RADEON_TEX_3_ENABLE (1 << 7)1877# define RADEON_TEX_BLEND_ENABLE_MASK (0xf << 12)1878# define RADEON_TEX_BLEND_0_ENABLE (1 << 12)1879# define RADEON_TEX_BLEND_1_ENABLE (1 << 13)1880# define RADEON_TEX_BLEND_2_ENABLE (1 << 14)1881# define RADEON_TEX_BLEND_3_ENABLE (1 << 15)1882# define RADEON_PLANAR_YUV_ENABLE (1 << 20)1883# define RADEON_SPECULAR_ENABLE (1 << 21)1884# define RADEON_FOG_ENABLE (1 << 22)1885# define RADEON_ALPHA_TEST_ENABLE (1 << 23)1886# define RADEON_ANTI_ALIAS_NONE (0 << 24)1887# define RADEON_ANTI_ALIAS_LINE (1 << 24)1888# define RADEON_ANTI_ALIAS_POLY (2 << 24)1889# define RADEON_ANTI_ALIAS_LINE_POLY (3 << 24)1890# define RADEON_BUMP_MAP_ENABLE (1 << 26)1891# define RADEON_BUMPED_MAP_T0 (0 << 27)1892# define RADEON_BUMPED_MAP_T1 (1 << 27)1893# define RADEON_BUMPED_MAP_T2 (2 << 27)1894# define RADEON_TEX_3D_ENABLE_0 (1 << 29)1895# define RADEON_TEX_3D_ENABLE_1 (1 << 30)1896# define RADEON_MC_ENABLE (1 << 31)1897#define RADEON_PP_FOG_COLOR 0x1c181898# define RADEON_FOG_COLOR_MASK 0x00ffffff1899# define RADEON_FOG_VERTEX (0 << 24)1900# define RADEON_FOG_TABLE (1 << 24)1901# define RADEON_FOG_USE_DEPTH (0 << 25)1902# define RADEON_FOG_USE_DIFFUSE_ALPHA (2 << 25)1903# define RADEON_FOG_USE_SPEC_ALPHA (3 << 25)1904#define RADEON_PP_LUM_MATRIX 0x1d001905#define RADEON_PP_MISC 0x1c141906# define RADEON_REF_ALPHA_MASK 0x000000ff1907# define RADEON_ALPHA_TEST_FAIL (0 << 8)1908# define RADEON_ALPHA_TEST_LESS (1 << 8)1909# define RADEON_ALPHA_TEST_LEQUAL (2 << 8)1910# define RADEON_ALPHA_TEST_EQUAL (3 << 8)1911# define RADEON_ALPHA_TEST_GEQUAL (4 << 8)1912# define RADEON_ALPHA_TEST_GREATER (5 << 8)1913# define RADEON_ALPHA_TEST_NEQUAL (6 << 8)1914# define RADEON_ALPHA_TEST_PASS (7 << 8)1915# define RADEON_ALPHA_TEST_OP_MASK (7 << 8)1916# define RADEON_CHROMA_FUNC_FAIL (0 << 16)1917# define RADEON_CHROMA_FUNC_PASS (1 << 16)1918# define RADEON_CHROMA_FUNC_NEQUAL (2 << 16)1919# define RADEON_CHROMA_FUNC_EQUAL (3 << 16)1920# define RADEON_CHROMA_KEY_NEAREST (0 << 18)1921# define RADEON_CHROMA_KEY_ZERO (1 << 18)1922# define RADEON_SHADOW_ID_AUTO_INC (1 << 20)1923# define RADEON_SHADOW_FUNC_EQUAL (0 << 21)1924# define RADEON_SHADOW_FUNC_NEQUAL (1 << 21)1925# define RADEON_SHADOW_PASS_1 (0 << 22)1926# define RADEON_SHADOW_PASS_2 (1 << 22)1927# define RADEON_RIGHT_HAND_CUBE_D3D (0 << 24)1928# define RADEON_RIGHT_HAND_CUBE_OGL (1 << 24)1929#define RADEON_PP_ROT_MATRIX_0 0x1d581930#define RADEON_PP_ROT_MATRIX_1 0x1d5c1931#define RADEON_PP_TXFILTER_0 0x1c541932#define RADEON_PP_TXFILTER_1 0x1c6c1933#define RADEON_PP_TXFILTER_2 0x1c841934# define RADEON_MAG_FILTER_NEAREST (0 << 0)1935# define RADEON_MAG_FILTER_LINEAR (1 << 0)1936# define RADEON_MAG_FILTER_MASK (1 << 0)1937# define RADEON_MIN_FILTER_NEAREST (0 << 1)1938# define RADEON_MIN_FILTER_LINEAR (1 << 1)1939# define RADEON_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)1940# define RADEON_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)1941# define RADEON_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)1942# define RADEON_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)1943# define RADEON_MIN_FILTER_ANISO_NEAREST (8 << 1)1944# define RADEON_MIN_FILTER_ANISO_LINEAR (9 << 1)1945# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)1946# define RADEON_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)1947# define RADEON_MIN_FILTER_MASK (15 << 1)1948# define RADEON_MAX_ANISO_1_TO_1 (0 << 5)1949# define RADEON_MAX_ANISO_2_TO_1 (1 << 5)1950# define RADEON_MAX_ANISO_4_TO_1 (2 << 5)1951# define RADEON_MAX_ANISO_8_TO_1 (3 << 5)1952# define RADEON_MAX_ANISO_16_TO_1 (4 << 5)1953# define RADEON_MAX_ANISO_MASK (7 << 5)1954# define RADEON_LOD_BIAS_MASK (0xff << 8)1955# define RADEON_LOD_BIAS_SHIFT 81956# define RADEON_MAX_MIP_LEVEL_MASK (0x0f << 16)1957# define RADEON_MAX_MIP_LEVEL_SHIFT 161958# define RADEON_YUV_TO_RGB (1 << 20)1959# define RADEON_YUV_TEMPERATURE_COOL (0 << 21)1960# define RADEON_YUV_TEMPERATURE_HOT (1 << 21)1961# define RADEON_YUV_TEMPERATURE_MASK (1 << 21)1962# define RADEON_WRAPEN_S (1 << 22)1963# define RADEON_CLAMP_S_WRAP (0 << 23)1964# define RADEON_CLAMP_S_MIRROR (1 << 23)1965# define RADEON_CLAMP_S_CLAMP_LAST (2 << 23)1966# define RADEON_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23)1967# define RADEON_CLAMP_S_CLAMP_BORDER (4 << 23)1968# define RADEON_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23)1969# define RADEON_CLAMP_S_CLAMP_GL (6 << 23)1970# define RADEON_CLAMP_S_MIRROR_CLAMP_GL (7 << 23)1971# define RADEON_CLAMP_S_MASK (7 << 23)1972# define RADEON_WRAPEN_T (1 << 26)1973# define RADEON_CLAMP_T_WRAP (0 << 27)1974# define RADEON_CLAMP_T_MIRROR (1 << 27)1975# define RADEON_CLAMP_T_CLAMP_LAST (2 << 27)1976# define RADEON_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27)1977# define RADEON_CLAMP_T_CLAMP_BORDER (4 << 27)1978# define RADEON_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27)1979# define RADEON_CLAMP_T_CLAMP_GL (6 << 27)1980# define RADEON_CLAMP_T_MIRROR_CLAMP_GL (7 << 27)1981# define RADEON_CLAMP_T_MASK (7 << 27)1982# define RADEON_BORDER_MODE_OGL (0 << 31)1983# define RADEON_BORDER_MODE_D3D (1 << 31)1984#define RADEON_PP_TXFORMAT_0 0x1c581985#define RADEON_PP_TXFORMAT_1 0x1c701986#define RADEON_PP_TXFORMAT_2 0x1c881987# define RADEON_TXFORMAT_I8 (0 << 0)1988# define RADEON_TXFORMAT_AI88 (1 << 0)1989# define RADEON_TXFORMAT_RGB332 (2 << 0)1990# define RADEON_TXFORMAT_ARGB1555 (3 << 0)1991# define RADEON_TXFORMAT_RGB565 (4 << 0)1992# define RADEON_TXFORMAT_ARGB4444 (5 << 0)1993# define RADEON_TXFORMAT_ARGB8888 (6 << 0)1994# define RADEON_TXFORMAT_RGBA8888 (7 << 0)1995# define RADEON_TXFORMAT_Y8 (8 << 0)1996# define RADEON_TXFORMAT_VYUY422 (10 << 0)1997# define RADEON_TXFORMAT_YVYU422 (11 << 0)1998# define RADEON_TXFORMAT_DXT1 (12 << 0)1999# define RADEON_TXFORMAT_DXT23 (14 << 0)2000# define RADEON_TXFORMAT_DXT45 (15 << 0)2001# define RADEON_TXFORMAT_SHADOW16 (16 << 0)2002# define RADEON_TXFORMAT_SHADOW32 (17 << 0)2003# define RADEON_TXFORMAT_DUDV88 (18 << 0)2004# define RADEON_TXFORMAT_LDUDV655 (19 << 0)2005# define RADEON_TXFORMAT_LDUDUV8888 (20 << 0)2006# define RADEON_TXFORMAT_FORMAT_MASK (31 << 0)2007# define RADEON_TXFORMAT_FORMAT_SHIFT 02008# define RADEON_TXFORMAT_APPLE_YUV_MODE (1 << 5)2009# define RADEON_TXFORMAT_ALPHA_IN_MAP (1 << 6)2010# define RADEON_TXFORMAT_NON_POWER2 (1 << 7)2011# define RADEON_TXFORMAT_WIDTH_MASK (15 << 8)2012# define RADEON_TXFORMAT_WIDTH_SHIFT 82013# define RADEON_TXFORMAT_HEIGHT_MASK (15 << 12)2014# define RADEON_TXFORMAT_HEIGHT_SHIFT 122015# define RADEON_TXFORMAT_F5_WIDTH_MASK (15 << 16)2016# define RADEON_TXFORMAT_F5_WIDTH_SHIFT 162017# define RADEON_TXFORMAT_F5_HEIGHT_MASK (15 << 20)2018# define RADEON_TXFORMAT_F5_HEIGHT_SHIFT 202019# define RADEON_TXFORMAT_ST_ROUTE_STQ0 (0 << 24)2020# define RADEON_TXFORMAT_ST_ROUTE_MASK (3 << 24)2021# define RADEON_TXFORMAT_ST_ROUTE_STQ1 (1 << 24)2022# define RADEON_TXFORMAT_ST_ROUTE_STQ2 (2 << 24)2023# define RADEON_TXFORMAT_ENDIAN_NO_SWAP (0 << 26)2024# define RADEON_TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26)2025# define RADEON_TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26)2026# define RADEON_TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26)2027# define RADEON_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28)2028# define RADEON_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29)2029# define RADEON_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30)2030# define RADEON_TXFORMAT_PERSPECTIVE_ENABLE (1 << 31)2031#define RADEON_PP_CUBIC_FACES_0 0x1d242032#define RADEON_PP_CUBIC_FACES_1 0x1d282033#define RADEON_PP_CUBIC_FACES_2 0x1d2c2034# define RADEON_FACE_WIDTH_1_SHIFT 02035# define RADEON_FACE_HEIGHT_1_SHIFT 42036# define RADEON_FACE_WIDTH_1_MASK (0xf << 0)2037# define RADEON_FACE_HEIGHT_1_MASK (0xf << 4)2038# define RADEON_FACE_WIDTH_2_SHIFT 82039# define RADEON_FACE_HEIGHT_2_SHIFT 122040# define RADEON_FACE_WIDTH_2_MASK (0xf << 8)2041# define RADEON_FACE_HEIGHT_2_MASK (0xf << 12)2042# define RADEON_FACE_WIDTH_3_SHIFT 162043# define RADEON_FACE_HEIGHT_3_SHIFT 202044# define RADEON_FACE_WIDTH_3_MASK (0xf << 16)2045# define RADEON_FACE_HEIGHT_3_MASK (0xf << 20)2046# define RADEON_FACE_WIDTH_4_SHIFT 242047# define RADEON_FACE_HEIGHT_4_SHIFT 282048# define RADEON_FACE_WIDTH_4_MASK (0xf << 24)2049# define RADEON_FACE_HEIGHT_4_MASK (0xf << 28)2050 2051#define RADEON_PP_TXOFFSET_0 0x1c5c2052#define RADEON_PP_TXOFFSET_1 0x1c742053#define RADEON_PP_TXOFFSET_2 0x1c8c2054# define RADEON_TXO_ENDIAN_NO_SWAP (0 << 0)2055# define RADEON_TXO_ENDIAN_BYTE_SWAP (1 << 0)2056# define RADEON_TXO_ENDIAN_WORD_SWAP (2 << 0)2057# define RADEON_TXO_ENDIAN_HALFDW_SWAP (3 << 0)2058# define RADEON_TXO_MACRO_LINEAR (0 << 2)2059# define RADEON_TXO_MACRO_TILE (1 << 2)2060# define RADEON_TXO_MICRO_LINEAR (0 << 3)2061# define RADEON_TXO_MICRO_TILE_X2 (1 << 3)2062# define RADEON_TXO_MICRO_TILE_OPT (2 << 3)2063# define RADEON_TXO_OFFSET_MASK 0xffffffe02064# define RADEON_TXO_OFFSET_SHIFT 52065 2066#define RADEON_PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */2067#define RADEON_PP_CUBIC_OFFSET_T0_1 0x1dd42068#define RADEON_PP_CUBIC_OFFSET_T0_2 0x1dd82069#define RADEON_PP_CUBIC_OFFSET_T0_3 0x1ddc2070#define RADEON_PP_CUBIC_OFFSET_T0_4 0x1de02071#define RADEON_PP_CUBIC_OFFSET_T1_0 0x1e002072#define RADEON_PP_CUBIC_OFFSET_T1_1 0x1e042073#define RADEON_PP_CUBIC_OFFSET_T1_2 0x1e082074#define RADEON_PP_CUBIC_OFFSET_T1_3 0x1e0c2075#define RADEON_PP_CUBIC_OFFSET_T1_4 0x1e102076#define RADEON_PP_CUBIC_OFFSET_T2_0 0x1e142077#define RADEON_PP_CUBIC_OFFSET_T2_1 0x1e182078#define RADEON_PP_CUBIC_OFFSET_T2_2 0x1e1c2079#define RADEON_PP_CUBIC_OFFSET_T2_3 0x1e202080#define RADEON_PP_CUBIC_OFFSET_T2_4 0x1e242081 2082#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */2083#define RADEON_PP_TEX_SIZE_1 0x1d0c2084#define RADEON_PP_TEX_SIZE_2 0x1d142085# define RADEON_TEX_USIZE_MASK (0x7ff << 0)2086# define RADEON_TEX_USIZE_SHIFT 02087# define RADEON_TEX_VSIZE_MASK (0x7ff << 16)2088# define RADEON_TEX_VSIZE_SHIFT 162089# define RADEON_SIGNED_RGB_MASK (1 << 30)2090# define RADEON_SIGNED_RGB_SHIFT 302091# define RADEON_SIGNED_ALPHA_MASK (1 << 31)2092# define RADEON_SIGNED_ALPHA_SHIFT 312093#define RADEON_PP_TEX_PITCH_0 0x1d08 /* NPOT */2094#define RADEON_PP_TEX_PITCH_1 0x1d10 /* NPOT */2095#define RADEON_PP_TEX_PITCH_2 0x1d18 /* NPOT */2096/* note: bits 13-5: 32 byte aligned stride of texture map */2097 2098#define RADEON_PP_TXCBLEND_0 0x1c602099#define RADEON_PP_TXCBLEND_1 0x1c782100#define RADEON_PP_TXCBLEND_2 0x1c902101# define RADEON_COLOR_ARG_A_SHIFT 02102# define RADEON_COLOR_ARG_A_MASK (0x1f << 0)2103# define RADEON_COLOR_ARG_A_ZERO (0 << 0)2104# define RADEON_COLOR_ARG_A_CURRENT_COLOR (2 << 0)2105# define RADEON_COLOR_ARG_A_CURRENT_ALPHA (3 << 0)2106# define RADEON_COLOR_ARG_A_DIFFUSE_COLOR (4 << 0)2107# define RADEON_COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0)2108# define RADEON_COLOR_ARG_A_SPECULAR_COLOR (6 << 0)2109# define RADEON_COLOR_ARG_A_SPECULAR_ALPHA (7 << 0)2110# define RADEON_COLOR_ARG_A_TFACTOR_COLOR (8 << 0)2111# define RADEON_COLOR_ARG_A_TFACTOR_ALPHA (9 << 0)2112# define RADEON_COLOR_ARG_A_T0_COLOR (10 << 0)2113# define RADEON_COLOR_ARG_A_T0_ALPHA (11 << 0)2114# define RADEON_COLOR_ARG_A_T1_COLOR (12 << 0)2115# define RADEON_COLOR_ARG_A_T1_ALPHA (13 << 0)2116# define RADEON_COLOR_ARG_A_T2_COLOR (14 << 0)2117# define RADEON_COLOR_ARG_A_T2_ALPHA (15 << 0)2118# define RADEON_COLOR_ARG_A_T3_COLOR (16 << 0)2119# define RADEON_COLOR_ARG_A_T3_ALPHA (17 << 0)2120# define RADEON_COLOR_ARG_B_SHIFT 52121# define RADEON_COLOR_ARG_B_MASK (0x1f << 5)2122# define RADEON_COLOR_ARG_B_ZERO (0 << 5)2123# define RADEON_COLOR_ARG_B_CURRENT_COLOR (2 << 5)2124# define RADEON_COLOR_ARG_B_CURRENT_ALPHA (3 << 5)2125# define RADEON_COLOR_ARG_B_DIFFUSE_COLOR (4 << 5)2126# define RADEON_COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5)2127# define RADEON_COLOR_ARG_B_SPECULAR_COLOR (6 << 5)2128# define RADEON_COLOR_ARG_B_SPECULAR_ALPHA (7 << 5)2129# define RADEON_COLOR_ARG_B_TFACTOR_COLOR (8 << 5)2130# define RADEON_COLOR_ARG_B_TFACTOR_ALPHA (9 << 5)2131# define RADEON_COLOR_ARG_B_T0_COLOR (10 << 5)2132# define RADEON_COLOR_ARG_B_T0_ALPHA (11 << 5)2133# define RADEON_COLOR_ARG_B_T1_COLOR (12 << 5)2134# define RADEON_COLOR_ARG_B_T1_ALPHA (13 << 5)2135# define RADEON_COLOR_ARG_B_T2_COLOR (14 << 5)2136# define RADEON_COLOR_ARG_B_T2_ALPHA (15 << 5)2137# define RADEON_COLOR_ARG_B_T3_COLOR (16 << 5)2138# define RADEON_COLOR_ARG_B_T3_ALPHA (17 << 5)2139# define RADEON_COLOR_ARG_C_SHIFT 102140# define RADEON_COLOR_ARG_C_MASK (0x1f << 10)2141# define RADEON_COLOR_ARG_C_ZERO (0 << 10)2142# define RADEON_COLOR_ARG_C_CURRENT_COLOR (2 << 10)2143# define RADEON_COLOR_ARG_C_CURRENT_ALPHA (3 << 10)2144# define RADEON_COLOR_ARG_C_DIFFUSE_COLOR (4 << 10)2145# define RADEON_COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10)2146# define RADEON_COLOR_ARG_C_SPECULAR_COLOR (6 << 10)2147# define RADEON_COLOR_ARG_C_SPECULAR_ALPHA (7 << 10)2148# define RADEON_COLOR_ARG_C_TFACTOR_COLOR (8 << 10)2149# define RADEON_COLOR_ARG_C_TFACTOR_ALPHA (9 << 10)2150# define RADEON_COLOR_ARG_C_T0_COLOR (10 << 10)2151# define RADEON_COLOR_ARG_C_T0_ALPHA (11 << 10)2152# define RADEON_COLOR_ARG_C_T1_COLOR (12 << 10)2153# define RADEON_COLOR_ARG_C_T1_ALPHA (13 << 10)2154# define RADEON_COLOR_ARG_C_T2_COLOR (14 << 10)2155# define RADEON_COLOR_ARG_C_T2_ALPHA (15 << 10)2156# define RADEON_COLOR_ARG_C_T3_COLOR (16 << 10)2157# define RADEON_COLOR_ARG_C_T3_ALPHA (17 << 10)2158# define RADEON_COMP_ARG_A (1 << 15)2159# define RADEON_COMP_ARG_A_SHIFT 152160# define RADEON_COMP_ARG_B (1 << 16)2161# define RADEON_COMP_ARG_B_SHIFT 162162# define RADEON_COMP_ARG_C (1 << 17)2163# define RADEON_COMP_ARG_C_SHIFT 172164# define RADEON_BLEND_CTL_MASK (7 << 18)2165# define RADEON_BLEND_CTL_ADD (0 << 18)2166# define RADEON_BLEND_CTL_SUBTRACT (1 << 18)2167# define RADEON_BLEND_CTL_ADDSIGNED (2 << 18)2168# define RADEON_BLEND_CTL_BLEND (3 << 18)2169# define RADEON_BLEND_CTL_DOT3 (4 << 18)2170# define RADEON_SCALE_SHIFT 212171# define RADEON_SCALE_MASK (3 << 21)2172# define RADEON_SCALE_1X (0 << 21)2173# define RADEON_SCALE_2X (1 << 21)2174# define RADEON_SCALE_4X (2 << 21)2175# define RADEON_CLAMP_TX (1 << 23)2176# define RADEON_T0_EQ_TCUR (1 << 24)2177# define RADEON_T1_EQ_TCUR (1 << 25)2178# define RADEON_T2_EQ_TCUR (1 << 26)2179# define RADEON_T3_EQ_TCUR (1 << 27)2180# define RADEON_COLOR_ARG_MASK 0x1f2181# define RADEON_COMP_ARG_SHIFT 152182#define RADEON_PP_TXABLEND_0 0x1c642183#define RADEON_PP_TXABLEND_1 0x1c7c2184#define RADEON_PP_TXABLEND_2 0x1c942185# define RADEON_ALPHA_ARG_A_SHIFT 02186# define RADEON_ALPHA_ARG_A_MASK (0xf << 0)2187# define RADEON_ALPHA_ARG_A_ZERO (0 << 0)2188# define RADEON_ALPHA_ARG_A_CURRENT_ALPHA (1 << 0)2189# define RADEON_ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0)2190# define RADEON_ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0)2191# define RADEON_ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0)2192# define RADEON_ALPHA_ARG_A_T0_ALPHA (5 << 0)2193# define RADEON_ALPHA_ARG_A_T1_ALPHA (6 << 0)2194# define RADEON_ALPHA_ARG_A_T2_ALPHA (7 << 0)2195# define RADEON_ALPHA_ARG_A_T3_ALPHA (8 << 0)2196# define RADEON_ALPHA_ARG_B_SHIFT 42197# define RADEON_ALPHA_ARG_B_MASK (0xf << 4)2198# define RADEON_ALPHA_ARG_B_ZERO (0 << 4)2199# define RADEON_ALPHA_ARG_B_CURRENT_ALPHA (1 << 4)2200# define RADEON_ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4)2201# define RADEON_ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4)2202# define RADEON_ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4)2203# define RADEON_ALPHA_ARG_B_T0_ALPHA (5 << 4)2204# define RADEON_ALPHA_ARG_B_T1_ALPHA (6 << 4)2205# define RADEON_ALPHA_ARG_B_T2_ALPHA (7 << 4)2206# define RADEON_ALPHA_ARG_B_T3_ALPHA (8 << 4)2207# define RADEON_ALPHA_ARG_C_SHIFT 82208# define RADEON_ALPHA_ARG_C_MASK (0xf << 8)2209# define RADEON_ALPHA_ARG_C_ZERO (0 << 8)2210# define RADEON_ALPHA_ARG_C_CURRENT_ALPHA (1 << 8)2211# define RADEON_ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8)2212# define RADEON_ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8)2213# define RADEON_ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8)2214# define RADEON_ALPHA_ARG_C_T0_ALPHA (5 << 8)2215# define RADEON_ALPHA_ARG_C_T1_ALPHA (6 << 8)2216# define RADEON_ALPHA_ARG_C_T2_ALPHA (7 << 8)2217# define RADEON_ALPHA_ARG_C_T3_ALPHA (8 << 8)2218# define RADEON_DOT_ALPHA_DONT_REPLICATE (1 << 9)2219# define RADEON_ALPHA_ARG_MASK 0xf2220 2221#define RADEON_PP_TFACTOR_0 0x1c682222#define RADEON_PP_TFACTOR_1 0x1c802223#define RADEON_PP_TFACTOR_2 0x1c982224 2225#define RADEON_RB3D_BLENDCNTL 0x1c202226# define RADEON_COMB_FCN_MASK (3 << 12)2227# define RADEON_COMB_FCN_ADD_CLAMP (0 << 12)2228# define RADEON_COMB_FCN_ADD_NOCLAMP (1 << 12)2229# define RADEON_COMB_FCN_SUB_CLAMP (2 << 12)2230# define RADEON_COMB_FCN_SUB_NOCLAMP (3 << 12)2231# define RADEON_SRC_BLEND_GL_ZERO (32 << 16)2232# define RADEON_SRC_BLEND_GL_ONE (33 << 16)2233# define RADEON_SRC_BLEND_GL_SRC_COLOR (34 << 16)2234# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16)2235# define RADEON_SRC_BLEND_GL_DST_COLOR (36 << 16)2236# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16)2237# define RADEON_SRC_BLEND_GL_SRC_ALPHA (38 << 16)2238# define RADEON_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16)2239# define RADEON_SRC_BLEND_GL_DST_ALPHA (40 << 16)2240# define RADEON_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16)2241# define RADEON_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16)2242# define RADEON_SRC_BLEND_MASK (63 << 16)2243# define RADEON_DST_BLEND_GL_ZERO (32 << 24)2244# define RADEON_DST_BLEND_GL_ONE (33 << 24)2245# define RADEON_DST_BLEND_GL_SRC_COLOR (34 << 24)2246# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24)2247# define RADEON_DST_BLEND_GL_DST_COLOR (36 << 24)2248# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24)2249# define RADEON_DST_BLEND_GL_SRC_ALPHA (38 << 24)2250# define RADEON_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24)2251# define RADEON_DST_BLEND_GL_DST_ALPHA (40 << 24)2252# define RADEON_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24)2253# define RADEON_DST_BLEND_MASK (63 << 24)2254#define RADEON_RB3D_CNTL 0x1c3c2255# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)2256# define RADEON_PLANE_MASK_ENABLE (1 << 1)2257# define RADEON_DITHER_ENABLE (1 << 2)2258# define RADEON_ROUND_ENABLE (1 << 3)2259# define RADEON_SCALE_DITHER_ENABLE (1 << 4)2260# define RADEON_DITHER_INIT (1 << 5)2261# define RADEON_ROP_ENABLE (1 << 6)2262# define RADEON_STENCIL_ENABLE (1 << 7)2263# define RADEON_Z_ENABLE (1 << 8)2264# define RADEON_DEPTHXY_OFFSET_ENABLE (1 << 9)2265# define RADEON_RB3D_COLOR_FORMAT_SHIFT 102266 2267# define RADEON_COLOR_FORMAT_ARGB1555 32268# define RADEON_COLOR_FORMAT_RGB565 42269# define RADEON_COLOR_FORMAT_ARGB8888 62270# define RADEON_COLOR_FORMAT_RGB332 72271# define RADEON_COLOR_FORMAT_Y8 82272# define RADEON_COLOR_FORMAT_RGB8 92273# define RADEON_COLOR_FORMAT_YUV422_VYUY 112274# define RADEON_COLOR_FORMAT_YUV422_YVYU 122275# define RADEON_COLOR_FORMAT_aYUV444 142276# define RADEON_COLOR_FORMAT_ARGB4444 152277 2278# define RADEON_CLRCMP_FLIP_ENABLE (1 << 14)2279#define RADEON_RB3D_COLOROFFSET 0x1c402280# define RADEON_COLOROFFSET_MASK 0xfffffff02281#define RADEON_RB3D_COLORPITCH 0x1c482282# define RADEON_COLORPITCH_MASK 0x000001ff82283# define RADEON_COLOR_TILE_ENABLE (1 << 16)2284# define RADEON_COLOR_MICROTILE_ENABLE (1 << 17)2285# define RADEON_COLOR_ENDIAN_NO_SWAP (0 << 18)2286# define RADEON_COLOR_ENDIAN_WORD_SWAP (1 << 18)2287# define RADEON_COLOR_ENDIAN_DWORD_SWAP (2 << 18)2288#define RADEON_RB3D_DEPTHOFFSET 0x1c242289#define RADEON_RB3D_DEPTHPITCH 0x1c282290# define RADEON_DEPTHPITCH_MASK 0x00001ff82291# define RADEON_DEPTH_ENDIAN_NO_SWAP (0 << 18)2292# define RADEON_DEPTH_ENDIAN_WORD_SWAP (1 << 18)2293# define RADEON_DEPTH_ENDIAN_DWORD_SWAP (2 << 18)2294#define RADEON_RB3D_PLANEMASK 0x1d842295#define RADEON_RB3D_ROPCNTL 0x1d802296# define RADEON_ROP_MASK (15 << 8)2297# define RADEON_ROP_CLEAR (0 << 8)2298# define RADEON_ROP_NOR (1 << 8)2299# define RADEON_ROP_AND_INVERTED (2 << 8)2300# define RADEON_ROP_COPY_INVERTED (3 << 8)2301# define RADEON_ROP_AND_REVERSE (4 << 8)2302# define RADEON_ROP_INVERT (5 << 8)2303# define RADEON_ROP_XOR (6 << 8)2304# define RADEON_ROP_NAND (7 << 8)2305# define RADEON_ROP_AND (8 << 8)2306# define RADEON_ROP_EQUIV (9 << 8)2307# define RADEON_ROP_NOOP (10 << 8)2308# define RADEON_ROP_OR_INVERTED (11 << 8)2309# define RADEON_ROP_COPY (12 << 8)2310# define RADEON_ROP_OR_REVERSE (13 << 8)2311# define RADEON_ROP_OR (14 << 8)2312# define RADEON_ROP_SET (15 << 8)2313#define RADEON_RB3D_STENCILREFMASK 0x1d7c2314# define RADEON_STENCIL_REF_SHIFT 02315# define RADEON_STENCIL_REF_MASK (0xff << 0)2316# define RADEON_STENCIL_MASK_SHIFT 162317# define RADEON_STENCIL_VALUE_MASK (0xff << 16)2318# define RADEON_STENCIL_WRITEMASK_SHIFT 242319# define RADEON_STENCIL_WRITE_MASK (0xff << 24)2320#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c2321# define RADEON_DEPTH_FORMAT_MASK (0xf << 0)2322# define RADEON_DEPTH_FORMAT_16BIT_INT_Z (0 << 0)2323# define RADEON_DEPTH_FORMAT_24BIT_INT_Z (2 << 0)2324# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0)2325# define RADEON_DEPTH_FORMAT_32BIT_INT_Z (4 << 0)2326# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0)2327# define RADEON_DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0)2328# define RADEON_DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0)2329# define RADEON_DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0)2330# define RADEON_Z_TEST_NEVER (0 << 4)2331# define RADEON_Z_TEST_LESS (1 << 4)2332# define RADEON_Z_TEST_LEQUAL (2 << 4)2333# define RADEON_Z_TEST_EQUAL (3 << 4)2334# define RADEON_Z_TEST_GEQUAL (4 << 4)2335# define RADEON_Z_TEST_GREATER (5 << 4)2336# define RADEON_Z_TEST_NEQUAL (6 << 4)2337# define RADEON_Z_TEST_ALWAYS (7 << 4)2338# define RADEON_Z_TEST_MASK (7 << 4)2339# define RADEON_STENCIL_TEST_NEVER (0 << 12)2340# define RADEON_STENCIL_TEST_LESS (1 << 12)2341# define RADEON_STENCIL_TEST_LEQUAL (2 << 12)2342# define RADEON_STENCIL_TEST_EQUAL (3 << 12)2343# define RADEON_STENCIL_TEST_GEQUAL (4 << 12)2344# define RADEON_STENCIL_TEST_GREATER (5 << 12)2345# define RADEON_STENCIL_TEST_NEQUAL (6 << 12)2346# define RADEON_STENCIL_TEST_ALWAYS (7 << 12)2347# define RADEON_STENCIL_TEST_MASK (0x7 << 12)2348# define RADEON_STENCIL_FAIL_KEEP (0 << 16)2349# define RADEON_STENCIL_FAIL_ZERO (1 << 16)2350# define RADEON_STENCIL_FAIL_REPLACE (2 << 16)2351# define RADEON_STENCIL_FAIL_INC (3 << 16)2352# define RADEON_STENCIL_FAIL_DEC (4 << 16)2353# define RADEON_STENCIL_FAIL_INVERT (5 << 16)2354# define RADEON_STENCIL_FAIL_MASK (0x7 << 16)2355# define RADEON_STENCIL_ZPASS_KEEP (0 << 20)2356# define RADEON_STENCIL_ZPASS_ZERO (1 << 20)2357# define RADEON_STENCIL_ZPASS_REPLACE (2 << 20)2358# define RADEON_STENCIL_ZPASS_INC (3 << 20)2359# define RADEON_STENCIL_ZPASS_DEC (4 << 20)2360# define RADEON_STENCIL_ZPASS_INVERT (5 << 20)2361# define RADEON_STENCIL_ZPASS_MASK (0x7 << 20)2362# define RADEON_STENCIL_ZFAIL_KEEP (0 << 24)2363# define RADEON_STENCIL_ZFAIL_ZERO (1 << 24)2364# define RADEON_STENCIL_ZFAIL_REPLACE (2 << 24)2365# define RADEON_STENCIL_ZFAIL_INC (3 << 24)2366# define RADEON_STENCIL_ZFAIL_DEC (4 << 24)2367# define RADEON_STENCIL_ZFAIL_INVERT (5 << 24)2368# define RADEON_STENCIL_ZFAIL_MASK (0x7 << 24)2369# define RADEON_Z_COMPRESSION_ENABLE (1 << 28)2370# define RADEON_FORCE_Z_DIRTY (1 << 29)2371# define RADEON_Z_WRITE_ENABLE (1 << 30)2372#define RADEON_RE_LINE_PATTERN 0x1cd02373# define RADEON_LINE_PATTERN_MASK 0x0000ffff2374# define RADEON_LINE_REPEAT_COUNT_SHIFT 162375# define RADEON_LINE_PATTERN_START_SHIFT 242376# define RADEON_LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28)2377# define RADEON_LINE_PATTERN_BIG_BIT_ORDER (1 << 28)2378# define RADEON_LINE_PATTERN_AUTO_RESET (1 << 29)2379#define RADEON_RE_LINE_STATE 0x1cd42380# define RADEON_LINE_CURRENT_PTR_SHIFT 02381# define RADEON_LINE_CURRENT_COUNT_SHIFT 82382#define RADEON_RE_MISC 0x26c42383# define RADEON_STIPPLE_COORD_MASK 0x1f2384# define RADEON_STIPPLE_X_OFFSET_SHIFT 02385# define RADEON_STIPPLE_X_OFFSET_MASK (0x1f << 0)2386# define RADEON_STIPPLE_Y_OFFSET_SHIFT 82387# define RADEON_STIPPLE_Y_OFFSET_MASK (0x1f << 8)2388# define RADEON_STIPPLE_LITTLE_BIT_ORDER (0 << 16)2389# define RADEON_STIPPLE_BIG_BIT_ORDER (1 << 16)2390#define RADEON_RE_SOLID_COLOR 0x1c1c2391#define RADEON_RE_TOP_LEFT 0x26c02392# define RADEON_RE_LEFT_SHIFT 02393# define RADEON_RE_TOP_SHIFT 162394#define RADEON_RE_WIDTH_HEIGHT 0x1c442395# define RADEON_RE_WIDTH_SHIFT 02396# define RADEON_RE_HEIGHT_SHIFT 162397 2398#define RADEON_RB3D_ZPASS_DATA 0x32902399#define RADEON_RB3D_ZPASS_ADDR 0x32942400 2401#define RADEON_SE_CNTL 0x1c4c2402# define RADEON_FFACE_CULL_CW (0 << 0)2403# define RADEON_FFACE_CULL_CCW (1 << 0)2404# define RADEON_FFACE_CULL_DIR_MASK (1 << 0)2405# define RADEON_BFACE_CULL (0 << 1)2406# define RADEON_BFACE_SOLID (3 << 1)2407# define RADEON_FFACE_CULL (0 << 3)2408# define RADEON_FFACE_SOLID (3 << 3)2409# define RADEON_FFACE_CULL_MASK (3 << 3)2410# define RADEON_BADVTX_CULL_DISABLE (1 << 5)2411# define RADEON_FLAT_SHADE_VTX_0 (0 << 6)2412# define RADEON_FLAT_SHADE_VTX_1 (1 << 6)2413# define RADEON_FLAT_SHADE_VTX_2 (2 << 6)2414# define RADEON_FLAT_SHADE_VTX_LAST (3 << 6)2415# define RADEON_DIFFUSE_SHADE_SOLID (0 << 8)2416# define RADEON_DIFFUSE_SHADE_FLAT (1 << 8)2417# define RADEON_DIFFUSE_SHADE_GOURAUD (2 << 8)2418# define RADEON_DIFFUSE_SHADE_MASK (3 << 8)2419# define RADEON_ALPHA_SHADE_SOLID (0 << 10)2420# define RADEON_ALPHA_SHADE_FLAT (1 << 10)2421# define RADEON_ALPHA_SHADE_GOURAUD (2 << 10)2422# define RADEON_ALPHA_SHADE_MASK (3 << 10)2423# define RADEON_SPECULAR_SHADE_SOLID (0 << 12)2424# define RADEON_SPECULAR_SHADE_FLAT (1 << 12)2425# define RADEON_SPECULAR_SHADE_GOURAUD (2 << 12)2426# define RADEON_SPECULAR_SHADE_MASK (3 << 12)2427# define RADEON_FOG_SHADE_SOLID (0 << 14)2428# define RADEON_FOG_SHADE_FLAT (1 << 14)2429# define RADEON_FOG_SHADE_GOURAUD (2 << 14)2430# define RADEON_FOG_SHADE_MASK (3 << 14)2431# define RADEON_ZBIAS_ENABLE_POINT (1 << 16)2432# define RADEON_ZBIAS_ENABLE_LINE (1 << 17)2433# define RADEON_ZBIAS_ENABLE_TRI (1 << 18)2434# define RADEON_WIDELINE_ENABLE (1 << 20)2435# define RADEON_VPORT_XY_XFORM_ENABLE (1 << 24)2436# define RADEON_VPORT_Z_XFORM_ENABLE (1 << 25)2437# define RADEON_VTX_PIX_CENTER_D3D (0 << 27)2438# define RADEON_VTX_PIX_CENTER_OGL (1 << 27)2439# define RADEON_ROUND_MODE_TRUNC (0 << 28)2440# define RADEON_ROUND_MODE_ROUND (1 << 28)2441# define RADEON_ROUND_MODE_ROUND_EVEN (2 << 28)2442# define RADEON_ROUND_MODE_ROUND_ODD (3 << 28)2443# define RADEON_ROUND_PREC_16TH_PIX (0 << 30)2444# define RADEON_ROUND_PREC_8TH_PIX (1 << 30)2445# define RADEON_ROUND_PREC_4TH_PIX (2 << 30)2446# define RADEON_ROUND_PREC_HALF_PIX (3 << 30)2447#define R200_RE_CNTL 0x1c502448# define R200_STIPPLE_ENABLE 0x12449# define R200_SCISSOR_ENABLE 0x22450# define R200_PATTERN_ENABLE 0x42451# define R200_PERSPECTIVE_ENABLE 0x82452# define R200_POINT_SMOOTH 0x202453# define R200_VTX_STQ0_D3D 0x000100002454# define R200_VTX_STQ1_D3D 0x000400002455# define R200_VTX_STQ2_D3D 0x001000002456# define R200_VTX_STQ3_D3D 0x004000002457# define R200_VTX_STQ4_D3D 0x010000002458# define R200_VTX_STQ5_D3D 0x040000002459#define RADEON_SE_CNTL_STATUS 0x21402460# define RADEON_VC_NO_SWAP (0 << 0)2461# define RADEON_VC_16BIT_SWAP (1 << 0)2462# define RADEON_VC_32BIT_SWAP (2 << 0)2463# define RADEON_VC_HALF_DWORD_SWAP (3 << 0)2464# define RADEON_TCL_BYPASS (1 << 8)2465#define RADEON_SE_COORD_FMT 0x1c502466# define RADEON_VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0)2467# define RADEON_VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1)2468# define RADEON_VTX_ST0_NONPARAMETRIC (1 << 8)2469# define RADEON_VTX_ST1_NONPARAMETRIC (1 << 9)2470# define RADEON_VTX_ST2_NONPARAMETRIC (1 << 10)2471# define RADEON_VTX_ST3_NONPARAMETRIC (1 << 11)2472# define RADEON_VTX_W0_NORMALIZE (1 << 12)2473# define RADEON_VTX_W0_IS_NOT_1_OVER_W0 (1 << 16)2474# define RADEON_VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17)2475# define RADEON_VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19)2476# define RADEON_VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21)2477# define RADEON_VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23)2478# define RADEON_TEX1_W_ROUTING_USE_W0 (0 << 26)2479# define RADEON_TEX1_W_ROUTING_USE_Q1 (1 << 26)2480#define RADEON_SE_LINE_WIDTH 0x1db82481#define RADEON_SE_TCL_LIGHT_MODEL_CTL 0x226c2482# define RADEON_LIGHTING_ENABLE (1 << 0)2483# define RADEON_LIGHT_IN_MODELSPACE (1 << 1)2484# define RADEON_LOCAL_VIEWER (1 << 2)2485# define RADEON_NORMALIZE_NORMALS (1 << 3)2486# define RADEON_RESCALE_NORMALS (1 << 4)2487# define RADEON_SPECULAR_LIGHTS (1 << 5)2488# define RADEON_DIFFUSE_SPECULAR_COMBINE (1 << 6)2489# define RADEON_LIGHT_ALPHA (1 << 7)2490# define RADEON_LOCAL_LIGHT_VEC_GL (1 << 8)2491# define RADEON_LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9)2492# define RADEON_LM_SOURCE_STATE_PREMULT 02493# define RADEON_LM_SOURCE_STATE_MULT 12494# define RADEON_LM_SOURCE_VERTEX_DIFFUSE 22495# define RADEON_LM_SOURCE_VERTEX_SPECULAR 32496# define RADEON_EMISSIVE_SOURCE_SHIFT 162497# define RADEON_AMBIENT_SOURCE_SHIFT 182498# define RADEON_DIFFUSE_SOURCE_SHIFT 202499# define RADEON_SPECULAR_SOURCE_SHIFT 222500#define RADEON_SE_TCL_MATERIAL_AMBIENT_RED 0x22202501#define RADEON_SE_TCL_MATERIAL_AMBIENT_GREEN 0x22242502#define RADEON_SE_TCL_MATERIAL_AMBIENT_BLUE 0x22282503#define RADEON_SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c2504#define RADEON_SE_TCL_MATERIAL_DIFFUSE_RED 0x22302505#define RADEON_SE_TCL_MATERIAL_DIFFUSE_GREEN 0x22342506#define RADEON_SE_TCL_MATERIAL_DIFFUSE_BLUE 0x22382507#define RADEON_SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c2508#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED 0x22102509#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x22142510#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x22182511#define RADEON_SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c2512#define RADEON_SE_TCL_MATERIAL_SPECULAR_RED 0x22402513#define RADEON_SE_TCL_MATERIAL_SPECULAR_GREEN 0x22442514#define RADEON_SE_TCL_MATERIAL_SPECULAR_BLUE 0x22482515#define RADEON_SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c2516#define RADEON_SE_TCL_MATRIX_SELECT_0 0x225c2517# define RADEON_MODELVIEW_0_SHIFT 02518# define RADEON_MODELVIEW_1_SHIFT 42519# define RADEON_MODELVIEW_2_SHIFT 82520# define RADEON_MODELVIEW_3_SHIFT 122521# define RADEON_IT_MODELVIEW_0_SHIFT 162522# define RADEON_IT_MODELVIEW_1_SHIFT 202523# define RADEON_IT_MODELVIEW_2_SHIFT 242524# define RADEON_IT_MODELVIEW_3_SHIFT 282525#define RADEON_SE_TCL_MATRIX_SELECT_1 0x22602526# define RADEON_MODELPROJECT_0_SHIFT 02527# define RADEON_MODELPROJECT_1_SHIFT 42528# define RADEON_MODELPROJECT_2_SHIFT 82529# define RADEON_MODELPROJECT_3_SHIFT 122530# define RADEON_TEXMAT_0_SHIFT 162531# define RADEON_TEXMAT_1_SHIFT 202532# define RADEON_TEXMAT_2_SHIFT 242533# define RADEON_TEXMAT_3_SHIFT 282534 2535 2536#define RADEON_SE_TCL_OUTPUT_VTX_FMT 0x22542537# define RADEON_TCL_VTX_W0 (1 << 0)2538# define RADEON_TCL_VTX_FP_DIFFUSE (1 << 1)2539# define RADEON_TCL_VTX_FP_ALPHA (1 << 2)2540# define RADEON_TCL_VTX_PK_DIFFUSE (1 << 3)2541# define RADEON_TCL_VTX_FP_SPEC (1 << 4)2542# define RADEON_TCL_VTX_FP_FOG (1 << 5)2543# define RADEON_TCL_VTX_PK_SPEC (1 << 6)2544# define RADEON_TCL_VTX_ST0 (1 << 7)2545# define RADEON_TCL_VTX_ST1 (1 << 8)2546# define RADEON_TCL_VTX_Q1 (1 << 9)2547# define RADEON_TCL_VTX_ST2 (1 << 10)2548# define RADEON_TCL_VTX_Q2 (1 << 11)2549# define RADEON_TCL_VTX_ST3 (1 << 12)2550# define RADEON_TCL_VTX_Q3 (1 << 13)2551# define RADEON_TCL_VTX_Q0 (1 << 14)2552# define RADEON_TCL_VTX_WEIGHT_COUNT_SHIFT 152553# define RADEON_TCL_VTX_NORM0 (1 << 18)2554# define RADEON_TCL_VTX_XY1 (1 << 27)2555# define RADEON_TCL_VTX_Z1 (1 << 28)2556# define RADEON_TCL_VTX_W1 (1 << 29)2557# define RADEON_TCL_VTX_NORM1 (1 << 30)2558# define RADEON_TCL_VTX_Z0 (1 << 31)2559 2560#define RADEON_SE_TCL_OUTPUT_VTX_SEL 0x22582561# define RADEON_TCL_COMPUTE_XYZW (1 << 0)2562# define RADEON_TCL_COMPUTE_DIFFUSE (1 << 1)2563# define RADEON_TCL_COMPUTE_SPECULAR (1 << 2)2564# define RADEON_TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3)2565# define RADEON_TCL_FORCE_INORDER_PROC (1 << 4)2566# define RADEON_TCL_TEX_INPUT_TEX_0 02567# define RADEON_TCL_TEX_INPUT_TEX_1 12568# define RADEON_TCL_TEX_INPUT_TEX_2 22569# define RADEON_TCL_TEX_INPUT_TEX_3 32570# define RADEON_TCL_TEX_COMPUTED_TEX_0 82571# define RADEON_TCL_TEX_COMPUTED_TEX_1 92572# define RADEON_TCL_TEX_COMPUTED_TEX_2 102573# define RADEON_TCL_TEX_COMPUTED_TEX_3 112574# define RADEON_TCL_TEX_0_OUTPUT_SHIFT 162575# define RADEON_TCL_TEX_1_OUTPUT_SHIFT 202576# define RADEON_TCL_TEX_2_OUTPUT_SHIFT 242577# define RADEON_TCL_TEX_3_OUTPUT_SHIFT 282578 2579#define RADEON_SE_TCL_PER_LIGHT_CTL_0 0x22702580# define RADEON_LIGHT_0_ENABLE (1 << 0)2581# define RADEON_LIGHT_0_ENABLE_AMBIENT (1 << 1)2582# define RADEON_LIGHT_0_ENABLE_SPECULAR (1 << 2)2583# define RADEON_LIGHT_0_IS_LOCAL (1 << 3)2584# define RADEON_LIGHT_0_IS_SPOT (1 << 4)2585# define RADEON_LIGHT_0_DUAL_CONE (1 << 5)2586# define RADEON_LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6)2587# define RADEON_LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7)2588# define RADEON_LIGHT_0_SHIFT 02589# define RADEON_LIGHT_1_ENABLE (1 << 16)2590# define RADEON_LIGHT_1_ENABLE_AMBIENT (1 << 17)2591# define RADEON_LIGHT_1_ENABLE_SPECULAR (1 << 18)2592# define RADEON_LIGHT_1_IS_LOCAL (1 << 19)2593# define RADEON_LIGHT_1_IS_SPOT (1 << 20)2594# define RADEON_LIGHT_1_DUAL_CONE (1 << 21)2595# define RADEON_LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22)2596# define RADEON_LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23)2597# define RADEON_LIGHT_1_SHIFT 162598#define RADEON_SE_TCL_PER_LIGHT_CTL_1 0x22742599# define RADEON_LIGHT_2_SHIFT 02600# define RADEON_LIGHT_3_SHIFT 162601#define RADEON_SE_TCL_PER_LIGHT_CTL_2 0x22782602# define RADEON_LIGHT_4_SHIFT 02603# define RADEON_LIGHT_5_SHIFT 162604#define RADEON_SE_TCL_PER_LIGHT_CTL_3 0x227c2605# define RADEON_LIGHT_6_SHIFT 02606# define RADEON_LIGHT_7_SHIFT 162607 2608#define RADEON_SE_TCL_SHININESS 0x22502609 2610#define RADEON_SE_TCL_TEXTURE_PROC_CTL 0x22682611# define RADEON_TEXGEN_TEXMAT_0_ENABLE (1 << 0)2612# define RADEON_TEXGEN_TEXMAT_1_ENABLE (1 << 1)2613# define RADEON_TEXGEN_TEXMAT_2_ENABLE (1 << 2)2614# define RADEON_TEXGEN_TEXMAT_3_ENABLE (1 << 3)2615# define RADEON_TEXMAT_0_ENABLE (1 << 4)2616# define RADEON_TEXMAT_1_ENABLE (1 << 5)2617# define RADEON_TEXMAT_2_ENABLE (1 << 6)2618# define RADEON_TEXMAT_3_ENABLE (1 << 7)2619# define RADEON_TEXGEN_INPUT_MASK 0xf2620# define RADEON_TEXGEN_INPUT_TEXCOORD_0 02621# define RADEON_TEXGEN_INPUT_TEXCOORD_1 12622# define RADEON_TEXGEN_INPUT_TEXCOORD_2 22623# define RADEON_TEXGEN_INPUT_TEXCOORD_3 32624# define RADEON_TEXGEN_INPUT_OBJ 42625# define RADEON_TEXGEN_INPUT_EYE 52626# define RADEON_TEXGEN_INPUT_EYE_NORMAL 62627# define RADEON_TEXGEN_INPUT_EYE_REFLECT 72628# define RADEON_TEXGEN_INPUT_EYE_NORMALIZED 82629# define RADEON_TEXGEN_0_INPUT_SHIFT 162630# define RADEON_TEXGEN_1_INPUT_SHIFT 202631# define RADEON_TEXGEN_2_INPUT_SHIFT 242632# define RADEON_TEXGEN_3_INPUT_SHIFT 282633 2634#define RADEON_SE_TCL_UCP_VERT_BLEND_CTL 0x22642635# define RADEON_UCP_IN_CLIP_SPACE (1 << 0)2636# define RADEON_UCP_IN_MODEL_SPACE (1 << 1)2637# define RADEON_UCP_ENABLE_0 (1 << 2)2638# define RADEON_UCP_ENABLE_1 (1 << 3)2639# define RADEON_UCP_ENABLE_2 (1 << 4)2640# define RADEON_UCP_ENABLE_3 (1 << 5)2641# define RADEON_UCP_ENABLE_4 (1 << 6)2642# define RADEON_UCP_ENABLE_5 (1 << 7)2643# define RADEON_TCL_FOG_MASK (3 << 8)2644# define RADEON_TCL_FOG_DISABLE (0 << 8)2645# define RADEON_TCL_FOG_EXP (1 << 8)2646# define RADEON_TCL_FOG_EXP2 (2 << 8)2647# define RADEON_TCL_FOG_LINEAR (3 << 8)2648# define RADEON_RNG_BASED_FOG (1 << 10)2649# define RADEON_LIGHT_TWOSIDE (1 << 11)2650# define RADEON_BLEND_OP_COUNT_MASK (7 << 12)2651# define RADEON_BLEND_OP_COUNT_SHIFT 122652# define RADEON_POSITION_BLEND_OP_ENABLE (1 << 16)2653# define RADEON_NORMAL_BLEND_OP_ENABLE (1 << 17)2654# define RADEON_VERTEX_BLEND_SRC_0_PRIMARY (1 << 18)2655# define RADEON_VERTEX_BLEND_SRC_0_SECONDARY (1 << 18)2656# define RADEON_VERTEX_BLEND_SRC_1_PRIMARY (1 << 19)2657# define RADEON_VERTEX_BLEND_SRC_1_SECONDARY (1 << 19)2658# define RADEON_VERTEX_BLEND_SRC_2_PRIMARY (1 << 20)2659# define RADEON_VERTEX_BLEND_SRC_2_SECONDARY (1 << 20)2660# define RADEON_VERTEX_BLEND_SRC_3_PRIMARY (1 << 21)2661# define RADEON_VERTEX_BLEND_SRC_3_SECONDARY (1 << 21)2662# define RADEON_VERTEX_BLEND_WGT_MINUS_ONE (1 << 22)2663# define RADEON_CULL_FRONT_IS_CW (0 << 28)2664# define RADEON_CULL_FRONT_IS_CCW (1 << 28)2665# define RADEON_CULL_FRONT (1 << 29)2666# define RADEON_CULL_BACK (1 << 30)2667# define RADEON_FORCE_W_TO_ONE (1 << 31)2668 2669#define RADEON_SE_VPORT_XSCALE 0x1d982670#define RADEON_SE_VPORT_XOFFSET 0x1d9c2671#define RADEON_SE_VPORT_YSCALE 0x1da02672#define RADEON_SE_VPORT_YOFFSET 0x1da42673#define RADEON_SE_VPORT_ZSCALE 0x1da82674#define RADEON_SE_VPORT_ZOFFSET 0x1dac2675#define RADEON_SE_ZBIAS_FACTOR 0x1db02676#define RADEON_SE_ZBIAS_CONSTANT 0x1db42677 2678#define RADEON_SE_VTX_FMT 0x20802679# define RADEON_SE_VTX_FMT_XY 0x000000002680# define RADEON_SE_VTX_FMT_W0 0x000000012681# define RADEON_SE_VTX_FMT_FPCOLOR 0x000000022682# define RADEON_SE_VTX_FMT_FPALPHA 0x000000042683# define RADEON_SE_VTX_FMT_PKCOLOR 0x000000082684# define RADEON_SE_VTX_FMT_FPSPEC 0x000000102685# define RADEON_SE_VTX_FMT_FPFOG 0x000000202686# define RADEON_SE_VTX_FMT_PKSPEC 0x000000402687# define RADEON_SE_VTX_FMT_ST0 0x000000802688# define RADEON_SE_VTX_FMT_ST1 0x000001002689# define RADEON_SE_VTX_FMT_Q1 0x000002002690# define RADEON_SE_VTX_FMT_ST2 0x000004002691# define RADEON_SE_VTX_FMT_Q2 0x000008002692# define RADEON_SE_VTX_FMT_ST3 0x000010002693# define RADEON_SE_VTX_FMT_Q3 0x000020002694# define RADEON_SE_VTX_FMT_Q0 0x000040002695# define RADEON_SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x000380002696# define RADEON_SE_VTX_FMT_N0 0x000400002697# define RADEON_SE_VTX_FMT_XY1 0x080000002698# define RADEON_SE_VTX_FMT_Z1 0x100000002699# define RADEON_SE_VTX_FMT_W1 0x200000002700# define RADEON_SE_VTX_FMT_N1 0x400000002701# define RADEON_SE_VTX_FMT_Z 0x800000002702 2703#define RADEON_SE_VF_CNTL 0x20842704# define RADEON_VF_PRIM_TYPE_POINT_LIST 12705# define RADEON_VF_PRIM_TYPE_LINE_LIST 22706# define RADEON_VF_PRIM_TYPE_LINE_STRIP 32707# define RADEON_VF_PRIM_TYPE_TRIANGLE_LIST 42708# define RADEON_VF_PRIM_TYPE_TRIANGLE_FAN 52709# define RADEON_VF_PRIM_TYPE_TRIANGLE_STRIP 62710# define RADEON_VF_PRIM_TYPE_TRIANGLE_FLAG 72711# define RADEON_VF_PRIM_TYPE_RECTANGLE_LIST 82712# define RADEON_VF_PRIM_TYPE_POINT_LIST_3 92713# define RADEON_VF_PRIM_TYPE_LINE_LIST_3 102714# define RADEON_VF_PRIM_TYPE_SPIRIT_LIST 112715# define RADEON_VF_PRIM_TYPE_LINE_LOOP 122716# define RADEON_VF_PRIM_TYPE_QUAD_LIST 132717# define RADEON_VF_PRIM_TYPE_QUAD_STRIP 142718# define RADEON_VF_PRIM_TYPE_POLYGON 152719# define RADEON_VF_PRIM_WALK_STATE (0<<4)2720# define RADEON_VF_PRIM_WALK_INDEX (1<<4)2721# define RADEON_VF_PRIM_WALK_LIST (2<<4)2722# define RADEON_VF_PRIM_WALK_DATA (3<<4)2723# define RADEON_VF_COLOR_ORDER_RGBA (1<<6)2724# define RADEON_VF_RADEON_MODE (1<<8)2725# define RADEON_VF_TCL_OUTPUT_CTL_ENA (1<<9)2726# define RADEON_VF_PROG_STREAM_ENA (1<<10)2727# define RADEON_VF_INDEX_SIZE_SHIFT 112728# define RADEON_VF_NUM_VERTICES_SHIFT 162729 2730#define RADEON_SE_PORT_DATA0 0x20002731 2732#define R200_SE_VAP_CNTL 0x20802733# define R200_VAP_TCL_ENABLE 0x000000012734# define R200_VAP_SINGLE_BUF_STATE_ENABLE 0x000000102735# define R200_VAP_FORCE_W_TO_ONE 0x000100002736# define R200_VAP_D3D_TEX_DEFAULT 0x000200002737# define R200_VAP_VF_MAX_VTX_NUM__SHIFT 182738# define R200_VAP_VF_MAX_VTX_NUM (9 << 18)2739# define R200_VAP_DX_CLIP_SPACE_DEF 0x004000002740#define R200_VF_MAX_VTX_INDX 0x210c2741#define R200_VF_MIN_VTX_INDX 0x21102742#define R200_SE_VTE_CNTL 0x20b02743# define R200_VPORT_X_SCALE_ENA 0x000000012744# define R200_VPORT_X_OFFSET_ENA 0x000000022745# define R200_VPORT_Y_SCALE_ENA 0x000000042746# define R200_VPORT_Y_OFFSET_ENA 0x000000082747# define R200_VPORT_Z_SCALE_ENA 0x000000102748# define R200_VPORT_Z_OFFSET_ENA 0x000000202749# define R200_VTX_XY_FMT 0x000001002750# define R200_VTX_Z_FMT 0x000002002751# define R200_VTX_W0_FMT 0x000004002752# define R200_VTX_W0_NORMALIZE 0x000008002753# define R200_VTX_ST_DENORMALIZED 0x000010002754#define R200_SE_VAP_CNTL_STATUS 0x21402755# define R200_VC_NO_SWAP (0 << 0)2756# define R200_VC_16BIT_SWAP (1 << 0)2757# define R200_VC_32BIT_SWAP (2 << 0)2758#define R200_PP_TXFILTER_0 0x2c002759#define R200_PP_TXFILTER_1 0x2c202760#define R200_PP_TXFILTER_2 0x2c402761#define R200_PP_TXFILTER_3 0x2c602762#define R200_PP_TXFILTER_4 0x2c802763#define R200_PP_TXFILTER_5 0x2ca02764# define R200_MAG_FILTER_NEAREST (0 << 0)2765# define R200_MAG_FILTER_LINEAR (1 << 0)2766# define R200_MAG_FILTER_MASK (1 << 0)2767# define R200_MIN_FILTER_NEAREST (0 << 1)2768# define R200_MIN_FILTER_LINEAR (1 << 1)2769# define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1)2770# define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1)2771# define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1)2772# define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1)2773# define R200_MIN_FILTER_ANISO_NEAREST (8 << 1)2774# define R200_MIN_FILTER_ANISO_LINEAR (9 << 1)2775# define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1)2776# define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1)2777# define R200_MIN_FILTER_MASK (15 << 1)2778# define R200_MAX_ANISO_1_TO_1 (0 << 5)2779# define R200_MAX_ANISO_2_TO_1 (1 << 5)2780# define R200_MAX_ANISO_4_TO_1 (2 << 5)2781# define R200_MAX_ANISO_8_TO_1 (3 << 5)2782# define R200_MAX_ANISO_16_TO_1 (4 << 5)2783# define R200_MAX_ANISO_MASK (7 << 5)2784# define R200_MAX_MIP_LEVEL_MASK (0x0f << 16)2785# define R200_MAX_MIP_LEVEL_SHIFT 162786# define R200_YUV_TO_RGB (1 << 20)2787# define R200_YUV_TEMPERATURE_COOL (0 << 21)2788# define R200_YUV_TEMPERATURE_HOT (1 << 21)2789# define R200_YUV_TEMPERATURE_MASK (1 << 21)2790# define R200_WRAPEN_S (1 << 22)2791# define R200_CLAMP_S_WRAP (0 << 23)2792# define R200_CLAMP_S_MIRROR (1 << 23)2793# define R200_CLAMP_S_CLAMP_LAST (2 << 23)2794# define R200_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23)2795# define R200_CLAMP_S_CLAMP_BORDER (4 << 23)2796# define R200_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23)2797# define R200_CLAMP_S_CLAMP_GL (6 << 23)2798# define R200_CLAMP_S_MIRROR_CLAMP_GL (7 << 23)2799# define R200_CLAMP_S_MASK (7 << 23)2800# define R200_WRAPEN_T (1 << 26)2801# define R200_CLAMP_T_WRAP (0 << 27)2802# define R200_CLAMP_T_MIRROR (1 << 27)2803# define R200_CLAMP_T_CLAMP_LAST (2 << 27)2804# define R200_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27)2805# define R200_CLAMP_T_CLAMP_BORDER (4 << 27)2806# define R200_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27)2807# define R200_CLAMP_T_CLAMP_GL (6 << 27)2808# define R200_CLAMP_T_MIRROR_CLAMP_GL (7 << 27)2809# define R200_CLAMP_T_MASK (7 << 27)2810# define R200_KILL_LT_ZERO (1 << 30)2811# define R200_BORDER_MODE_OGL (0 << 31)2812# define R200_BORDER_MODE_D3D (1 << 31)2813#define R200_PP_TXFORMAT_0 0x2c042814#define R200_PP_TXFORMAT_1 0x2c242815#define R200_PP_TXFORMAT_2 0x2c442816#define R200_PP_TXFORMAT_3 0x2c642817#define R200_PP_TXFORMAT_4 0x2c842818#define R200_PP_TXFORMAT_5 0x2ca42819# define R200_TXFORMAT_I8 (0 << 0)2820# define R200_TXFORMAT_AI88 (1 << 0)2821# define R200_TXFORMAT_RGB332 (2 << 0)2822# define R200_TXFORMAT_ARGB1555 (3 << 0)2823# define R200_TXFORMAT_RGB565 (4 << 0)2824# define R200_TXFORMAT_ARGB4444 (5 << 0)2825# define R200_TXFORMAT_ARGB8888 (6 << 0)2826# define R200_TXFORMAT_RGBA8888 (7 << 0)2827# define R200_TXFORMAT_Y8 (8 << 0)2828# define R200_TXFORMAT_AVYU4444 (9 << 0)2829# define R200_TXFORMAT_VYUY422 (10 << 0)2830# define R200_TXFORMAT_YVYU422 (11 << 0)2831# define R200_TXFORMAT_DXT1 (12 << 0)2832# define R200_TXFORMAT_DXT23 (14 << 0)2833# define R200_TXFORMAT_DXT45 (15 << 0)2834# define R200_TXFORMAT_DVDU88 (18 << 0)2835# define R200_TXFORMAT_LDVDU655 (19 << 0)2836# define R200_TXFORMAT_LDVDU8888 (20 << 0)2837# define R200_TXFORMAT_GR1616 (21 << 0)2838# define R200_TXFORMAT_ABGR8888 (22 << 0)2839# define R200_TXFORMAT_BGR111110 (23 << 0)2840# define R200_TXFORMAT_FORMAT_MASK (31 << 0)2841# define R200_TXFORMAT_FORMAT_SHIFT 02842# define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6)2843# define R200_TXFORMAT_NON_POWER2 (1 << 7)2844# define R200_TXFORMAT_WIDTH_MASK (15 << 8)2845# define R200_TXFORMAT_WIDTH_SHIFT 82846# define R200_TXFORMAT_HEIGHT_MASK (15 << 12)2847# define R200_TXFORMAT_HEIGHT_SHIFT 122848# define R200_TXFORMAT_F5_WIDTH_MASK (15 << 16) /* cube face 5 */2849# define R200_TXFORMAT_F5_WIDTH_SHIFT 162850# define R200_TXFORMAT_F5_HEIGHT_MASK (15 << 20)2851# define R200_TXFORMAT_F5_HEIGHT_SHIFT 202852# define R200_TXFORMAT_ST_ROUTE_STQ0 (0 << 24)2853# define R200_TXFORMAT_ST_ROUTE_STQ1 (1 << 24)2854# define R200_TXFORMAT_ST_ROUTE_STQ2 (2 << 24)2855# define R200_TXFORMAT_ST_ROUTE_STQ3 (3 << 24)2856# define R200_TXFORMAT_ST_ROUTE_STQ4 (4 << 24)2857# define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24)2858# define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24)2859# define R200_TXFORMAT_ST_ROUTE_SHIFT 242860# define R200_TXFORMAT_LOOKUP_DISABLE (1 << 27)2861# define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28)2862# define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29)2863# define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30)2864#define R200_PP_TXFORMAT_X_0 0x2c082865#define R200_PP_TXFORMAT_X_1 0x2c282866#define R200_PP_TXFORMAT_X_2 0x2c482867#define R200_PP_TXFORMAT_X_3 0x2c682868#define R200_PP_TXFORMAT_X_4 0x2c882869#define R200_PP_TXFORMAT_X_5 0x2ca82870 2871#define R200_PP_TXSIZE_0 0x2c0c /* NPOT only */2872#define R200_PP_TXSIZE_1 0x2c2c /* NPOT only */2873#define R200_PP_TXSIZE_2 0x2c4c /* NPOT only */2874#define R200_PP_TXSIZE_3 0x2c6c /* NPOT only */2875#define R200_PP_TXSIZE_4 0x2c8c /* NPOT only */2876#define R200_PP_TXSIZE_5 0x2cac /* NPOT only */2877 2878#define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */2879#define R200_PP_TXPITCH_1 0x2c30 /* NPOT only */2880#define R200_PP_TXPITCH_2 0x2c50 /* NPOT only */2881#define R200_PP_TXPITCH_3 0x2c70 /* NPOT only */2882#define R200_PP_TXPITCH_4 0x2c90 /* NPOT only */2883#define R200_PP_TXPITCH_5 0x2cb0 /* NPOT only */2884 2885#define R200_PP_CUBIC_FACES_0 0x2c182886#define R200_PP_CUBIC_FACES_1 0x2c382887#define R200_PP_CUBIC_FACES_2 0x2c582888#define R200_PP_CUBIC_FACES_3 0x2c782889#define R200_PP_CUBIC_FACES_4 0x2c982890#define R200_PP_CUBIC_FACES_5 0x2cb82891 2892#define R200_PP_TXOFFSET_0 0x2d002893# define R200_TXO_ENDIAN_NO_SWAP (0 << 0)2894# define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0)2895# define R200_TXO_ENDIAN_WORD_SWAP (2 << 0)2896# define R200_TXO_ENDIAN_HALFDW_SWAP (3 << 0)2897# define R200_TXO_MACRO_LINEAR (0 << 2)2898# define R200_TXO_MACRO_TILE (1 << 2)2899# define R200_TXO_MICRO_LINEAR (0 << 3)2900# define R200_TXO_MICRO_TILE (1 << 3)2901# define R200_TXO_OFFSET_MASK 0xffffffe02902# define R200_TXO_OFFSET_SHIFT 52903#define R200_PP_CUBIC_OFFSET_F1_0 0x2d042904#define R200_PP_CUBIC_OFFSET_F2_0 0x2d082905#define R200_PP_CUBIC_OFFSET_F3_0 0x2d0c2906#define R200_PP_CUBIC_OFFSET_F4_0 0x2d102907#define R200_PP_CUBIC_OFFSET_F5_0 0x2d142908 2909#define R200_PP_TXOFFSET_1 0x2d182910#define R200_PP_CUBIC_OFFSET_F1_1 0x2d1c2911#define R200_PP_CUBIC_OFFSET_F2_1 0x2d202912#define R200_PP_CUBIC_OFFSET_F3_1 0x2d242913#define R200_PP_CUBIC_OFFSET_F4_1 0x2d282914#define R200_PP_CUBIC_OFFSET_F5_1 0x2d2c2915 2916#define R200_PP_TXOFFSET_2 0x2d302917#define R200_PP_CUBIC_OFFSET_F1_2 0x2d342918#define R200_PP_CUBIC_OFFSET_F2_2 0x2d382919#define R200_PP_CUBIC_OFFSET_F3_2 0x2d3c2920#define R200_PP_CUBIC_OFFSET_F4_2 0x2d402921#define R200_PP_CUBIC_OFFSET_F5_2 0x2d442922 2923#define R200_PP_TXOFFSET_3 0x2d482924#define R200_PP_CUBIC_OFFSET_F1_3 0x2d4c2925#define R200_PP_CUBIC_OFFSET_F2_3 0x2d502926#define R200_PP_CUBIC_OFFSET_F3_3 0x2d542927#define R200_PP_CUBIC_OFFSET_F4_3 0x2d582928#define R200_PP_CUBIC_OFFSET_F5_3 0x2d5c2929#define R200_PP_TXOFFSET_4 0x2d602930#define R200_PP_CUBIC_OFFSET_F1_4 0x2d642931#define R200_PP_CUBIC_OFFSET_F2_4 0x2d682932#define R200_PP_CUBIC_OFFSET_F3_4 0x2d6c2933#define R200_PP_CUBIC_OFFSET_F4_4 0x2d702934#define R200_PP_CUBIC_OFFSET_F5_4 0x2d742935#define R200_PP_TXOFFSET_5 0x2d782936#define R200_PP_CUBIC_OFFSET_F1_5 0x2d7c2937#define R200_PP_CUBIC_OFFSET_F2_5 0x2d802938#define R200_PP_CUBIC_OFFSET_F3_5 0x2d842939#define R200_PP_CUBIC_OFFSET_F4_5 0x2d882940#define R200_PP_CUBIC_OFFSET_F5_5 0x2d8c2941 2942#define R200_PP_TFACTOR_0 0x2ee02943#define R200_PP_TFACTOR_1 0x2ee42944#define R200_PP_TFACTOR_2 0x2ee82945#define R200_PP_TFACTOR_3 0x2eec2946#define R200_PP_TFACTOR_4 0x2ef02947#define R200_PP_TFACTOR_5 0x2ef42948 2949#define R200_PP_TXCBLEND_0 0x2f002950# define R200_TXC_ARG_A_ZERO (0)2951# define R200_TXC_ARG_A_CURRENT_COLOR (2)2952# define R200_TXC_ARG_A_CURRENT_ALPHA (3)2953# define R200_TXC_ARG_A_DIFFUSE_COLOR (4)2954# define R200_TXC_ARG_A_DIFFUSE_ALPHA (5)2955# define R200_TXC_ARG_A_SPECULAR_COLOR (6)2956# define R200_TXC_ARG_A_SPECULAR_ALPHA (7)2957# define R200_TXC_ARG_A_TFACTOR_COLOR (8)2958# define R200_TXC_ARG_A_TFACTOR_ALPHA (9)2959# define R200_TXC_ARG_A_R0_COLOR (10)2960# define R200_TXC_ARG_A_R0_ALPHA (11)2961# define R200_TXC_ARG_A_R1_COLOR (12)2962# define R200_TXC_ARG_A_R1_ALPHA (13)2963# define R200_TXC_ARG_A_R2_COLOR (14)2964# define R200_TXC_ARG_A_R2_ALPHA (15)2965# define R200_TXC_ARG_A_R3_COLOR (16)2966# define R200_TXC_ARG_A_R3_ALPHA (17)2967# define R200_TXC_ARG_A_R4_COLOR (18)2968# define R200_TXC_ARG_A_R4_ALPHA (19)2969# define R200_TXC_ARG_A_R5_COLOR (20)2970# define R200_TXC_ARG_A_R5_ALPHA (21)2971# define R200_TXC_ARG_A_TFACTOR1_COLOR (26)2972# define R200_TXC_ARG_A_TFACTOR1_ALPHA (27)2973# define R200_TXC_ARG_A_MASK (31 << 0)2974# define R200_TXC_ARG_A_SHIFT 02975# define R200_TXC_ARG_B_ZERO (0 << 5)2976# define R200_TXC_ARG_B_CURRENT_COLOR (2 << 5)2977# define R200_TXC_ARG_B_CURRENT_ALPHA (3 << 5)2978# define R200_TXC_ARG_B_DIFFUSE_COLOR (4 << 5)2979# define R200_TXC_ARG_B_DIFFUSE_ALPHA (5 << 5)2980# define R200_TXC_ARG_B_SPECULAR_COLOR (6 << 5)2981# define R200_TXC_ARG_B_SPECULAR_ALPHA (7 << 5)2982# define R200_TXC_ARG_B_TFACTOR_COLOR (8 << 5)2983# define R200_TXC_ARG_B_TFACTOR_ALPHA (9 << 5)2984# define R200_TXC_ARG_B_R0_COLOR (10 << 5)2985# define R200_TXC_ARG_B_R0_ALPHA (11 << 5)2986# define R200_TXC_ARG_B_R1_COLOR (12 << 5)2987# define R200_TXC_ARG_B_R1_ALPHA (13 << 5)2988# define R200_TXC_ARG_B_R2_COLOR (14 << 5)2989# define R200_TXC_ARG_B_R2_ALPHA (15 << 5)2990# define R200_TXC_ARG_B_R3_COLOR (16 << 5)2991# define R200_TXC_ARG_B_R3_ALPHA (17 << 5)2992# define R200_TXC_ARG_B_R4_COLOR (18 << 5)2993# define R200_TXC_ARG_B_R4_ALPHA (19 << 5)2994# define R200_TXC_ARG_B_R5_COLOR (20 << 5)2995# define R200_TXC_ARG_B_R5_ALPHA (21 << 5)2996# define R200_TXC_ARG_B_TFACTOR1_COLOR (26 << 5)2997# define R200_TXC_ARG_B_TFACTOR1_ALPHA (27 << 5)2998# define R200_TXC_ARG_B_MASK (31 << 5)2999# define R200_TXC_ARG_B_SHIFT 53000# define R200_TXC_ARG_C_ZERO (0 << 10)3001# define R200_TXC_ARG_C_CURRENT_COLOR (2 << 10)3002# define R200_TXC_ARG_C_CURRENT_ALPHA (3 << 10)3003# define R200_TXC_ARG_C_DIFFUSE_COLOR (4 << 10)3004# define R200_TXC_ARG_C_DIFFUSE_ALPHA (5 << 10)3005# define R200_TXC_ARG_C_SPECULAR_COLOR (6 << 10)3006# define R200_TXC_ARG_C_SPECULAR_ALPHA (7 << 10)3007# define R200_TXC_ARG_C_TFACTOR_COLOR (8 << 10)3008# define R200_TXC_ARG_C_TFACTOR_ALPHA (9 << 10)3009# define R200_TXC_ARG_C_R0_COLOR (10 << 10)3010# define R200_TXC_ARG_C_R0_ALPHA (11 << 10)3011# define R200_TXC_ARG_C_R1_COLOR (12 << 10)3012# define R200_TXC_ARG_C_R1_ALPHA (13 << 10)3013# define R200_TXC_ARG_C_R2_COLOR (14 << 10)3014# define R200_TXC_ARG_C_R2_ALPHA (15 << 10)3015# define R200_TXC_ARG_C_R3_COLOR (16 << 10)3016# define R200_TXC_ARG_C_R3_ALPHA (17 << 10)3017# define R200_TXC_ARG_C_R4_COLOR (18 << 10)3018# define R200_TXC_ARG_C_R4_ALPHA (19 << 10)3019# define R200_TXC_ARG_C_R5_COLOR (20 << 10)3020# define R200_TXC_ARG_C_R5_ALPHA (21 << 10)3021# define R200_TXC_ARG_C_TFACTOR1_COLOR (26 << 10)3022# define R200_TXC_ARG_C_TFACTOR1_ALPHA (27 << 10)3023# define R200_TXC_ARG_C_MASK (31 << 10)3024# define R200_TXC_ARG_C_SHIFT 103025# define R200_TXC_COMP_ARG_A (1 << 16)3026# define R200_TXC_COMP_ARG_A_SHIFT (16)3027# define R200_TXC_BIAS_ARG_A (1 << 17)3028# define R200_TXC_SCALE_ARG_A (1 << 18)3029# define R200_TXC_NEG_ARG_A (1 << 19)3030# define R200_TXC_COMP_ARG_B (1 << 20)3031# define R200_TXC_COMP_ARG_B_SHIFT (20)3032# define R200_TXC_BIAS_ARG_B (1 << 21)3033# define R200_TXC_SCALE_ARG_B (1 << 22)3034# define R200_TXC_NEG_ARG_B (1 << 23)3035# define R200_TXC_COMP_ARG_C (1 << 24)3036# define R200_TXC_COMP_ARG_C_SHIFT (24)3037# define R200_TXC_BIAS_ARG_C (1 << 25)3038# define R200_TXC_SCALE_ARG_C (1 << 26)3039# define R200_TXC_NEG_ARG_C (1 << 27)3040# define R200_TXC_OP_MADD (0 << 28)3041# define R200_TXC_OP_CND0 (2 << 28)3042# define R200_TXC_OP_LERP (3 << 28)3043# define R200_TXC_OP_DOT3 (4 << 28)3044# define R200_TXC_OP_DOT4 (5 << 28)3045# define R200_TXC_OP_CONDITIONAL (6 << 28)3046# define R200_TXC_OP_DOT2_ADD (7 << 28)3047# define R200_TXC_OP_MASK (7 << 28)3048#define R200_PP_TXCBLEND2_0 0x2f043049# define R200_TXC_TFACTOR_SEL_SHIFT 03050# define R200_TXC_TFACTOR_SEL_MASK 0x73051# define R200_TXC_TFACTOR1_SEL_SHIFT 43052# define R200_TXC_TFACTOR1_SEL_MASK (0x7 << 4)3053# define R200_TXC_SCALE_SHIFT 83054# define R200_TXC_SCALE_MASK (7 << 8)3055# define R200_TXC_SCALE_1X (0 << 8)3056# define R200_TXC_SCALE_2X (1 << 8)3057# define R200_TXC_SCALE_4X (2 << 8)3058# define R200_TXC_SCALE_8X (3 << 8)3059# define R200_TXC_SCALE_INV2 (5 << 8)3060# define R200_TXC_SCALE_INV4 (6 << 8)3061# define R200_TXC_SCALE_INV8 (7 << 8)3062# define R200_TXC_CLAMP_SHIFT 123063# define R200_TXC_CLAMP_MASK (3 << 12)3064# define R200_TXC_CLAMP_WRAP (0 << 12)3065# define R200_TXC_CLAMP_0_1 (1 << 12)3066# define R200_TXC_CLAMP_8_8 (2 << 12)3067# define R200_TXC_OUTPUT_REG_MASK (7 << 16)3068# define R200_TXC_OUTPUT_REG_NONE (0 << 16)3069# define R200_TXC_OUTPUT_REG_R0 (1 << 16)3070# define R200_TXC_OUTPUT_REG_R1 (2 << 16)3071# define R200_TXC_OUTPUT_REG_R2 (3 << 16)3072# define R200_TXC_OUTPUT_REG_R3 (4 << 16)3073# define R200_TXC_OUTPUT_REG_R4 (5 << 16)3074# define R200_TXC_OUTPUT_REG_R5 (6 << 16)3075# define R200_TXC_OUTPUT_MASK_MASK (7 << 20)3076# define R200_TXC_OUTPUT_MASK_RGB (0 << 20)3077# define R200_TXC_OUTPUT_MASK_RG (1 << 20)3078# define R200_TXC_OUTPUT_MASK_RB (2 << 20)3079# define R200_TXC_OUTPUT_MASK_R (3 << 20)3080# define R200_TXC_OUTPUT_MASK_GB (4 << 20)3081# define R200_TXC_OUTPUT_MASK_G (5 << 20)3082# define R200_TXC_OUTPUT_MASK_B (6 << 20)3083# define R200_TXC_OUTPUT_MASK_NONE (7 << 20)3084# define R200_TXC_REPL_NORMAL 03085# define R200_TXC_REPL_RED 13086# define R200_TXC_REPL_GREEN 23087# define R200_TXC_REPL_BLUE 33088# define R200_TXC_REPL_ARG_A_SHIFT 263089# define R200_TXC_REPL_ARG_A_MASK (3 << 26)3090# define R200_TXC_REPL_ARG_B_SHIFT 283091# define R200_TXC_REPL_ARG_B_MASK (3 << 28)3092# define R200_TXC_REPL_ARG_C_SHIFT 303093# define R200_TXC_REPL_ARG_C_MASK (3 << 30)3094#define R200_PP_TXABLEND_0 0x2f083095# define R200_TXA_ARG_A_ZERO (0)3096# define R200_TXA_ARG_A_CURRENT_ALPHA (2) /* guess */3097# define R200_TXA_ARG_A_CURRENT_BLUE (3) /* guess */3098# define R200_TXA_ARG_A_DIFFUSE_ALPHA (4)3099# define R200_TXA_ARG_A_DIFFUSE_BLUE (5)3100# define R200_TXA_ARG_A_SPECULAR_ALPHA (6)3101# define R200_TXA_ARG_A_SPECULAR_BLUE (7)3102# define R200_TXA_ARG_A_TFACTOR_ALPHA (8)3103# define R200_TXA_ARG_A_TFACTOR_BLUE (9)3104# define R200_TXA_ARG_A_R0_ALPHA (10)3105# define R200_TXA_ARG_A_R0_BLUE (11)3106# define R200_TXA_ARG_A_R1_ALPHA (12)3107# define R200_TXA_ARG_A_R1_BLUE (13)3108# define R200_TXA_ARG_A_R2_ALPHA (14)3109# define R200_TXA_ARG_A_R2_BLUE (15)3110# define R200_TXA_ARG_A_R3_ALPHA (16)3111# define R200_TXA_ARG_A_R3_BLUE (17)3112# define R200_TXA_ARG_A_R4_ALPHA (18)3113# define R200_TXA_ARG_A_R4_BLUE (19)3114# define R200_TXA_ARG_A_R5_ALPHA (20)3115# define R200_TXA_ARG_A_R5_BLUE (21)3116# define R200_TXA_ARG_A_TFACTOR1_ALPHA (26)3117# define R200_TXA_ARG_A_TFACTOR1_BLUE (27)3118# define R200_TXA_ARG_A_MASK (31 << 0)3119# define R200_TXA_ARG_A_SHIFT 03120# define R200_TXA_ARG_B_ZERO (0 << 5)3121# define R200_TXA_ARG_B_CURRENT_ALPHA (2 << 5) /* guess */3122# define R200_TXA_ARG_B_CURRENT_BLUE (3 << 5) /* guess */3123# define R200_TXA_ARG_B_DIFFUSE_ALPHA (4 << 5)3124# define R200_TXA_ARG_B_DIFFUSE_BLUE (5 << 5)3125# define R200_TXA_ARG_B_SPECULAR_ALPHA (6 << 5)3126# define R200_TXA_ARG_B_SPECULAR_BLUE (7 << 5)3127# define R200_TXA_ARG_B_TFACTOR_ALPHA (8 << 5)3128# define R200_TXA_ARG_B_TFACTOR_BLUE (9 << 5)3129# define R200_TXA_ARG_B_R0_ALPHA (10 << 5)3130# define R200_TXA_ARG_B_R0_BLUE (11 << 5)3131# define R200_TXA_ARG_B_R1_ALPHA (12 << 5)3132# define R200_TXA_ARG_B_R1_BLUE (13 << 5)3133# define R200_TXA_ARG_B_R2_ALPHA (14 << 5)3134# define R200_TXA_ARG_B_R2_BLUE (15 << 5)3135# define R200_TXA_ARG_B_R3_ALPHA (16 << 5)3136# define R200_TXA_ARG_B_R3_BLUE (17 << 5)3137# define R200_TXA_ARG_B_R4_ALPHA (18 << 5)3138# define R200_TXA_ARG_B_R4_BLUE (19 << 5)3139# define R200_TXA_ARG_B_R5_ALPHA (20 << 5)3140# define R200_TXA_ARG_B_R5_BLUE (21 << 5)3141# define R200_TXA_ARG_B_TFACTOR1_ALPHA (26 << 5)3142# define R200_TXA_ARG_B_TFACTOR1_BLUE (27 << 5)3143# define R200_TXA_ARG_B_MASK (31 << 5)3144# define R200_TXA_ARG_B_SHIFT 53145# define R200_TXA_ARG_C_ZERO (0 << 10)3146# define R200_TXA_ARG_C_CURRENT_ALPHA (2 << 10) /* guess */3147# define R200_TXA_ARG_C_CURRENT_BLUE (3 << 10) /* guess */3148# define R200_TXA_ARG_C_DIFFUSE_ALPHA (4 << 10)3149# define R200_TXA_ARG_C_DIFFUSE_BLUE (5 << 10)3150# define R200_TXA_ARG_C_SPECULAR_ALPHA (6 << 10)3151# define R200_TXA_ARG_C_SPECULAR_BLUE (7 << 10)3152# define R200_TXA_ARG_C_TFACTOR_ALPHA (8 << 10)3153# define R200_TXA_ARG_C_TFACTOR_BLUE (9 << 10)3154# define R200_TXA_ARG_C_R0_ALPHA (10 << 10)3155# define R200_TXA_ARG_C_R0_BLUE (11 << 10)3156# define R200_TXA_ARG_C_R1_ALPHA (12 << 10)3157# define R200_TXA_ARG_C_R1_BLUE (13 << 10)3158# define R200_TXA_ARG_C_R2_ALPHA (14 << 10)3159# define R200_TXA_ARG_C_R2_BLUE (15 << 10)3160# define R200_TXA_ARG_C_R3_ALPHA (16 << 10)3161# define R200_TXA_ARG_C_R3_BLUE (17 << 10)3162# define R200_TXA_ARG_C_R4_ALPHA (18 << 10)3163# define R200_TXA_ARG_C_R4_BLUE (19 << 10)3164# define R200_TXA_ARG_C_R5_ALPHA (20 << 10)3165# define R200_TXA_ARG_C_R5_BLUE (21 << 10)3166# define R200_TXA_ARG_C_TFACTOR1_ALPHA (26 << 10)3167# define R200_TXA_ARG_C_TFACTOR1_BLUE (27 << 10)3168# define R200_TXA_ARG_C_MASK (31 << 10)3169# define R200_TXA_ARG_C_SHIFT 103170# define R200_TXA_COMP_ARG_A (1 << 16)3171# define R200_TXA_COMP_ARG_A_SHIFT (16)3172# define R200_TXA_BIAS_ARG_A (1 << 17)3173# define R200_TXA_SCALE_ARG_A (1 << 18)3174# define R200_TXA_NEG_ARG_A (1 << 19)3175# define R200_TXA_COMP_ARG_B (1 << 20)3176# define R200_TXA_COMP_ARG_B_SHIFT (20)3177# define R200_TXA_BIAS_ARG_B (1 << 21)3178# define R200_TXA_SCALE_ARG_B (1 << 22)3179# define R200_TXA_NEG_ARG_B (1 << 23)3180# define R200_TXA_COMP_ARG_C (1 << 24)3181# define R200_TXA_COMP_ARG_C_SHIFT (24)3182# define R200_TXA_BIAS_ARG_C (1 << 25)3183# define R200_TXA_SCALE_ARG_C (1 << 26)3184# define R200_TXA_NEG_ARG_C (1 << 27)3185# define R200_TXA_OP_MADD (0 << 28)3186# define R200_TXA_OP_CND0 (2 << 28)3187# define R200_TXA_OP_LERP (3 << 28)3188# define R200_TXA_OP_CONDITIONAL (6 << 28)3189# define R200_TXA_OP_MASK (7 << 28)3190#define R200_PP_TXABLEND2_0 0x2f0c3191# define R200_TXA_TFACTOR_SEL_SHIFT 03192# define R200_TXA_TFACTOR_SEL_MASK 0x73193# define R200_TXA_TFACTOR1_SEL_SHIFT 43194# define R200_TXA_TFACTOR1_SEL_MASK (0x7 << 4)3195# define R200_TXA_SCALE_SHIFT 83196# define R200_TXA_SCALE_MASK (7 << 8)3197# define R200_TXA_SCALE_1X (0 << 8)3198# define R200_TXA_SCALE_2X (1 << 8)3199# define R200_TXA_SCALE_4X (2 << 8)3200# define R200_TXA_SCALE_8X (3 << 8)3201# define R200_TXA_SCALE_INV2 (5 << 8)3202# define R200_TXA_SCALE_INV4 (6 << 8)3203# define R200_TXA_SCALE_INV8 (7 << 8)3204# define R200_TXA_CLAMP_SHIFT 123205# define R200_TXA_CLAMP_MASK (3 << 12)3206# define R200_TXA_CLAMP_WRAP (0 << 12)3207# define R200_TXA_CLAMP_0_1 (1 << 12)3208# define R200_TXA_CLAMP_8_8 (2 << 12)3209# define R200_TXA_OUTPUT_REG_MASK (7 << 16)3210# define R200_TXA_OUTPUT_REG_NONE (0 << 16)3211# define R200_TXA_OUTPUT_REG_R0 (1 << 16)3212# define R200_TXA_OUTPUT_REG_R1 (2 << 16)3213# define R200_TXA_OUTPUT_REG_R2 (3 << 16)3214# define R200_TXA_OUTPUT_REG_R3 (4 << 16)3215# define R200_TXA_OUTPUT_REG_R4 (5 << 16)3216# define R200_TXA_OUTPUT_REG_R5 (6 << 16)3217# define R200_TXA_DOT_ALPHA (1 << 20)3218# define R200_TXA_REPL_NORMAL 03219# define R200_TXA_REPL_RED 13220# define R200_TXA_REPL_GREEN 23221# define R200_TXA_REPL_ARG_A_SHIFT 263222# define R200_TXA_REPL_ARG_A_MASK (3 << 26)3223# define R200_TXA_REPL_ARG_B_SHIFT 283224# define R200_TXA_REPL_ARG_B_MASK (3 << 28)3225# define R200_TXA_REPL_ARG_C_SHIFT 303226# define R200_TXA_REPL_ARG_C_MASK (3 << 30)3227 3228#define R200_SE_VTX_FMT_0 0x20883229# define R200_VTX_XY 0 /* always have xy */3230# define R200_VTX_Z0 (1<<0)3231# define R200_VTX_W0 (1<<1)3232# define R200_VTX_WEIGHT_COUNT_SHIFT (2)3233# define R200_VTX_PV_MATRIX_SEL (1<<5)3234# define R200_VTX_N0 (1<<6)3235# define R200_VTX_POINT_SIZE (1<<7)3236# define R200_VTX_DISCRETE_FOG (1<<8)3237# define R200_VTX_SHININESS_0 (1<<9)3238# define R200_VTX_SHININESS_1 (1<<10)3239# define R200_VTX_COLOR_NOT_PRESENT 03240# define R200_VTX_PK_RGBA 13241# define R200_VTX_FP_RGB 23242# define R200_VTX_FP_RGBA 33243# define R200_VTX_COLOR_MASK 33244# define R200_VTX_COLOR_0_SHIFT 113245# define R200_VTX_COLOR_1_SHIFT 133246# define R200_VTX_COLOR_2_SHIFT 153247# define R200_VTX_COLOR_3_SHIFT 173248# define R200_VTX_COLOR_4_SHIFT 193249# define R200_VTX_COLOR_5_SHIFT 213250# define R200_VTX_COLOR_6_SHIFT 233251# define R200_VTX_COLOR_7_SHIFT 253252# define R200_VTX_XY1 (1<<28)3253# define R200_VTX_Z1 (1<<29)3254# define R200_VTX_W1 (1<<30)3255# define R200_VTX_N1 (1<<31)3256#define R200_SE_VTX_FMT_1 0x208c3257# define R200_VTX_TEX0_COMP_CNT_SHIFT 03258# define R200_VTX_TEX1_COMP_CNT_SHIFT 33259# define R200_VTX_TEX2_COMP_CNT_SHIFT 63260# define R200_VTX_TEX3_COMP_CNT_SHIFT 93261# define R200_VTX_TEX4_COMP_CNT_SHIFT 123262# define R200_VTX_TEX5_COMP_CNT_SHIFT 153263 3264#define R200_SE_TCL_OUTPUT_VTX_FMT_0 0x20903265#define R200_SE_TCL_OUTPUT_VTX_FMT_1 0x20943266#define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x22503267# define R200_OUTPUT_XYZW (1<<0)3268# define R200_OUTPUT_COLOR_0 (1<<8)3269# define R200_OUTPUT_COLOR_1 (1<<9)3270# define R200_OUTPUT_TEX_0 (1<<16)3271# define R200_OUTPUT_TEX_1 (1<<17)3272# define R200_OUTPUT_TEX_2 (1<<18)3273# define R200_OUTPUT_TEX_3 (1<<19)3274# define R200_OUTPUT_TEX_4 (1<<20)3275# define R200_OUTPUT_TEX_5 (1<<21)3276# define R200_OUTPUT_TEX_MASK (0x3f<<16)3277# define R200_OUTPUT_DISCRETE_FOG (1<<24)3278# define R200_OUTPUT_PT_SIZE (1<<25)3279# define R200_FORCE_INORDER_PROC (1<<31)3280#define R200_PP_CNTL_X 0x2cc43281#define R200_PP_TXMULTI_CTL_0 0x2c1c3282#define R200_PP_TXMULTI_CTL_1 0x2c3c3283#define R200_PP_TXMULTI_CTL_2 0x2c5c3284#define R200_PP_TXMULTI_CTL_3 0x2c7c3285#define R200_PP_TXMULTI_CTL_4 0x2c9c3286#define R200_PP_TXMULTI_CTL_5 0x2cbc3287#define R200_SE_VTX_STATE_CNTL 0x21803288# define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16)3289 3290 /* Registers for CP and Microcode Engine */3291#define RADEON_CP_ME_RAM_ADDR 0x07d43292#define RADEON_CP_ME_RAM_RADDR 0x07d83293#define RADEON_CP_ME_RAM_DATAH 0x07dc3294#define RADEON_CP_ME_RAM_DATAL 0x07e03295 3296#define RADEON_CP_RB_BASE 0x07003297#define RADEON_CP_RB_CNTL 0x07043298# define RADEON_RB_BUFSZ_SHIFT 03299# define RADEON_RB_BUFSZ_MASK (0x3f << 0)3300# define RADEON_RB_BLKSZ_SHIFT 83301# define RADEON_RB_BLKSZ_MASK (0x3f << 8)3302# define RADEON_BUF_SWAP_32BIT (2 << 16)3303# define RADEON_MAX_FETCH_SHIFT 183304# define RADEON_MAX_FETCH_MASK (0x3 << 18)3305# define RADEON_RB_NO_UPDATE (1 << 27)3306# define RADEON_RB_RPTR_WR_ENA (1 << 31)3307#define RADEON_CP_RB_RPTR_ADDR 0x070c3308#define RADEON_CP_RB_RPTR 0x07103309#define RADEON_CP_RB_WPTR 0x07143310#define RADEON_CP_RB_RPTR_WR 0x071c3311 3312#define RADEON_SCRATCH_UMSK 0x07703313#define RADEON_SCRATCH_ADDR 0x07743314 3315#define R600_CP_RB_BASE 0xc1003316#define R600_CP_RB_CNTL 0xc1043317# define R600_RB_BUFSZ(x) ((x) << 0)3318# define R600_RB_BLKSZ(x) ((x) << 8)3319# define R600_RB_NO_UPDATE (1 << 27)3320# define R600_RB_RPTR_WR_ENA (1 << 31)3321#define R600_CP_RB_RPTR_WR 0xc1083322#define R600_CP_RB_RPTR_ADDR 0xc10c3323#define R600_CP_RB_RPTR_ADDR_HI 0xc1103324#define R600_CP_RB_WPTR 0xc1143325#define R600_CP_RB_WPTR_ADDR 0xc1183326#define R600_CP_RB_WPTR_ADDR_HI 0xc11c3327#define R600_CP_RB_RPTR 0x87003328#define R600_CP_RB_WPTR_DELAY 0x87043329 3330#define RADEON_CP_IB_BASE 0x07383331#define RADEON_CP_IB_BUFSZ 0x073c3332 3333#define RADEON_CP_CSQ_CNTL 0x07403334# define RADEON_CSQ_CNT_PRIMARY_MASK (0xff << 0)3335# define RADEON_CSQ_PRIDIS_INDDIS (0 << 28)3336# define RADEON_CSQ_PRIPIO_INDDIS (1 << 28)3337# define RADEON_CSQ_PRIBM_INDDIS (2 << 28)3338# define RADEON_CSQ_PRIPIO_INDBM (3 << 28)3339# define RADEON_CSQ_PRIBM_INDBM (4 << 28)3340# define RADEON_CSQ_PRIPIO_INDPIO (15 << 28)3341 3342#define R300_CP_RESYNC_ADDR 0x7783343#define R300_CP_RESYNC_DATA 0x77c3344 3345#define RADEON_CP_CSQ_STAT 0x07f83346# define RADEON_CSQ_RPTR_PRIMARY_MASK (0xff << 0)3347# define RADEON_CSQ_WPTR_PRIMARY_MASK (0xff << 8)3348# define RADEON_CSQ_RPTR_INDIRECT_MASK (0xff << 16)3349# define RADEON_CSQ_WPTR_INDIRECT_MASK (0xff << 24)3350#define RADEON_CP_CSQ2_STAT 0x07fc3351#define RADEON_CP_CSQ_ADDR 0x07f03352#define RADEON_CP_CSQ_DATA 0x07f43353#define RADEON_CP_CSQ_APER_PRIMARY 0x10003354#define RADEON_CP_CSQ_APER_INDIRECT 0x13003355 3356#define RADEON_CP_RB_WPTR_DELAY 0x07183357# define RADEON_PRE_WRITE_TIMER_SHIFT 03358# define RADEON_PRE_WRITE_LIMIT_SHIFT 233359#define RADEON_CP_CSQ_MODE 0x07443360# define RADEON_INDIRECT2_START_SHIFT 03361# define RADEON_INDIRECT2_START_MASK (0x7f << 0)3362# define RADEON_INDIRECT1_START_SHIFT 83363# define RADEON_INDIRECT1_START_MASK (0x7f << 8)3364 3365#define RADEON_AIC_CNTL 0x01d03366# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)3367# define RADEON_DIS_OUT_OF_PCI_GART_ACCESS (1 << 1)3368# define RS400_MSI_REARM (1 << 3) /* rs400/rs480 */3369#define RADEON_AIC_LO_ADDR 0x01dc3370#define RADEON_AIC_PT_BASE 0x01d83371#define RADEON_AIC_HI_ADDR 0x01e03372 3373 3374 3375 /* Constants */3376/* #define RADEON_LAST_FRAME_REG RADEON_GUI_SCRATCH_REG0 */3377/* efine RADEON_LAST_CLEAR_REG RADEON_GUI_SCRATCH_REG2 */3378 3379 3380 3381 /* CP packet types */3382#define RADEON_CP_PACKET0 0x000000003383#define RADEON_CP_PACKET1 0x400000003384#define RADEON_CP_PACKET2 0x800000003385#define RADEON_CP_PACKET3 0xC00000003386# define RADEON_CP_PACKET_MASK 0xC00000003387# define RADEON_CP_PACKET_COUNT_MASK 0x3fff00003388# define RADEON_CP_PACKET_MAX_DWORDS (1 << 12)3389# define RADEON_CP_PACKET0_REG_MASK 0x000007ff3390# define R300_CP_PACKET0_REG_MASK 0x00001fff3391# define R600_CP_PACKET0_REG_MASK 0x0000ffff3392# define RADEON_CP_PACKET1_REG0_MASK 0x000007ff3393# define RADEON_CP_PACKET1_REG1_MASK 0x003ff8003394 3395#define RADEON_CP_PACKET0_ONE_REG_WR 0x000080003396 3397#define RADEON_CP_PACKET3_NOP 0xC00010003398#define RADEON_CP_PACKET3_NEXT_CHAR 0xC00019003399#define RADEON_CP_PACKET3_PLY_NEXTSCAN 0xC0001D003400#define RADEON_CP_PACKET3_SET_SCISSORS 0xC0001E003401#define RADEON_CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC00023003402#define RADEON_CP_PACKET3_LOAD_MICROCODE 0xC00024003403#define RADEON_CP_PACKET3_WAIT_FOR_IDLE 0xC00026003404#define RADEON_CP_PACKET3_3D_DRAW_VBUF 0xC00028003405#define RADEON_CP_PACKET3_3D_DRAW_IMMD 0xC00029003406#define RADEON_CP_PACKET3_3D_DRAW_INDX 0xC0002A003407#define RADEON_CP_PACKET3_LOAD_PALETTE 0xC0002C003408#define R200_CP_PACKET3_3D_DRAW_IMMD_2 0xc00035003409#define RADEON_CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F003410#define RADEON_CP_PACKET3_CNTL_PAINT 0xC00091003411#define RADEON_CP_PACKET3_CNTL_BITBLT 0xC00092003412#define RADEON_CP_PACKET3_CNTL_SMALLTEXT 0xC00093003413#define RADEON_CP_PACKET3_CNTL_HOSTDATA_BLT 0xC00094003414#define RADEON_CP_PACKET3_CNTL_POLYLINE 0xC00095003415#define RADEON_CP_PACKET3_CNTL_POLYSCANLINES 0xC00098003416#define RADEON_CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A003417#define RADEON_CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B003418#define RADEON_CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C003419 3420 3421#define RADEON_CP_VC_FRMT_XY 0x000000003422#define RADEON_CP_VC_FRMT_W0 0x000000013423#define RADEON_CP_VC_FRMT_FPCOLOR 0x000000023424#define RADEON_CP_VC_FRMT_FPALPHA 0x000000043425#define RADEON_CP_VC_FRMT_PKCOLOR 0x000000083426#define RADEON_CP_VC_FRMT_FPSPEC 0x000000103427#define RADEON_CP_VC_FRMT_FPFOG 0x000000203428#define RADEON_CP_VC_FRMT_PKSPEC 0x000000403429#define RADEON_CP_VC_FRMT_ST0 0x000000803430#define RADEON_CP_VC_FRMT_ST1 0x000001003431#define RADEON_CP_VC_FRMT_Q1 0x000002003432#define RADEON_CP_VC_FRMT_ST2 0x000004003433#define RADEON_CP_VC_FRMT_Q2 0x000008003434#define RADEON_CP_VC_FRMT_ST3 0x000010003435#define RADEON_CP_VC_FRMT_Q3 0x000020003436#define RADEON_CP_VC_FRMT_Q0 0x000040003437#define RADEON_CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x000380003438#define RADEON_CP_VC_FRMT_N0 0x000400003439#define RADEON_CP_VC_FRMT_XY1 0x080000003440#define RADEON_CP_VC_FRMT_Z1 0x100000003441#define RADEON_CP_VC_FRMT_W1 0x200000003442#define RADEON_CP_VC_FRMT_N1 0x400000003443#define RADEON_CP_VC_FRMT_Z 0x800000003444 3445#define RADEON_CP_VC_CNTL_PRIM_TYPE_NONE 0x000000003446#define RADEON_CP_VC_CNTL_PRIM_TYPE_POINT 0x000000013447#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE 0x000000023448#define RADEON_CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x000000033449#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x000000043450#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x000000053451#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x000000063452#define RADEON_CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x000000073453#define RADEON_CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x000000083454#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x000000093455#define RADEON_CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a3456#define RADEON_CP_VC_CNTL_PRIM_WALK_IND 0x000000103457#define RADEON_CP_VC_CNTL_PRIM_WALK_LIST 0x000000203458#define RADEON_CP_VC_CNTL_PRIM_WALK_RING 0x000000303459#define RADEON_CP_VC_CNTL_COLOR_ORDER_BGRA 0x000000003460#define RADEON_CP_VC_CNTL_COLOR_ORDER_RGBA 0x000000403461#define RADEON_CP_VC_CNTL_MAOS_ENABLE 0x000000803462#define RADEON_CP_VC_CNTL_VTX_FMT_NON_RADEON_MODE 0x000000003463#define RADEON_CP_VC_CNTL_VTX_FMT_RADEON_MODE 0x000001003464#define RADEON_CP_VC_CNTL_TCL_DISABLE 0x000000003465#define RADEON_CP_VC_CNTL_TCL_ENABLE 0x000002003466#define RADEON_CP_VC_CNTL_NUM_SHIFT 163467 3468#define RADEON_VS_MATRIX_0_ADDR 03469#define RADEON_VS_MATRIX_1_ADDR 43470#define RADEON_VS_MATRIX_2_ADDR 83471#define RADEON_VS_MATRIX_3_ADDR 123472#define RADEON_VS_MATRIX_4_ADDR 163473#define RADEON_VS_MATRIX_5_ADDR 203474#define RADEON_VS_MATRIX_6_ADDR 243475#define RADEON_VS_MATRIX_7_ADDR 283476#define RADEON_VS_MATRIX_8_ADDR 323477#define RADEON_VS_MATRIX_9_ADDR 363478#define RADEON_VS_MATRIX_10_ADDR 403479#define RADEON_VS_MATRIX_11_ADDR 443480#define RADEON_VS_MATRIX_12_ADDR 483481#define RADEON_VS_MATRIX_13_ADDR 523482#define RADEON_VS_MATRIX_14_ADDR 563483#define RADEON_VS_MATRIX_15_ADDR 603484#define RADEON_VS_LIGHT_AMBIENT_ADDR 643485#define RADEON_VS_LIGHT_DIFFUSE_ADDR 723486#define RADEON_VS_LIGHT_SPECULAR_ADDR 803487#define RADEON_VS_LIGHT_DIRPOS_ADDR 883488#define RADEON_VS_LIGHT_HWVSPOT_ADDR 963489#define RADEON_VS_LIGHT_ATTENUATION_ADDR 1043490#define RADEON_VS_MATRIX_EYE2CLIP_ADDR 1123491#define RADEON_VS_UCP_ADDR 1163492#define RADEON_VS_GLOBAL_AMBIENT_ADDR 1223493#define RADEON_VS_FOG_PARAM_ADDR 1233494#define RADEON_VS_EYE_VECTOR_ADDR 1243495 3496#define RADEON_SS_LIGHT_DCD_ADDR 03497#define RADEON_SS_LIGHT_SPOT_EXPONENT_ADDR 83498#define RADEON_SS_LIGHT_SPOT_CUTOFF_ADDR 163499#define RADEON_SS_LIGHT_SPECULAR_THRESH_ADDR 243500#define RADEON_SS_LIGHT_RANGE_CUTOFF_ADDR 323501#define RADEON_SS_VERT_GUARD_CLIP_ADJ_ADDR 483502#define RADEON_SS_VERT_GUARD_DISCARD_ADJ_ADDR 493503#define RADEON_SS_HORZ_GUARD_CLIP_ADJ_ADDR 503504#define RADEON_SS_HORZ_GUARD_DISCARD_ADJ_ADDR 513505#define RADEON_SS_SHININESS 603506 3507#define RADEON_TV_MASTER_CNTL 0x08003508# define RADEON_TV_ASYNC_RST (1 << 0)3509# define RADEON_CRT_ASYNC_RST (1 << 1)3510# define RADEON_RESTART_PHASE_FIX (1 << 3)3511# define RADEON_TV_FIFO_ASYNC_RST (1 << 4)3512# define RADEON_VIN_ASYNC_RST (1 << 5)3513# define RADEON_AUD_ASYNC_RST (1 << 6)3514# define RADEON_DVS_ASYNC_RST (1 << 7)3515# define RADEON_CRT_FIFO_CE_EN (1 << 9)3516# define RADEON_TV_FIFO_CE_EN (1 << 10)3517# define RADEON_RE_SYNC_NOW_SEL_MASK (3 << 14)3518# define RADEON_TVCLK_ALWAYS_ONb (1 << 30)3519# define RADEON_TV_ON (1 << 31)3520#define RADEON_TV_PRE_DAC_MUX_CNTL 0x08883521# define RADEON_Y_RED_EN (1 << 0)3522# define RADEON_C_GRN_EN (1 << 1)3523# define RADEON_CMP_BLU_EN (1 << 2)3524# define RADEON_DAC_DITHER_EN (1 << 3)3525# define RADEON_RED_MX_FORCE_DAC_DATA (6 << 4)3526# define RADEON_GRN_MX_FORCE_DAC_DATA (6 << 8)3527# define RADEON_BLU_MX_FORCE_DAC_DATA (6 << 12)3528# define RADEON_TV_FORCE_DAC_DATA_SHIFT 163529#define RADEON_TV_RGB_CNTL 0x08043530# define RADEON_SWITCH_TO_BLUE (1 << 4)3531# define RADEON_RGB_DITHER_EN (1 << 5)3532# define RADEON_RGB_SRC_SEL_MASK (3 << 8)3533# define RADEON_RGB_SRC_SEL_CRTC1 (0 << 8)3534# define RADEON_RGB_SRC_SEL_RMX (1 << 8)3535# define RADEON_RGB_SRC_SEL_CRTC2 (2 << 8)3536# define RADEON_RGB_CONVERT_BY_PASS (1 << 10)3537# define RADEON_UVRAM_READ_MARGIN_SHIFT 163538# define RADEON_FIFORAM_FFMACRO_READ_MARGIN_SHIFT 203539# define RADEON_RGB_ATTEN_SEL(x) ((x) << 24)3540# define RADEON_TVOUT_SCALE_EN (1 << 26)3541# define RADEON_RGB_ATTEN_VAL(x) ((x) << 28)3542#define RADEON_TV_SYNC_CNTL 0x08083543# define RADEON_SYNC_OE (1 << 0)3544# define RADEON_SYNC_OUT (1 << 1)3545# define RADEON_SYNC_IN (1 << 2)3546# define RADEON_SYNC_PUB (1 << 3)3547# define RADEON_SYNC_PD (1 << 4)3548# define RADEON_TV_SYNC_IO_DRIVE (1 << 5)3549#define RADEON_TV_HTOTAL 0x080c3550#define RADEON_TV_HDISP 0x08103551#define RADEON_TV_HSTART 0x08183552#define RADEON_TV_HCOUNT 0x081C3553#define RADEON_TV_VTOTAL 0x08203554#define RADEON_TV_VDISP 0x08243555#define RADEON_TV_VCOUNT 0x08283556#define RADEON_TV_FTOTAL 0x082c3557#define RADEON_TV_FCOUNT 0x08303558#define RADEON_TV_FRESTART 0x08343559#define RADEON_TV_HRESTART 0x08383560#define RADEON_TV_VRESTART 0x083c3561#define RADEON_TV_HOST_READ_DATA 0x08403562#define RADEON_TV_HOST_WRITE_DATA 0x08443563#define RADEON_TV_HOST_RD_WT_CNTL 0x08483564# define RADEON_HOST_FIFO_RD (1 << 12)3565# define RADEON_HOST_FIFO_RD_ACK (1 << 13)3566# define RADEON_HOST_FIFO_WT (1 << 14)3567# define RADEON_HOST_FIFO_WT_ACK (1 << 15)3568#define RADEON_TV_VSCALER_CNTL1 0x084c3569# define RADEON_UV_INC_MASK 0xffff3570# define RADEON_UV_INC_SHIFT 03571# define RADEON_Y_W_EN (1 << 24)3572# define RADEON_RESTART_FIELD (1 << 29) /* restart on field 0 */3573# define RADEON_Y_DEL_W_SIG_SHIFT 263574#define RADEON_TV_TIMING_CNTL 0x08503575# define RADEON_H_INC_MASK 0xfff3576# define RADEON_H_INC_SHIFT 03577# define RADEON_REQ_Y_FIRST (1 << 19)3578# define RADEON_FORCE_BURST_ALWAYS (1 << 21)3579# define RADEON_UV_POST_SCALE_BYPASS (1 << 23)3580# define RADEON_UV_OUTPUT_POST_SCALE_SHIFT 243581#define RADEON_TV_VSCALER_CNTL2 0x08543582# define RADEON_DITHER_MODE (1 << 0)3583# define RADEON_Y_OUTPUT_DITHER_EN (1 << 1)3584# define RADEON_UV_OUTPUT_DITHER_EN (1 << 2)3585# define RADEON_UV_TO_BUF_DITHER_EN (1 << 3)3586#define RADEON_TV_Y_FALL_CNTL 0x08583587# define RADEON_Y_FALL_PING_PONG (1 << 16)3588# define RADEON_Y_COEF_EN (1 << 17)3589#define RADEON_TV_Y_RISE_CNTL 0x085c3590# define RADEON_Y_RISE_PING_PONG (1 << 16)3591#define RADEON_TV_Y_SAW_TOOTH_CNTL 0x08603592#define RADEON_TV_UPSAMP_AND_GAIN_CNTL 0x08643593# define RADEON_YUPSAMP_EN (1 << 0)3594# define RADEON_UVUPSAMP_EN (1 << 2)3595#define RADEON_TV_GAIN_LIMIT_SETTINGS 0x08683596# define RADEON_Y_GAIN_LIMIT_SHIFT 03597# define RADEON_UV_GAIN_LIMIT_SHIFT 163598#define RADEON_TV_LINEAR_GAIN_SETTINGS 0x086c3599# define RADEON_Y_GAIN_SHIFT 03600# define RADEON_UV_GAIN_SHIFT 163601#define RADEON_TV_MODULATOR_CNTL1 0x08703602# define RADEON_YFLT_EN (1 << 2)3603# define RADEON_UVFLT_EN (1 << 3)3604# define RADEON_ALT_PHASE_EN (1 << 6)3605# define RADEON_SYNC_TIP_LEVEL (1 << 7)3606# define RADEON_BLANK_LEVEL_SHIFT 83607# define RADEON_SET_UP_LEVEL_SHIFT 163608# define RADEON_SLEW_RATE_LIMIT (1 << 23)3609# define RADEON_CY_FILT_BLEND_SHIFT 283610#define RADEON_TV_MODULATOR_CNTL2 0x08743611# define RADEON_TV_U_BURST_LEVEL_MASK 0x1ff3612# define RADEON_TV_V_BURST_LEVEL_MASK 0x1ff3613# define RADEON_TV_V_BURST_LEVEL_SHIFT 163614#define RADEON_TV_CRC_CNTL 0x08903615#define RADEON_TV_UV_ADR 0x08ac3616# define RADEON_MAX_UV_ADR_MASK 0x000000ff3617# define RADEON_MAX_UV_ADR_SHIFT 03618# define RADEON_TABLE1_BOT_ADR_MASK 0x0000ff003619# define RADEON_TABLE1_BOT_ADR_SHIFT 83620# define RADEON_TABLE3_TOP_ADR_MASK 0x00ff00003621# define RADEON_TABLE3_TOP_ADR_SHIFT 163622# define RADEON_HCODE_TABLE_SEL_MASK 0x060000003623# define RADEON_HCODE_TABLE_SEL_SHIFT 253624# define RADEON_VCODE_TABLE_SEL_MASK 0x180000003625# define RADEON_VCODE_TABLE_SEL_SHIFT 273626# define RADEON_TV_MAX_FIFO_ADDR 0x1a73627# define RADEON_TV_MAX_FIFO_ADDR_INTERNAL 0x1ff3628#define RADEON_TV_PLL_FINE_CNTL 0x0020 /* PLL */3629#define RADEON_TV_PLL_CNTL 0x0021 /* PLL */3630# define RADEON_TV_M0LO_MASK 0xff3631# define RADEON_TV_M0HI_MASK 0x73632# define RADEON_TV_M0HI_SHIFT 183633# define RADEON_TV_N0LO_MASK 0x1ff3634# define RADEON_TV_N0LO_SHIFT 83635# define RADEON_TV_N0HI_MASK 0x33636# define RADEON_TV_N0HI_SHIFT 213637# define RADEON_TV_P_MASK 0xf3638# define RADEON_TV_P_SHIFT 243639# define RADEON_TV_SLIP_EN (1 << 23)3640# define RADEON_TV_DTO_EN (1 << 28)3641#define RADEON_TV_PLL_CNTL1 0x0022 /* PLL */3642# define RADEON_TVPLL_RESET (1 << 1)3643# define RADEON_TVPLL_SLEEP (1 << 3)3644# define RADEON_TVPLL_REFCLK_SEL (1 << 4)3645# define RADEON_TVPCP_SHIFT 83646# define RADEON_TVPCP_MASK (7 << 8)3647# define RADEON_TVPVG_SHIFT 113648# define RADEON_TVPVG_MASK (7 << 11)3649# define RADEON_TVPDC_SHIFT 143650# define RADEON_TVPDC_MASK (3 << 14)3651# define RADEON_TVPLL_TEST_DIS (1 << 31)3652# define RADEON_TVCLK_SRC_SEL_TVPLL (1 << 30)3653 3654#define RS400_DISP2_REQ_CNTL1 0xe303655# define RS400_DISP2_START_REQ_LEVEL_SHIFT 03656# define RS400_DISP2_START_REQ_LEVEL_MASK 0x3ff3657# define RS400_DISP2_STOP_REQ_LEVEL_SHIFT 123658# define RS400_DISP2_STOP_REQ_LEVEL_MASK 0x3ff3659# define RS400_DISP2_ALLOW_FID_LEVEL_SHIFT 223660# define RS400_DISP2_ALLOW_FID_LEVEL_MASK 0x3ff3661#define RS400_DISP2_REQ_CNTL2 0xe343662# define RS400_DISP2_CRITICAL_POINT_START_SHIFT 123663# define RS400_DISP2_CRITICAL_POINT_START_MASK 0x3ff3664# define RS400_DISP2_CRITICAL_POINT_STOP_SHIFT 223665# define RS400_DISP2_CRITICAL_POINT_STOP_MASK 0x3ff3666#define RS400_DMIF_MEM_CNTL1 0xe383667# define RS400_DISP2_START_ADR_SHIFT 03668# define RS400_DISP2_START_ADR_MASK 0x3ff3669# define RS400_DISP1_CRITICAL_POINT_START_SHIFT 123670# define RS400_DISP1_CRITICAL_POINT_START_MASK 0x3ff3671# define RS400_DISP1_CRITICAL_POINT_STOP_SHIFT 223672# define RS400_DISP1_CRITICAL_POINT_STOP_MASK 0x3ff3673#define RS400_DISP1_REQ_CNTL1 0xe3c3674# define RS400_DISP1_START_REQ_LEVEL_SHIFT 03675# define RS400_DISP1_START_REQ_LEVEL_MASK 0x3ff3676# define RS400_DISP1_STOP_REQ_LEVEL_SHIFT 123677# define RS400_DISP1_STOP_REQ_LEVEL_MASK 0x3ff3678# define RS400_DISP1_ALLOW_FID_LEVEL_SHIFT 223679# define RS400_DISP1_ALLOW_FID_LEVEL_MASK 0x3ff3680 3681#define RADEON_PCIE_INDEX 0x00303682#define RADEON_PCIE_DATA 0x00343683#define RADEON_PCIE_TX_GART_CNTL 0x103684# define RADEON_PCIE_TX_GART_EN (1 << 0)3685# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1)3686# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1)3687# define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1)3688# define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3)3689# define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3)3690# define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5)3691# define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8)3692#define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x113693#define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x123694#define RADEON_PCIE_TX_GART_BASE 0x133695#define RADEON_PCIE_TX_GART_START_LO 0x143696#define RADEON_PCIE_TX_GART_START_HI 0x153697#define RADEON_PCIE_TX_GART_END_LO 0x163698#define RADEON_PCIE_TX_GART_END_HI 0x173699#define RADEON_PCIE_TX_GART_ERROR 0x183700 3701#define RADEON_SCRATCH_REG0 0x15e03702#define RADEON_SCRATCH_REG1 0x15e43703#define RADEON_SCRATCH_REG2 0x15e83704#define RADEON_SCRATCH_REG3 0x15ec3705#define RADEON_SCRATCH_REG4 0x15f03706#define RADEON_SCRATCH_REG5 0x15f43707 3708#define RV530_GB_PIPE_SELECT2 0x41243709 3710#define RADEON_CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)3711#define RADEON_CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)3712#define RADEON_CP_PACKET0_GET_ONE_REG_WR(h) (((h) >> 15) & 1)3713#define RADEON_CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)3714#define R100_CP_PACKET0_GET_REG(h) (((h) & 0x1FFF) << 2)3715#define R600_CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)3716#define RADEON_PACKET_TYPE0 03717#define RADEON_PACKET_TYPE1 13718#define RADEON_PACKET_TYPE2 23719#define RADEON_PACKET_TYPE3 33720 3721#define RADEON_PACKET3_NOP 0x103722 3723#define RADEON_VLINE_STAT (1 << 12)3724 3725#endif3726