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1/*2 * Copyright 2008 Advanced Micro Devices, Inc.3 * Copyright 2008 Red Hat Inc.4 * Copyright 2009 Jerome Glisse.5 *6 * Permission is hereby granted, free of charge, to any person obtaining a7 * copy of this software and associated documentation files (the "Software"),8 * to deal in the Software without restriction, including without limitation9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,10 * and/or sell copies of the Software, and to permit persons to whom the11 * Software is furnished to do so, subject to the following conditions:12 *13 * The above copyright notice and this permission notice shall be included in14 * all copies or substantial portions of the Software.15 *16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR22 * OTHER DEALINGS IN THE SOFTWARE.23 *24 * Authors: Dave Airlie25 * Alex Deucher26 * Jerome Glisse27 * Christian König28 */29 30#include <linux/debugfs.h>31 32#include <drm/drm_device.h>33#include <drm/drm_file.h>34 35#include "radeon.h"36 37/*38 * Rings39 * Most engines on the GPU are fed via ring buffers. Ring40 * buffers are areas of GPU accessible memory that the host41 * writes commands into and the GPU reads commands out of.42 * There is a rptr (read pointer) that determines where the43 * GPU is currently reading, and a wptr (write pointer)44 * which determines where the host has written. When the45 * pointers are equal, the ring is idle. When the host46 * writes commands to the ring buffer, it increments the47 * wptr. The GPU then starts fetching commands and executes48 * them until the pointers are equal again.49 */50static void radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring);51 52/**53 * radeon_ring_supports_scratch_reg - check if the ring supports54 * writing to scratch registers55 *56 * @rdev: radeon_device pointer57 * @ring: radeon_ring structure holding ring information58 *59 * Check if a specific ring supports writing to scratch registers (all asics).60 * Returns true if the ring supports writing to scratch regs, false if not.61 */62bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev,63 struct radeon_ring *ring)64{65 switch (ring->idx) {66 case RADEON_RING_TYPE_GFX_INDEX:67 case CAYMAN_RING_TYPE_CP1_INDEX:68 case CAYMAN_RING_TYPE_CP2_INDEX:69 return true;70 default:71 return false;72 }73}74 75/**76 * radeon_ring_free_size - update the free size77 *78 * @rdev: radeon_device pointer79 * @ring: radeon_ring structure holding ring information80 *81 * Update the free dw slots in the ring buffer (all asics).82 */83void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)84{85 uint32_t rptr = radeon_ring_get_rptr(rdev, ring);86 87 /* This works because ring_size is a power of 2 */88 ring->ring_free_dw = rptr + (ring->ring_size / 4);89 ring->ring_free_dw -= ring->wptr;90 ring->ring_free_dw &= ring->ptr_mask;91 if (!ring->ring_free_dw) {92 /* this is an empty ring */93 ring->ring_free_dw = ring->ring_size / 4;94 /* update lockup info to avoid false positive */95 radeon_ring_lockup_update(rdev, ring);96 }97}98 99/**100 * radeon_ring_alloc - allocate space on the ring buffer101 *102 * @rdev: radeon_device pointer103 * @ring: radeon_ring structure holding ring information104 * @ndw: number of dwords to allocate in the ring buffer105 *106 * Allocate @ndw dwords in the ring buffer (all asics).107 * Returns 0 on success, error on failure.108 */109int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)110{111 int r;112 113 /* make sure we aren't trying to allocate more space than there is on the ring */114 if (ndw > (ring->ring_size / 4))115 return -ENOMEM;116 /* Align requested size with padding so unlock_commit can117 * pad safely */118 radeon_ring_free_size(rdev, ring);119 ndw = (ndw + ring->align_mask) & ~ring->align_mask;120 while (ndw > (ring->ring_free_dw - 1)) {121 radeon_ring_free_size(rdev, ring);122 if (ndw < ring->ring_free_dw) {123 break;124 }125 r = radeon_fence_wait_next(rdev, ring->idx);126 if (r)127 return r;128 }129 ring->count_dw = ndw;130 ring->wptr_old = ring->wptr;131 return 0;132}133 134/**135 * radeon_ring_lock - lock the ring and allocate space on it136 *137 * @rdev: radeon_device pointer138 * @ring: radeon_ring structure holding ring information139 * @ndw: number of dwords to allocate in the ring buffer140 *141 * Lock the ring and allocate @ndw dwords in the ring buffer142 * (all asics).143 * Returns 0 on success, error on failure.144 */145int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)146{147 int r;148 149 mutex_lock(&rdev->ring_lock);150 r = radeon_ring_alloc(rdev, ring, ndw);151 if (r) {152 mutex_unlock(&rdev->ring_lock);153 return r;154 }155 return 0;156}157 158/**159 * radeon_ring_commit - tell the GPU to execute the new160 * commands on the ring buffer161 *162 * @rdev: radeon_device pointer163 * @ring: radeon_ring structure holding ring information164 * @hdp_flush: Whether or not to perform an HDP cache flush165 *166 * Update the wptr (write pointer) to tell the GPU to167 * execute new commands on the ring buffer (all asics).168 */169void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring,170 bool hdp_flush)171{172 /* If we are emitting the HDP flush via the ring buffer, we need to173 * do it before padding.174 */175 if (hdp_flush && rdev->asic->ring[ring->idx]->hdp_flush)176 rdev->asic->ring[ring->idx]->hdp_flush(rdev, ring);177 /* We pad to match fetch size */178 while (ring->wptr & ring->align_mask) {179 radeon_ring_write(ring, ring->nop);180 }181 mb();182 /* If we are emitting the HDP flush via MMIO, we need to do it after183 * all CPU writes to VRAM finished.184 */185 if (hdp_flush && rdev->asic->mmio_hdp_flush)186 rdev->asic->mmio_hdp_flush(rdev);187 radeon_ring_set_wptr(rdev, ring);188}189 190/**191 * radeon_ring_unlock_commit - tell the GPU to execute the new192 * commands on the ring buffer and unlock it193 *194 * @rdev: radeon_device pointer195 * @ring: radeon_ring structure holding ring information196 * @hdp_flush: Whether or not to perform an HDP cache flush197 *198 * Call radeon_ring_commit() then unlock the ring (all asics).199 */200void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring,201 bool hdp_flush)202{203 radeon_ring_commit(rdev, ring, hdp_flush);204 mutex_unlock(&rdev->ring_lock);205}206 207/**208 * radeon_ring_undo - reset the wptr209 *210 * @ring: radeon_ring structure holding ring information211 *212 * Reset the driver's copy of the wptr (all asics).213 */214void radeon_ring_undo(struct radeon_ring *ring)215{216 ring->wptr = ring->wptr_old;217}218 219/**220 * radeon_ring_unlock_undo - reset the wptr and unlock the ring221 *222 * @rdev: radeon device structure223 * @ring: radeon_ring structure holding ring information224 *225 * Call radeon_ring_undo() then unlock the ring (all asics).226 */227void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring)228{229 radeon_ring_undo(ring);230 mutex_unlock(&rdev->ring_lock);231}232 233/**234 * radeon_ring_lockup_update - update lockup variables235 *236 * @rdev: radeon device structure237 * @ring: radeon_ring structure holding ring information238 *239 * Update the last rptr value and timestamp (all asics).240 */241void radeon_ring_lockup_update(struct radeon_device *rdev,242 struct radeon_ring *ring)243{244 atomic_set(&ring->last_rptr, radeon_ring_get_rptr(rdev, ring));245 atomic64_set(&ring->last_activity, jiffies_64);246}247 248/**249 * radeon_ring_test_lockup() - check if ring is lockedup by recording information250 * @rdev: radeon device structure251 * @ring: radeon_ring structure holding ring information252 *253 */254bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring)255{256 uint32_t rptr = radeon_ring_get_rptr(rdev, ring);257 uint64_t last = atomic64_read(&ring->last_activity);258 uint64_t elapsed;259 260 if (rptr != atomic_read(&ring->last_rptr)) {261 /* ring is still working, no lockup */262 radeon_ring_lockup_update(rdev, ring);263 return false;264 }265 266 elapsed = jiffies_to_msecs(jiffies_64 - last);267 if (radeon_lockup_timeout && elapsed >= radeon_lockup_timeout) {268 dev_err(rdev->dev, "ring %d stalled for more than %llumsec\n",269 ring->idx, elapsed);270 return true;271 }272 /* give a chance to the GPU ... */273 return false;274}275 276/**277 * radeon_ring_backup - Back up the content of a ring278 *279 * @rdev: radeon_device pointer280 * @ring: the ring we want to back up281 * @data: placeholder for returned commit data282 *283 * Saves all unprocessed commits from a ring, returns the number of dwords saved.284 */285unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring,286 uint32_t **data)287{288 unsigned size, ptr, i;289 290 /* just in case lock the ring */291 mutex_lock(&rdev->ring_lock);292 *data = NULL;293 294 if (ring->ring_obj == NULL) {295 mutex_unlock(&rdev->ring_lock);296 return 0;297 }298 299 /* it doesn't make sense to save anything if all fences are signaled */300 if (!radeon_fence_count_emitted(rdev, ring->idx)) {301 mutex_unlock(&rdev->ring_lock);302 return 0;303 }304 305 /* calculate the number of dw on the ring */306 if (ring->rptr_save_reg)307 ptr = RREG32(ring->rptr_save_reg);308 else if (rdev->wb.enabled)309 ptr = le32_to_cpu(*ring->next_rptr_cpu_addr);310 else {311 /* no way to read back the next rptr */312 mutex_unlock(&rdev->ring_lock);313 return 0;314 }315 316 size = ring->wptr + (ring->ring_size / 4);317 size -= ptr;318 size &= ring->ptr_mask;319 if (size == 0) {320 mutex_unlock(&rdev->ring_lock);321 return 0;322 }323 324 /* and then save the content of the ring */325 *data = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);326 if (!*data) {327 mutex_unlock(&rdev->ring_lock);328 return 0;329 }330 for (i = 0; i < size; ++i) {331 (*data)[i] = ring->ring[ptr++];332 ptr &= ring->ptr_mask;333 }334 335 mutex_unlock(&rdev->ring_lock);336 return size;337}338 339/**340 * radeon_ring_restore - append saved commands to the ring again341 *342 * @rdev: radeon_device pointer343 * @ring: ring to append commands to344 * @size: number of dwords we want to write345 * @data: saved commands346 *347 * Allocates space on the ring and restore the previously saved commands.348 */349int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,350 unsigned size, uint32_t *data)351{352 int i, r;353 354 if (!size || !data)355 return 0;356 357 /* restore the saved ring content */358 r = radeon_ring_lock(rdev, ring, size);359 if (r)360 return r;361 362 for (i = 0; i < size; ++i) {363 radeon_ring_write(ring, data[i]);364 }365 366 radeon_ring_unlock_commit(rdev, ring, false);367 kvfree(data);368 return 0;369}370 371/**372 * radeon_ring_init - init driver ring struct.373 *374 * @rdev: radeon_device pointer375 * @ring: radeon_ring structure holding ring information376 * @ring_size: size of the ring377 * @rptr_offs: offset of the rptr writeback location in the WB buffer378 * @nop: nop packet for this ring379 *380 * Initialize the driver information for the selected ring (all asics).381 * Returns 0 on success, error on failure.382 */383int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size,384 unsigned rptr_offs, u32 nop)385{386 int r;387 388 ring->ring_size = ring_size;389 ring->rptr_offs = rptr_offs;390 ring->nop = nop;391 ring->rdev = rdev;392 /* Allocate ring buffer */393 if (ring->ring_obj == NULL) {394 r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,395 RADEON_GEM_DOMAIN_GTT, 0, NULL,396 NULL, &ring->ring_obj);397 if (r) {398 dev_err(rdev->dev, "(%d) ring create failed\n", r);399 return r;400 }401 r = radeon_bo_reserve(ring->ring_obj, false);402 if (unlikely(r != 0))403 return r;404 r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT,405 &ring->gpu_addr);406 if (r) {407 radeon_bo_unreserve(ring->ring_obj);408 dev_err(rdev->dev, "(%d) ring pin failed\n", r);409 return r;410 }411 r = radeon_bo_kmap(ring->ring_obj,412 (void **)&ring->ring);413 radeon_bo_unreserve(ring->ring_obj);414 if (r) {415 dev_err(rdev->dev, "(%d) ring map failed\n", r);416 return r;417 }418 radeon_debugfs_ring_init(rdev, ring);419 }420 ring->ptr_mask = (ring->ring_size / 4) - 1;421 ring->ring_free_dw = ring->ring_size / 4;422 if (rdev->wb.enabled) {423 u32 index = RADEON_WB_RING0_NEXT_RPTR + (ring->idx * 4);424 ring->next_rptr_gpu_addr = rdev->wb.gpu_addr + index;425 ring->next_rptr_cpu_addr = &rdev->wb.wb[index/4];426 }427 radeon_ring_lockup_update(rdev, ring);428 return 0;429}430 431/**432 * radeon_ring_fini - tear down the driver ring struct.433 *434 * @rdev: radeon_device pointer435 * @ring: radeon_ring structure holding ring information436 *437 * Tear down the driver information for the selected ring (all asics).438 */439void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring)440{441 int r;442 struct radeon_bo *ring_obj;443 444 mutex_lock(&rdev->ring_lock);445 ring_obj = ring->ring_obj;446 ring->ready = false;447 ring->ring = NULL;448 ring->ring_obj = NULL;449 mutex_unlock(&rdev->ring_lock);450 451 if (ring_obj) {452 r = radeon_bo_reserve(ring_obj, false);453 if (likely(r == 0)) {454 radeon_bo_kunmap(ring_obj);455 radeon_bo_unpin(ring_obj);456 radeon_bo_unreserve(ring_obj);457 }458 radeon_bo_unref(&ring_obj);459 }460}461 462/*463 * Debugfs info464 */465#if defined(CONFIG_DEBUG_FS)466 467static int radeon_debugfs_ring_info_show(struct seq_file *m, void *unused)468{469 struct radeon_ring *ring = m->private;470 struct radeon_device *rdev = ring->rdev;471 472 uint32_t rptr, wptr, rptr_next;473 unsigned count, i, j;474 475 radeon_ring_free_size(rdev, ring);476 count = (ring->ring_size / 4) - ring->ring_free_dw;477 478 wptr = radeon_ring_get_wptr(rdev, ring);479 seq_printf(m, "wptr: 0x%08x [%5d]\n",480 wptr, wptr);481 482 rptr = radeon_ring_get_rptr(rdev, ring);483 seq_printf(m, "rptr: 0x%08x [%5d]\n",484 rptr, rptr);485 486 if (ring->rptr_save_reg) {487 rptr_next = RREG32(ring->rptr_save_reg);488 seq_printf(m, "rptr next(0x%04x): 0x%08x [%5d]\n",489 ring->rptr_save_reg, rptr_next, rptr_next);490 } else491 rptr_next = ~0;492 493 seq_printf(m, "driver's copy of the wptr: 0x%08x [%5d]\n",494 ring->wptr, ring->wptr);495 seq_printf(m, "last semaphore signal addr : 0x%016llx\n",496 ring->last_semaphore_signal_addr);497 seq_printf(m, "last semaphore wait addr : 0x%016llx\n",498 ring->last_semaphore_wait_addr);499 seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);500 seq_printf(m, "%u dwords in ring\n", count);501 502 if (!ring->ring)503 return 0;504 505 /* print 8 dw before current rptr as often it's the last executed506 * packet that is the root issue507 */508 i = (rptr + ring->ptr_mask + 1 - 32) & ring->ptr_mask;509 for (j = 0; j <= (count + 32); j++) {510 seq_printf(m, "r[%5d]=0x%08x", i, ring->ring[i]);511 if (rptr == i)512 seq_puts(m, " *");513 if (rptr_next == i)514 seq_puts(m, " #");515 seq_puts(m, "\n");516 i = (i + 1) & ring->ptr_mask;517 }518 return 0;519}520 521DEFINE_SHOW_ATTRIBUTE(radeon_debugfs_ring_info);522 523static const char *radeon_debugfs_ring_idx_to_name(uint32_t ridx)524{525 switch (ridx) {526 case RADEON_RING_TYPE_GFX_INDEX:527 return "radeon_ring_gfx";528 case CAYMAN_RING_TYPE_CP1_INDEX:529 return "radeon_ring_cp1";530 case CAYMAN_RING_TYPE_CP2_INDEX:531 return "radeon_ring_cp2";532 case R600_RING_TYPE_DMA_INDEX:533 return "radeon_ring_dma1";534 case CAYMAN_RING_TYPE_DMA1_INDEX:535 return "radeon_ring_dma2";536 case R600_RING_TYPE_UVD_INDEX:537 return "radeon_ring_uvd";538 case TN_RING_TYPE_VCE1_INDEX:539 return "radeon_ring_vce1";540 case TN_RING_TYPE_VCE2_INDEX:541 return "radeon_ring_vce2";542 default:543 return NULL;544 545 }546}547#endif548 549static void radeon_debugfs_ring_init(struct radeon_device *rdev, struct radeon_ring *ring)550{551#if defined(CONFIG_DEBUG_FS)552 const char *ring_name = radeon_debugfs_ring_idx_to_name(ring->idx);553 struct dentry *root = rdev_to_drm(rdev)->primary->debugfs_root;554 555 if (ring_name)556 debugfs_create_file(ring_name, 0444, root, ring,557 &radeon_debugfs_ring_info_fops);558 559#endif560}561