1168 lines · c
1/*2 * Copyright 2008 Advanced Micro Devices, Inc.3 * Copyright 2008 Red Hat Inc.4 * Copyright 2009 Jerome Glisse.5 *6 * Permission is hereby granted, free of charge, to any person obtaining a7 * copy of this software and associated documentation files (the "Software"),8 * to deal in the Software without restriction, including without limitation9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,10 * and/or sell copies of the Software, and to permit persons to whom the11 * Software is furnished to do so, subject to the following conditions:12 *13 * The above copyright notice and this permission notice shall be included in14 * all copies or substantial portions of the Software.15 *16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR22 * OTHER DEALINGS IN THE SOFTWARE.23 *24 * Authors: Dave Airlie25 * Alex Deucher26 * Jerome Glisse27 */28/* RS600 / Radeon X1250/X1270 integrated GPU29 *30 * This file gather function specific to RS600 which is the IGP of31 * the X1250/X1270 family supporting intel CPU (while RS690/RS74032 * is the X1250/X1270 supporting AMD CPU). The display engine are33 * the avivo one, bios is an atombios, 3D block are the one of the34 * R4XX family. The GART is different from the RS400 one and is very35 * close to the one of the R600 family (R600 likely being an evolution36 * of the RS600 GART block).37 */38 39#include <linux/io-64-nonatomic-lo-hi.h>40#include <linux/pci.h>41 42#include <drm/drm_device.h>43#include <drm/drm_vblank.h>44#include <drm/drm_fourcc.h>45#include <drm/drm_framebuffer.h>46 47#include "atom.h"48#include "radeon.h"49#include "radeon_asic.h"50#include "radeon_audio.h"51#include "rs600_reg_safe.h"52#include "rs600d.h"53 54static void rs600_gpu_init(struct radeon_device *rdev);55int rs600_mc_wait_for_idle(struct radeon_device *rdev);56 57static const u32 crtc_offsets[2] = {58 0,59 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL60};61 62static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc)63{64 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK)65 return true;66 else67 return false;68}69 70static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc)71{72 u32 pos1, pos2;73 74 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);75 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]);76 77 if (pos1 != pos2)78 return true;79 else80 return false;81}82 83/**84 * avivo_wait_for_vblank - vblank wait asic callback.85 *86 * @rdev: radeon_device pointer87 * @crtc: crtc to wait for vblank on88 *89 * Wait for vblank on the requested crtc (r5xx-r7xx).90 */91void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc)92{93 unsigned i = 0;94 95 if (crtc >= rdev->num_crtc)96 return;97 98 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN))99 return;100 101 /* depending on when we hit vblank, we may be close to active; if so,102 * wait for another frame.103 */104 while (avivo_is_in_vblank(rdev, crtc)) {105 if (i++ % 100 == 0) {106 if (!avivo_is_counter_moving(rdev, crtc))107 break;108 }109 }110 111 while (!avivo_is_in_vblank(rdev, crtc)) {112 if (i++ % 100 == 0) {113 if (!avivo_is_counter_moving(rdev, crtc))114 break;115 }116 }117}118 119void rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async)120{121 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];122 struct drm_framebuffer *fb = radeon_crtc->base.primary->fb;123 u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);124 int i;125 126 /* Lock the graphics update lock */127 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;128 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);129 130 /* flip at hsync for async, default is vsync */131 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset,132 async ? AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN : 0);133 /* update pitch */134 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset,135 fb->pitches[0] / fb->format->cpp[0]);136 /* update the scanout addresses */137 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,138 (u32)crtc_base);139 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,140 (u32)crtc_base);141 142 /* Wait for update_pending to go high. */143 for (i = 0; i < rdev->usec_timeout; i++) {144 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)145 break;146 udelay(1);147 }148 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");149 150 /* Unlock the lock, so double-buffering can take place inside vblank */151 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;152 WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);153}154 155bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc_id)156{157 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];158 159 /* Return current update_pending status: */160 return !!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) &161 AVIVO_D1GRPH_SURFACE_UPDATE_PENDING);162}163 164void avivo_program_fmt(struct drm_encoder *encoder)165{166 struct drm_device *dev = encoder->dev;167 struct radeon_device *rdev = dev->dev_private;168 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);169 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);170 int bpc = 0;171 u32 tmp = 0;172 enum radeon_connector_dither dither = RADEON_FMT_DITHER_DISABLE;173 174 if (connector) {175 struct radeon_connector *radeon_connector = to_radeon_connector(connector);176 bpc = radeon_get_monitor_bpc(connector);177 dither = radeon_connector->dither;178 }179 180 /* LVDS FMT is set up by atom */181 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)182 return;183 184 if (bpc == 0)185 return;186 187 switch (bpc) {188 case 6:189 if (dither == RADEON_FMT_DITHER_ENABLE)190 /* XXX sort out optimal dither settings */191 tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;192 else193 tmp |= AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN;194 break;195 case 8:196 if (dither == RADEON_FMT_DITHER_ENABLE)197 /* XXX sort out optimal dither settings */198 tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN |199 AVIVO_TMDS_BIT_DEPTH_CONTROL_SPATIAL_DITHER_DEPTH);200 else201 tmp |= (AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_EN |202 AVIVO_TMDS_BIT_DEPTH_CONTROL_TRUNCATE_DEPTH);203 break;204 case 10:205 default:206 /* not needed */207 break;208 }209 210 switch (radeon_encoder->encoder_id) {211 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:212 WREG32(AVIVO_TMDSA_BIT_DEPTH_CONTROL, tmp);213 break;214 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:215 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, tmp);216 break;217 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:218 WREG32(AVIVO_DVOA_BIT_DEPTH_CONTROL, tmp);219 break;220 case ENCODER_OBJECT_ID_INTERNAL_DDI:221 WREG32(AVIVO_DDIA_BIT_DEPTH_CONTROL, tmp);222 break;223 default:224 break;225 }226}227 228void rs600_pm_misc(struct radeon_device *rdev)229{230 int requested_index = rdev->pm.requested_power_state_index;231 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];232 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;233 u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;234 u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl;235 236 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {237 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {238 tmp = RREG32(voltage->gpio.reg);239 if (voltage->active_high)240 tmp |= voltage->gpio.mask;241 else242 tmp &= ~(voltage->gpio.mask);243 WREG32(voltage->gpio.reg, tmp);244 if (voltage->delay)245 udelay(voltage->delay);246 } else {247 tmp = RREG32(voltage->gpio.reg);248 if (voltage->active_high)249 tmp &= ~voltage->gpio.mask;250 else251 tmp |= voltage->gpio.mask;252 WREG32(voltage->gpio.reg, tmp);253 if (voltage->delay)254 udelay(voltage->delay);255 }256 } else if (voltage->type == VOLTAGE_VDDC)257 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC);258 259 dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);260 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);261 dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf);262 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {263 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) {264 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2);265 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2);266 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) {267 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4);268 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4);269 }270 } else {271 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1);272 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1);273 }274 WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);275 276 dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);277 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {278 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP;279 if (voltage->delay) {280 dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC;281 dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay);282 } else283 dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC;284 } else285 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP;286 WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);287 288 hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);289 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)290 hdp_dyn_cntl &= ~HDP_FORCEON;291 else292 hdp_dyn_cntl |= HDP_FORCEON;293 WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);294#if 0295 /* mc_host_dyn seems to cause hangs from time to time */296 mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);297 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN)298 mc_host_dyn_cntl &= ~MC_HOST_FORCEON;299 else300 mc_host_dyn_cntl |= MC_HOST_FORCEON;301 WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);302#endif303 dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);304 if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN)305 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN;306 else307 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN;308 WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);309 310 /* set pcie lanes */311 if ((rdev->flags & RADEON_IS_PCIE) &&312 !(rdev->flags & RADEON_IS_IGP) &&313 rdev->asic->pm.set_pcie_lanes &&314 (ps->pcie_lanes !=315 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {316 radeon_set_pcie_lanes(rdev,317 ps->pcie_lanes);318 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes);319 }320}321 322void rs600_pm_prepare(struct radeon_device *rdev)323{324 struct drm_device *ddev = rdev_to_drm(rdev);325 struct drm_crtc *crtc;326 struct radeon_crtc *radeon_crtc;327 u32 tmp;328 329 /* disable any active CRTCs */330 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {331 radeon_crtc = to_radeon_crtc(crtc);332 if (radeon_crtc->enabled) {333 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);334 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;335 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);336 }337 }338}339 340void rs600_pm_finish(struct radeon_device *rdev)341{342 struct drm_device *ddev = rdev_to_drm(rdev);343 struct drm_crtc *crtc;344 struct radeon_crtc *radeon_crtc;345 u32 tmp;346 347 /* enable any active CRTCs */348 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {349 radeon_crtc = to_radeon_crtc(crtc);350 if (radeon_crtc->enabled) {351 tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);352 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;353 WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);354 }355 }356}357 358/* hpd for digital panel detect/disconnect */359bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)360{361 u32 tmp;362 bool connected = false;363 364 switch (hpd) {365 case RADEON_HPD_1:366 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);367 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))368 connected = true;369 break;370 case RADEON_HPD_2:371 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);372 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))373 connected = true;374 break;375 default:376 break;377 }378 return connected;379}380 381void rs600_hpd_set_polarity(struct radeon_device *rdev,382 enum radeon_hpd_id hpd)383{384 u32 tmp;385 bool connected = rs600_hpd_sense(rdev, hpd);386 387 switch (hpd) {388 case RADEON_HPD_1:389 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);390 if (connected)391 tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);392 else393 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);394 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);395 break;396 case RADEON_HPD_2:397 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);398 if (connected)399 tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);400 else401 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);402 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);403 break;404 default:405 break;406 }407}408 409void rs600_hpd_init(struct radeon_device *rdev)410{411 struct drm_device *dev = rdev_to_drm(rdev);412 struct drm_connector *connector;413 unsigned enable = 0;414 415 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {416 struct radeon_connector *radeon_connector = to_radeon_connector(connector);417 switch (radeon_connector->hpd.hpd) {418 case RADEON_HPD_1:419 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,420 S_007D00_DC_HOT_PLUG_DETECT1_EN(1));421 break;422 case RADEON_HPD_2:423 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,424 S_007D10_DC_HOT_PLUG_DETECT2_EN(1));425 break;426 default:427 break;428 }429 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)430 enable |= 1 << radeon_connector->hpd.hpd;431 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);432 }433 radeon_irq_kms_enable_hpd(rdev, enable);434}435 436void rs600_hpd_fini(struct radeon_device *rdev)437{438 struct drm_device *dev = rdev_to_drm(rdev);439 struct drm_connector *connector;440 unsigned disable = 0;441 442 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {443 struct radeon_connector *radeon_connector = to_radeon_connector(connector);444 switch (radeon_connector->hpd.hpd) {445 case RADEON_HPD_1:446 WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,447 S_007D00_DC_HOT_PLUG_DETECT1_EN(0));448 break;449 case RADEON_HPD_2:450 WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,451 S_007D10_DC_HOT_PLUG_DETECT2_EN(0));452 break;453 default:454 break;455 }456 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)457 disable |= 1 << radeon_connector->hpd.hpd;458 }459 radeon_irq_kms_disable_hpd(rdev, disable);460}461 462int rs600_asic_reset(struct radeon_device *rdev, bool hard)463{464 struct rv515_mc_save save;465 u32 status, tmp;466 int ret = 0;467 468 status = RREG32(R_000E40_RBBM_STATUS);469 if (!G_000E40_GUI_ACTIVE(status)) {470 return 0;471 }472 /* Stops all mc clients */473 rv515_mc_stop(rdev, &save);474 status = RREG32(R_000E40_RBBM_STATUS);475 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);476 /* stop CP */477 WREG32(RADEON_CP_CSQ_CNTL, 0);478 tmp = RREG32(RADEON_CP_RB_CNTL);479 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);480 WREG32(RADEON_CP_RB_RPTR_WR, 0);481 WREG32(RADEON_CP_RB_WPTR, 0);482 WREG32(RADEON_CP_RB_CNTL, tmp);483 pci_save_state(rdev->pdev);484 /* disable bus mastering */485 pci_clear_master(rdev->pdev);486 mdelay(1);487 /* reset GA+VAP */488 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |489 S_0000F0_SOFT_RESET_GA(1));490 RREG32(R_0000F0_RBBM_SOFT_RESET);491 mdelay(500);492 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);493 mdelay(1);494 status = RREG32(R_000E40_RBBM_STATUS);495 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);496 /* reset CP */497 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));498 RREG32(R_0000F0_RBBM_SOFT_RESET);499 mdelay(500);500 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);501 mdelay(1);502 status = RREG32(R_000E40_RBBM_STATUS);503 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);504 /* reset MC */505 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));506 RREG32(R_0000F0_RBBM_SOFT_RESET);507 mdelay(500);508 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);509 mdelay(1);510 status = RREG32(R_000E40_RBBM_STATUS);511 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);512 /* restore PCI & busmastering */513 pci_restore_state(rdev->pdev);514 /* Check if GPU is idle */515 if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {516 dev_err(rdev->dev, "failed to reset GPU\n");517 ret = -1;518 } else519 dev_info(rdev->dev, "GPU reset succeed\n");520 rv515_mc_resume(rdev, &save);521 return ret;522}523 524/*525 * GART.526 */527void rs600_gart_tlb_flush(struct radeon_device *rdev)528{529 uint32_t tmp;530 531 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);532 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;533 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);534 535 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);536 tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);537 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);538 539 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);540 tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;541 WREG32_MC(R_000100_MC_PT0_CNTL, tmp);542 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);543}544 545static int rs600_gart_init(struct radeon_device *rdev)546{547 int r;548 549 if (rdev->gart.robj) {550 WARN(1, "RS600 GART already initialized\n");551 return 0;552 }553 /* Initialize common gart structure */554 r = radeon_gart_init(rdev);555 if (r) {556 return r;557 }558 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;559 return radeon_gart_table_vram_alloc(rdev);560}561 562static int rs600_gart_enable(struct radeon_device *rdev)563{564 u32 tmp;565 int r, i;566 567 if (rdev->gart.robj == NULL) {568 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");569 return -EINVAL;570 }571 r = radeon_gart_table_vram_pin(rdev);572 if (r)573 return r;574 /* Enable bus master */575 tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;576 WREG32(RADEON_BUS_CNTL, tmp);577 /* FIXME: setup default page */578 WREG32_MC(R_000100_MC_PT0_CNTL,579 (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |580 S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));581 582 for (i = 0; i < 19; i++) {583 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,584 S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |585 S_00016C_SYSTEM_ACCESS_MODE_MASK(586 V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |587 S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(588 V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |589 S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |590 S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |591 S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));592 }593 /* enable first context */594 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,595 S_000102_ENABLE_PAGE_TABLE(1) |596 S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));597 598 /* disable all other contexts */599 for (i = 1; i < 8; i++)600 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);601 602 /* setup the page table */603 WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,604 rdev->gart.table_addr);605 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);606 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);607 WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);608 609 /* System context maps to VRAM space */610 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);611 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);612 613 /* enable page tables */614 tmp = RREG32_MC(R_000100_MC_PT0_CNTL);615 WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));616 tmp = RREG32_MC(R_000009_MC_CNTL1);617 WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));618 rs600_gart_tlb_flush(rdev);619 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",620 (unsigned)(rdev->mc.gtt_size >> 20),621 (unsigned long long)rdev->gart.table_addr);622 rdev->gart.ready = true;623 return 0;624}625 626static void rs600_gart_disable(struct radeon_device *rdev)627{628 u32 tmp;629 630 /* FIXME: disable out of gart access */631 WREG32_MC(R_000100_MC_PT0_CNTL, 0);632 tmp = RREG32_MC(R_000009_MC_CNTL1);633 WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);634 radeon_gart_table_vram_unpin(rdev);635}636 637static void rs600_gart_fini(struct radeon_device *rdev)638{639 radeon_gart_fini(rdev);640 rs600_gart_disable(rdev);641 radeon_gart_table_vram_free(rdev);642}643 644uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags)645{646 addr = addr & 0xFFFFFFFFFFFFF000ULL;647 addr |= R600_PTE_SYSTEM;648 if (flags & RADEON_GART_PAGE_VALID)649 addr |= R600_PTE_VALID;650 if (flags & RADEON_GART_PAGE_READ)651 addr |= R600_PTE_READABLE;652 if (flags & RADEON_GART_PAGE_WRITE)653 addr |= R600_PTE_WRITEABLE;654 if (flags & RADEON_GART_PAGE_SNOOP)655 addr |= R600_PTE_SNOOPED;656 return addr;657}658 659void rs600_gart_set_page(struct radeon_device *rdev, unsigned i,660 uint64_t entry)661{662 void __iomem *ptr = (void *)rdev->gart.ptr;663 writeq(entry, ptr + (i * 8));664}665 666int rs600_irq_set(struct radeon_device *rdev)667{668 uint32_t tmp = 0;669 uint32_t mode_int = 0;670 u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &671 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);672 u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &673 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);674 u32 hdmi0;675 if (ASIC_IS_DCE2(rdev))676 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &677 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);678 else679 hdmi0 = 0;680 681 if (!rdev->irq.installed) {682 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");683 WREG32(R_000040_GEN_INT_CNTL, 0);684 return -EINVAL;685 }686 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {687 tmp |= S_000040_SW_INT_EN(1);688 }689 if (rdev->irq.crtc_vblank_int[0] ||690 atomic_read(&rdev->irq.pflip[0])) {691 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);692 }693 if (rdev->irq.crtc_vblank_int[1] ||694 atomic_read(&rdev->irq.pflip[1])) {695 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);696 }697 if (rdev->irq.hpd[0]) {698 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);699 }700 if (rdev->irq.hpd[1]) {701 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);702 }703 if (rdev->irq.afmt[0]) {704 hdmi0 |= S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);705 }706 WREG32(R_000040_GEN_INT_CNTL, tmp);707 WREG32(R_006540_DxMODE_INT_MASK, mode_int);708 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);709 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);710 if (ASIC_IS_DCE2(rdev))711 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);712 713 /* posting read */714 RREG32(R_000040_GEN_INT_CNTL);715 716 return 0;717}718 719static inline u32 rs600_irq_ack(struct radeon_device *rdev)720{721 uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);722 uint32_t irq_mask = S_000044_SW_INT(1);723 u32 tmp;724 725 if (G_000044_DISPLAY_INT_STAT(irqs)) {726 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);727 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {728 WREG32(R_006534_D1MODE_VBLANK_STATUS,729 S_006534_D1MODE_VBLANK_ACK(1));730 }731 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {732 WREG32(R_006D34_D2MODE_VBLANK_STATUS,733 S_006D34_D2MODE_VBLANK_ACK(1));734 }735 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {736 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);737 tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);738 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);739 }740 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {741 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);742 tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);743 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);744 }745 } else {746 rdev->irq.stat_regs.r500.disp_int = 0;747 }748 749 if (ASIC_IS_DCE2(rdev)) {750 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) &751 S_007404_HDMI0_AZ_FORMAT_WTRIG(1);752 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {753 tmp = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL);754 tmp |= S_007408_HDMI0_AZ_FORMAT_WTRIG_ACK(1);755 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, tmp);756 }757 } else758 rdev->irq.stat_regs.r500.hdmi0_status = 0;759 760 if (irqs) {761 WREG32(R_000044_GEN_INT_STATUS, irqs);762 }763 return irqs & irq_mask;764}765 766void rs600_irq_disable(struct radeon_device *rdev)767{768 u32 hdmi0 = RREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL) &769 ~S_007408_HDMI0_AZ_FORMAT_WTRIG_MASK(1);770 WREG32(R_007408_HDMI0_AUDIO_PACKET_CONTROL, hdmi0);771 WREG32(R_000040_GEN_INT_CNTL, 0);772 WREG32(R_006540_DxMODE_INT_MASK, 0);773 /* Wait and acknowledge irq */774 mdelay(1);775 rs600_irq_ack(rdev);776}777 778int rs600_irq_process(struct radeon_device *rdev)779{780 u32 status, msi_rearm;781 bool queue_hotplug = false;782 bool queue_hdmi = false;783 784 status = rs600_irq_ack(rdev);785 if (!status &&786 !rdev->irq.stat_regs.r500.disp_int &&787 !rdev->irq.stat_regs.r500.hdmi0_status) {788 return IRQ_NONE;789 }790 while (status ||791 rdev->irq.stat_regs.r500.disp_int ||792 rdev->irq.stat_regs.r500.hdmi0_status) {793 /* SW interrupt */794 if (G_000044_SW_INT(status)) {795 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);796 }797 /* Vertical blank interrupts */798 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {799 if (rdev->irq.crtc_vblank_int[0]) {800 drm_handle_vblank(rdev_to_drm(rdev), 0);801 rdev->pm.vblank_sync = true;802 wake_up(&rdev->irq.vblank_queue);803 }804 if (atomic_read(&rdev->irq.pflip[0]))805 radeon_crtc_handle_vblank(rdev, 0);806 }807 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {808 if (rdev->irq.crtc_vblank_int[1]) {809 drm_handle_vblank(rdev_to_drm(rdev), 1);810 rdev->pm.vblank_sync = true;811 wake_up(&rdev->irq.vblank_queue);812 }813 if (atomic_read(&rdev->irq.pflip[1]))814 radeon_crtc_handle_vblank(rdev, 1);815 }816 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {817 queue_hotplug = true;818 DRM_DEBUG("HPD1\n");819 }820 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {821 queue_hotplug = true;822 DRM_DEBUG("HPD2\n");823 }824 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {825 queue_hdmi = true;826 DRM_DEBUG("HDMI0\n");827 }828 status = rs600_irq_ack(rdev);829 }830 if (queue_hotplug)831 schedule_delayed_work(&rdev->hotplug_work, 0);832 if (queue_hdmi)833 schedule_work(&rdev->audio_work);834 if (rdev->msi_enabled) {835 switch (rdev->family) {836 case CHIP_RS600:837 case CHIP_RS690:838 case CHIP_RS740:839 msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;840 WREG32(RADEON_BUS_CNTL, msi_rearm);841 WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);842 break;843 default:844 WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);845 break;846 }847 }848 return IRQ_HANDLED;849}850 851u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)852{853 if (crtc == 0)854 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);855 else856 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);857}858 859int rs600_mc_wait_for_idle(struct radeon_device *rdev)860{861 unsigned i;862 863 for (i = 0; i < rdev->usec_timeout; i++) {864 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))865 return 0;866 udelay(1);867 }868 return -1;869}870 871static void rs600_gpu_init(struct radeon_device *rdev)872{873 r420_pipes_init(rdev);874 /* Wait for mc idle */875 if (rs600_mc_wait_for_idle(rdev))876 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");877}878 879static void rs600_mc_init(struct radeon_device *rdev)880{881 u64 base;882 883 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);884 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);885 rdev->mc.vram_is_ddr = true;886 rdev->mc.vram_width = 128;887 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);888 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;889 rdev->mc.visible_vram_size = rdev->mc.aper_size;890 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);891 base = RREG32_MC(R_000004_MC_FB_LOCATION);892 base = G_000004_MC_FB_START(base) << 16;893 radeon_vram_location(rdev, &rdev->mc, base);894 rdev->mc.gtt_base_align = 0;895 radeon_gtt_location(rdev, &rdev->mc);896 radeon_update_bandwidth_info(rdev);897}898 899void rs600_bandwidth_update(struct radeon_device *rdev)900{901 struct drm_display_mode *mode0 = NULL;902 struct drm_display_mode *mode1 = NULL;903 u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;904 /* FIXME: implement full support */905 906 if (!rdev->mode_info.mode_config_initialized)907 return;908 909 radeon_update_display_priority(rdev);910 911 if (rdev->mode_info.crtcs[0]->base.enabled)912 mode0 = &rdev->mode_info.crtcs[0]->base.mode;913 if (rdev->mode_info.crtcs[1]->base.enabled)914 mode1 = &rdev->mode_info.crtcs[1]->base.mode;915 916 rs690_line_buffer_adjust(rdev, mode0, mode1);917 918 if (rdev->disp_priority == 2) {919 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);920 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);921 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);922 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);923 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);924 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);925 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);926 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);927 }928}929 930uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)931{932 unsigned long flags;933 u32 r;934 935 spin_lock_irqsave(&rdev->mc_idx_lock, flags);936 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |937 S_000070_MC_IND_CITF_ARB0(1));938 r = RREG32(R_000074_MC_IND_DATA);939 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);940 return r;941}942 943void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)944{945 unsigned long flags;946 947 spin_lock_irqsave(&rdev->mc_idx_lock, flags);948 WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |949 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));950 WREG32(R_000074_MC_IND_DATA, v);951 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);952}953 954void rs600_set_safe_registers(struct radeon_device *rdev)955{956 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;957 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);958}959 960static void rs600_mc_program(struct radeon_device *rdev)961{962 struct rv515_mc_save save;963 964 /* Stops all mc clients */965 rv515_mc_stop(rdev, &save);966 967 /* Wait for mc idle */968 if (rs600_mc_wait_for_idle(rdev))969 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");970 971 /* FIXME: What does AGP means for such chipset ? */972 WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);973 WREG32_MC(R_000006_AGP_BASE, 0);974 WREG32_MC(R_000007_AGP_BASE_2, 0);975 /* Program MC */976 WREG32_MC(R_000004_MC_FB_LOCATION,977 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |978 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));979 WREG32(R_000134_HDP_FB_LOCATION,980 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));981 982 rv515_mc_resume(rdev, &save);983}984 985static int rs600_startup(struct radeon_device *rdev)986{987 int r;988 989 rs600_mc_program(rdev);990 /* Resume clock */991 rv515_clock_startup(rdev);992 /* Initialize GPU configuration (# pipes, ...) */993 rs600_gpu_init(rdev);994 /* Initialize GART (initialize after TTM so we can allocate995 * memory through TTM but finalize after TTM) */996 r = rs600_gart_enable(rdev);997 if (r)998 return r;999 1000 /* allocate wb buffer */1001 r = radeon_wb_init(rdev);1002 if (r)1003 return r;1004 1005 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);1006 if (r) {1007 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);1008 return r;1009 }1010 1011 /* Enable IRQ */1012 if (!rdev->irq.installed) {1013 r = radeon_irq_kms_init(rdev);1014 if (r)1015 return r;1016 }1017 1018 rs600_irq_set(rdev);1019 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);1020 /* 1M ring buffer */1021 r = r100_cp_init(rdev, 1024 * 1024);1022 if (r) {1023 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);1024 return r;1025 }1026 1027 r = radeon_ib_pool_init(rdev);1028 if (r) {1029 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);1030 return r;1031 }1032 1033 r = radeon_audio_init(rdev);1034 if (r) {1035 dev_err(rdev->dev, "failed initializing audio\n");1036 return r;1037 }1038 1039 return 0;1040}1041 1042int rs600_resume(struct radeon_device *rdev)1043{1044 int r;1045 1046 /* Make sur GART are not working */1047 rs600_gart_disable(rdev);1048 /* Resume clock before doing reset */1049 rv515_clock_startup(rdev);1050 /* Reset gpu before posting otherwise ATOM will enter infinite loop */1051 if (radeon_asic_reset(rdev)) {1052 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",1053 RREG32(R_000E40_RBBM_STATUS),1054 RREG32(R_0007C0_CP_STAT));1055 }1056 /* post */1057 atom_asic_init(rdev->mode_info.atom_context);1058 /* Resume clock after posting */1059 rv515_clock_startup(rdev);1060 /* Initialize surface registers */1061 radeon_surface_init(rdev);1062 1063 rdev->accel_working = true;1064 r = rs600_startup(rdev);1065 if (r) {1066 rdev->accel_working = false;1067 }1068 return r;1069}1070 1071int rs600_suspend(struct radeon_device *rdev)1072{1073 radeon_pm_suspend(rdev);1074 radeon_audio_fini(rdev);1075 r100_cp_disable(rdev);1076 radeon_wb_disable(rdev);1077 rs600_irq_disable(rdev);1078 rs600_gart_disable(rdev);1079 return 0;1080}1081 1082void rs600_fini(struct radeon_device *rdev)1083{1084 radeon_pm_fini(rdev);1085 radeon_audio_fini(rdev);1086 r100_cp_fini(rdev);1087 radeon_wb_fini(rdev);1088 radeon_ib_pool_fini(rdev);1089 radeon_gem_fini(rdev);1090 rs600_gart_fini(rdev);1091 radeon_irq_kms_fini(rdev);1092 radeon_fence_driver_fini(rdev);1093 radeon_bo_fini(rdev);1094 radeon_atombios_fini(rdev);1095 kfree(rdev->bios);1096 rdev->bios = NULL;1097}1098 1099int rs600_init(struct radeon_device *rdev)1100{1101 int r;1102 1103 /* Disable VGA */1104 rv515_vga_render_disable(rdev);1105 /* Initialize scratch registers */1106 radeon_scratch_init(rdev);1107 /* Initialize surface registers */1108 radeon_surface_init(rdev);1109 /* restore some register to sane defaults */1110 r100_restore_sanity(rdev);1111 /* BIOS */1112 if (!radeon_get_bios(rdev)) {1113 if (ASIC_IS_AVIVO(rdev))1114 return -EINVAL;1115 }1116 if (rdev->is_atom_bios) {1117 r = radeon_atombios_init(rdev);1118 if (r)1119 return r;1120 } else {1121 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");1122 return -EINVAL;1123 }1124 /* Reset gpu before posting otherwise ATOM will enter infinite loop */1125 if (radeon_asic_reset(rdev)) {1126 dev_warn(rdev->dev,1127 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",1128 RREG32(R_000E40_RBBM_STATUS),1129 RREG32(R_0007C0_CP_STAT));1130 }1131 /* check if cards are posted or not */1132 if (radeon_boot_test_post_card(rdev) == false)1133 return -EINVAL;1134 1135 /* Initialize clocks */1136 radeon_get_clock_info(rdev_to_drm(rdev));1137 /* initialize memory controller */1138 rs600_mc_init(rdev);1139 r100_debugfs_rbbm_init(rdev);1140 /* Fence driver */1141 radeon_fence_driver_init(rdev);1142 /* Memory manager */1143 r = radeon_bo_init(rdev);1144 if (r)1145 return r;1146 r = rs600_gart_init(rdev);1147 if (r)1148 return r;1149 rs600_set_safe_registers(rdev);1150 1151 /* Initialize power management */1152 radeon_pm_init(rdev);1153 1154 rdev->accel_working = true;1155 r = rs600_startup(rdev);1156 if (r) {1157 /* Somethings want wront with the accel init stop accel */1158 dev_err(rdev->dev, "Disabling GPU acceleration\n");1159 r100_cp_fini(rdev);1160 radeon_wb_fini(rdev);1161 radeon_ib_pool_fini(rdev);1162 rs600_gart_fini(rdev);1163 radeon_irq_kms_fini(rdev);1164 rdev->accel_working = false;1165 }1166 return 0;1167}1168