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1/*2 * Copyright 2011 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23#ifndef __RS780D_H__24#define __RS780D_H__25 26#define CG_SPLL_FUNC_CNTL 0x60027# define SPLL_RESET (1 << 0)28# define SPLL_SLEEP (1 << 1)29# define SPLL_REF_DIV(x) ((x) << 2)30# define SPLL_REF_DIV_MASK (7 << 2)31# define SPLL_REF_DIV_SHIFT 232# define SPLL_FB_DIV(x) ((x) << 5)33# define SPLL_FB_DIV_MASK (0xff << 2)34# define SPLL_FB_DIV_SHIFT 235# define SPLL_PULSEEN (1 << 13)36# define SPLL_PULSENUM(x) ((x) << 14)37# define SPLL_PULSENUM_MASK (3 << 14)38# define SPLL_SW_HILEN(x) ((x) << 16)39# define SPLL_SW_HILEN_MASK (0xf << 16)40# define SPLL_SW_HILEN_SHIFT 1641# define SPLL_SW_LOLEN(x) ((x) << 20)42# define SPLL_SW_LOLEN_MASK (0xf << 20)43# define SPLL_SW_LOLEN_SHIFT 2044# define SPLL_DIVEN (1 << 24)45# define SPLL_BYPASS_EN (1 << 25)46# define SPLL_CHG_STATUS (1 << 29)47# define SPLL_CTLREQ (1 << 30)48# define SPLL_CTLACK (1 << 31)49 50/* RS780/RS880 PM */51#define FVTHROT_CNTRL_REG 0x300052#define DONT_WAIT_FOR_FBDIV_WRAP (1 << 0)53#define MINIMUM_CIP(x) ((x) << 1)54#define MINIMUM_CIP_SHIFT 155#define MINIMUM_CIP_MASK 0x1fffffe56#define REFRESH_RATE_DIVISOR(x) ((x) << 25)57#define REFRESH_RATE_DIVISOR_SHIFT 2558#define REFRESH_RATE_DIVISOR_MASK (0x3 << 25)59#define ENABLE_FV_THROT (1 << 27)60#define ENABLE_FV_UPDATE (1 << 28)61#define TREND_SEL_MODE (1 << 29)62#define FORCE_TREND_SEL (1 << 30)63#define ENABLE_FV_THROT_IO (1 << 31)64#define FVTHROT_TARGET_REG 0x300465#define TARGET_IDLE_COUNT(x) ((x) << 0)66#define TARGET_IDLE_COUNT_MASK 0xffffff67#define TARGET_IDLE_COUNT_SHIFT 068#define FVTHROT_CB1 0x300869#define FVTHROT_CB2 0x300c70#define FVTHROT_CB3 0x301071#define FVTHROT_CB4 0x301472#define FVTHROT_UTC0 0x301873#define FVTHROT_UTC1 0x301c74#define FVTHROT_UTC2 0x302075#define FVTHROT_UTC3 0x302476#define FVTHROT_UTC4 0x302877#define FVTHROT_DTC0 0x302c78#define FVTHROT_DTC1 0x303079#define FVTHROT_DTC2 0x303480#define FVTHROT_DTC3 0x303881#define FVTHROT_DTC4 0x303c82#define FVTHROT_FBDIV_REG0 0x304083#define MIN_FEEDBACK_DIV(x) ((x) << 0)84#define MIN_FEEDBACK_DIV_MASK 0xfff85#define MIN_FEEDBACK_DIV_SHIFT 086#define MAX_FEEDBACK_DIV(x) ((x) << 12)87#define MAX_FEEDBACK_DIV_MASK (0xfff << 12)88#define MAX_FEEDBACK_DIV_SHIFT 1289#define FVTHROT_FBDIV_REG1 0x304490#define MAX_FEEDBACK_STEP(x) ((x) << 0)91#define MAX_FEEDBACK_STEP_MASK 0xfff92#define MAX_FEEDBACK_STEP_SHIFT 093#define STARTING_FEEDBACK_DIV(x) ((x) << 12)94#define STARTING_FEEDBACK_DIV_MASK (0xfff << 12)95#define STARTING_FEEDBACK_DIV_SHIFT 1296#define FORCE_FEEDBACK_DIV (1 << 24)97#define FVTHROT_FBDIV_REG2 0x304898#define FORCED_FEEDBACK_DIV(x) ((x) << 0)99#define FORCED_FEEDBACK_DIV_MASK 0xfff100#define FORCED_FEEDBACK_DIV_SHIFT 0101#define FB_DIV_TIMER_VAL(x) ((x) << 12)102#define FB_DIV_TIMER_VAL_MASK (0xffff << 12)103#define FB_DIV_TIMER_VAL_SHIFT 12104#define FVTHROT_FB_US_REG0 0x304c105#define FVTHROT_FB_US_REG1 0x3050106#define FVTHROT_FB_DS_REG0 0x3054107#define FVTHROT_FB_DS_REG1 0x3058108#define FVTHROT_PWM_CTRL_REG0 0x305c109#define STARTING_PWM_HIGHTIME(x) ((x) << 0)110#define STARTING_PWM_HIGHTIME_MASK 0xfff111#define STARTING_PWM_HIGHTIME_SHIFT 0112#define NUMBER_OF_CYCLES_IN_PERIOD(x) ((x) << 12)113#define NUMBER_OF_CYCLES_IN_PERIOD_MASK (0xfff << 12)114#define NUMBER_OF_CYCLES_IN_PERIOD_SHIFT 12115#define FORCE_STARTING_PWM_HIGHTIME (1 << 24)116#define INVERT_PWM_WAVEFORM (1 << 25)117#define FVTHROT_PWM_CTRL_REG1 0x3060118#define MIN_PWM_HIGHTIME(x) ((x) << 0)119#define MIN_PWM_HIGHTIME_MASK 0xfff120#define MIN_PWM_HIGHTIME_SHIFT 0121#define MAX_PWM_HIGHTIME(x) ((x) << 12)122#define MAX_PWM_HIGHTIME_MASK (0xfff << 12)123#define MAX_PWM_HIGHTIME_SHIFT 12124#define FVTHROT_PWM_US_REG0 0x3064125#define FVTHROT_PWM_US_REG1 0x3068126#define FVTHROT_PWM_DS_REG0 0x306c127#define FVTHROT_PWM_DS_REG1 0x3070128#define FVTHROT_STATUS_REG0 0x3074129#define CURRENT_FEEDBACK_DIV_MASK 0xfff130#define CURRENT_FEEDBACK_DIV_SHIFT 0131#define FVTHROT_STATUS_REG1 0x3078132#define FVTHROT_STATUS_REG2 0x307c133#define CG_INTGFX_MISC 0x3080134#define FVTHROT_VBLANK_SEL (1 << 9)135#define FVTHROT_PWM_FEEDBACK_DIV_REG1 0x308c136#define RANGE0_PWM_FEEDBACK_DIV(x) ((x) << 0)137#define RANGE0_PWM_FEEDBACK_DIV_MASK 0xfff138#define RANGE0_PWM_FEEDBACK_DIV_SHIFT 0139#define RANGE_PWM_FEEDBACK_DIV_EN (1 << 12)140#define FVTHROT_PWM_FEEDBACK_DIV_REG2 0x3090141#define RANGE1_PWM_FEEDBACK_DIV(x) ((x) << 0)142#define RANGE1_PWM_FEEDBACK_DIV_MASK 0xfff143#define RANGE1_PWM_FEEDBACK_DIV_SHIFT 0144#define RANGE2_PWM_FEEDBACK_DIV(x) ((x) << 12)145#define RANGE2_PWM_FEEDBACK_DIV_MASK (0xfff << 12)146#define RANGE2_PWM_FEEDBACK_DIV_SHIFT 12147#define FVTHROT_PWM_FEEDBACK_DIV_REG3 0x3094148#define RANGE0_PWM(x) ((x) << 0)149#define RANGE0_PWM_MASK 0xfff150#define RANGE0_PWM_SHIFT 0151#define RANGE1_PWM(x) ((x) << 12)152#define RANGE1_PWM_MASK (0xfff << 12)153#define RANGE1_PWM_SHIFT 12154#define FVTHROT_PWM_FEEDBACK_DIV_REG4 0x3098155#define RANGE2_PWM(x) ((x) << 0)156#define RANGE2_PWM_MASK 0xfff157#define RANGE2_PWM_SHIFT 0158#define RANGE3_PWM(x) ((x) << 12)159#define RANGE3_PWM_MASK (0xfff << 12)160#define RANGE3_PWM_SHIFT 12161#define FVTHROT_SLOW_CLK_FEEDBACK_DIV_REG1 0x30ac162#define RANGE0_SLOW_CLK_FEEDBACK_DIV(x) ((x) << 0)163#define RANGE0_SLOW_CLK_FEEDBACK_DIV_MASK 0xfff164#define RANGE0_SLOW_CLK_FEEDBACK_DIV_SHIFT 0165#define RANGE_SLOW_CLK_FEEDBACK_DIV_EN (1 << 12)166 167#define GFX_MACRO_BYPASS_CNTL 0x30c0168#define SPLL_BYPASS_CNTL (1 << 0)169#define UPLL_BYPASS_CNTL (1 << 1)170 171#endif172