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1/*2 * Copyright 2011 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: Alex Deucher23 */24 25#ifndef __RV6XX_DPM_H__26#define __RV6XX_DPM_H__27 28#include "r600_dpm.h"29 30/* Represents a single SCLK step. */31struct rv6xx_sclk_stepping {32 u32 vco_frequency;33 u32 post_divider;34};35 36struct rv6xx_pm_hw_state {37 u32 sclks[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];38 u32 mclks[R600_PM_NUMBER_OF_MCLKS];39 u16 vddc[R600_PM_NUMBER_OF_VOLTAGE_LEVELS];40 bool backbias[R600_PM_NUMBER_OF_VOLTAGE_LEVELS];41 bool pcie_gen2[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];42 u8 high_sclk_index;43 u8 medium_sclk_index;44 u8 low_sclk_index;45 u8 high_mclk_index;46 u8 medium_mclk_index;47 u8 low_mclk_index;48 u8 high_vddc_index;49 u8 medium_vddc_index;50 u8 low_vddc_index;51 u8 rp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];52 u8 lp[R600_PM_NUMBER_OF_ACTIVITY_LEVELS];53};54 55struct rv6xx_power_info {56 /* flags */57 bool voltage_control;58 bool sclk_ss;59 bool mclk_ss;60 bool dynamic_ss;61 bool dynamic_pcie_gen2;62 bool thermal_protection;63 bool display_gap;64 bool gfx_clock_gating;65 /* clk values */66 u32 fb_div_scale;67 u32 spll_ref_div;68 u32 mpll_ref_div;69 u32 bsu;70 u32 bsp;71 /* */72 u32 active_auto_throttle_sources;73 /* current power state */74 u32 restricted_levels;75 struct rv6xx_pm_hw_state hw;76};77 78struct rv6xx_pl {79 u32 sclk;80 u32 mclk;81 u16 vddc;82 u32 flags;83};84 85struct rv6xx_ps {86 struct rv6xx_pl high;87 struct rv6xx_pl medium;88 struct rv6xx_pl low;89};90 91#define RV6XX_DEFAULT_VCLK_FREQ 40000 /* 10 khz */92#define RV6XX_DEFAULT_DCLK_FREQ 30000 /* 10 khz */93 94#endif95