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1/*2 * Copyright 2013 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 * Authors: Alex Deucher23 */24 25#include "radeon.h"26#include "radeon_asic.h"27#include "rv770d.h"28 29/**30 * rv770_copy_dma - copy pages using the DMA engine31 *32 * @rdev: radeon_device pointer33 * @src_offset: src GPU address34 * @dst_offset: dst GPU address35 * @num_gpu_pages: number of GPU pages to xfer36 * @resv: reservation object to sync to37 *38 * Copy GPU paging using the DMA engine (r7xx).39 * Used by the radeon ttm implementation to move pages if40 * registered as the asic copy callback.41 */42struct radeon_fence *rv770_copy_dma(struct radeon_device *rdev,43 uint64_t src_offset, uint64_t dst_offset,44 unsigned num_gpu_pages,45 struct dma_resv *resv)46{47 struct radeon_fence *fence;48 struct radeon_sync sync;49 int ring_index = rdev->asic->copy.dma_ring_index;50 struct radeon_ring *ring = &rdev->ring[ring_index];51 u32 size_in_dw, cur_size_in_dw;52 int i, num_loops;53 int r = 0;54 55 radeon_sync_create(&sync);56 57 size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;58 num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFF);59 r = radeon_ring_lock(rdev, ring, num_loops * 5 + 8);60 if (r) {61 DRM_ERROR("radeon: moving bo (%d).\n", r);62 radeon_sync_free(rdev, &sync, NULL);63 return ERR_PTR(r);64 }65 66 radeon_sync_resv(rdev, &sync, resv, false);67 radeon_sync_rings(rdev, &sync, ring->idx);68 69 for (i = 0; i < num_loops; i++) {70 cur_size_in_dw = size_in_dw;71 if (cur_size_in_dw > 0xFFFF)72 cur_size_in_dw = 0xFFFF;73 size_in_dw -= cur_size_in_dw;74 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));75 radeon_ring_write(ring, dst_offset & 0xfffffffc);76 radeon_ring_write(ring, src_offset & 0xfffffffc);77 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);78 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);79 src_offset += cur_size_in_dw * 4;80 dst_offset += cur_size_in_dw * 4;81 }82 83 r = radeon_fence_emit(rdev, &fence, ring->idx);84 if (r) {85 radeon_ring_unlock_undo(rdev, ring);86 radeon_sync_free(rdev, &sync, NULL);87 return ERR_PTR(r);88 }89 90 radeon_ring_unlock_commit(rdev, ring, false);91 radeon_sync_free(rdev, &sync, fence);92 93 return fence;94}95