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1/*2 * Copyright 2011 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice (including the next12 * paragraph) shall be included in all copies or substantial portions of the13 * Software.14 *15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL18 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER21 * DEALINGS IN THE SOFTWARE.22 *23 */24 25#ifndef SI_BLIT_SHADERS_H26#define SI_BLIT_SHADERS_H27 28static const u32 si_default_state[] = {29 0xc0066900,30 0x00000000,31 0x00000060, /* DB_RENDER_CONTROL */32 0x00000000, /* DB_COUNT_CONTROL */33 0x00000000, /* DB_DEPTH_VIEW */34 0x0000002a, /* DB_RENDER_OVERRIDE */35 0x00000000, /* DB_RENDER_OVERRIDE2 */36 0x00000000, /* DB_HTILE_DATA_BASE */37 38 0xc0046900,39 0x00000008,40 0x00000000, /* DB_DEPTH_BOUNDS_MIN */41 0x00000000, /* DB_DEPTH_BOUNDS_MAX */42 0x00000000, /* DB_STENCIL_CLEAR */43 0x00000000, /* DB_DEPTH_CLEAR */44 45 0xc0036900,46 0x0000000f,47 0x00000000, /* DB_DEPTH_INFO */48 0x00000000, /* DB_Z_INFO */49 0x00000000, /* DB_STENCIL_INFO */50 51 0xc0016900,52 0x00000080,53 0x00000000, /* PA_SC_WINDOW_OFFSET */54 55 0xc00d6900,56 0x00000083,57 0x0000ffff, /* PA_SC_CLIPRECT_RULE */58 0x00000000, /* PA_SC_CLIPRECT_0_TL */59 0x20002000, /* PA_SC_CLIPRECT_0_BR */60 0x00000000,61 0x20002000,62 0x00000000,63 0x20002000,64 0x00000000,65 0x20002000,66 0xaaaaaaaa, /* PA_SC_EDGERULE */67 0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */68 0x0000000f, /* CB_TARGET_MASK */69 0x0000000f, /* CB_SHADER_MASK */70 71 0xc0226900,72 0x00000094,73 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */74 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */75 0x80000000,76 0x20002000,77 0x80000000,78 0x20002000,79 0x80000000,80 0x20002000,81 0x80000000,82 0x20002000,83 0x80000000,84 0x20002000,85 0x80000000,86 0x20002000,87 0x80000000,88 0x20002000,89 0x80000000,90 0x20002000,91 0x80000000,92 0x20002000,93 0x80000000,94 0x20002000,95 0x80000000,96 0x20002000,97 0x80000000,98 0x20002000,99 0x80000000,100 0x20002000,101 0x80000000,102 0x20002000,103 0x80000000,104 0x20002000,105 0x00000000, /* PA_SC_VPORT_ZMIN_0 */106 0x3f800000, /* PA_SC_VPORT_ZMAX_0 */107 108 0xc0026900,109 0x000000d9,110 0x00000000, /* CP_RINGID */111 0x00000000, /* CP_VMID */112 113 0xc0046900,114 0x00000100,115 0xffffffff, /* VGT_MAX_VTX_INDX */116 0x00000000, /* VGT_MIN_VTX_INDX */117 0x00000000, /* VGT_INDX_OFFSET */118 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */119 120 0xc0046900,121 0x00000105,122 0x00000000, /* CB_BLEND_RED */123 0x00000000, /* CB_BLEND_GREEN */124 0x00000000, /* CB_BLEND_BLUE */125 0x00000000, /* CB_BLEND_ALPHA */126 127 0xc0016900,128 0x000001e0,129 0x00000000, /* CB_BLEND0_CONTROL */130 131 0xc00e6900,132 0x00000200,133 0x00000000, /* DB_DEPTH_CONTROL */134 0x00000000, /* DB_EQAA */135 0x00cc0010, /* CB_COLOR_CONTROL */136 0x00000210, /* DB_SHADER_CONTROL */137 0x00010000, /* PA_CL_CLIP_CNTL */138 0x00000004, /* PA_SU_SC_MODE_CNTL */139 0x00000100, /* PA_CL_VTE_CNTL */140 0x00000000, /* PA_CL_VS_OUT_CNTL */141 0x00000000, /* PA_CL_NANINF_CNTL */142 0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */143 0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */144 0x00000000, /* PA_SU_PRIM_FILTER_CNTL */145 0x00000000, /* */146 0x00000000, /* */147 148 0xc0116900,149 0x00000280,150 0x00000000, /* PA_SU_POINT_SIZE */151 0x00000000, /* PA_SU_POINT_MINMAX */152 0x00000008, /* PA_SU_LINE_CNTL */153 0x00000000, /* PA_SC_LINE_STIPPLE */154 0x00000000, /* VGT_OUTPUT_PATH_CNTL */155 0x00000000, /* VGT_HOS_CNTL */156 0x00000000,157 0x00000000,158 0x00000000,159 0x00000000,160 0x00000000,161 0x00000000,162 0x00000000,163 0x00000000,164 0x00000000,165 0x00000000,166 0x00000000, /* VGT_GS_MODE */167 168 0xc0026900,169 0x00000292,170 0x00000000, /* PA_SC_MODE_CNTL_0 */171 0x00000000, /* PA_SC_MODE_CNTL_1 */172 173 0xc0016900,174 0x000002a1,175 0x00000000, /* VGT_PRIMITIVEID_EN */176 177 0xc0016900,178 0x000002a5,179 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */180 181 0xc0026900,182 0x000002a8,183 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */184 0x00000000,185 186 0xc0026900,187 0x000002ad,188 0x00000000, /* VGT_REUSE_OFF */189 0x00000000,190 191 0xc0016900,192 0x000002d5,193 0x00000000, /* VGT_SHADER_STAGES_EN */194 195 0xc0016900,196 0x000002dc,197 0x0000aa00, /* DB_ALPHA_TO_MASK */198 199 0xc0066900,200 0x000002de,201 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */202 0x00000000,203 0x00000000,204 0x00000000,205 0x00000000,206 0x00000000,207 208 0xc0026900,209 0x000002e5,210 0x00000000, /* VGT_STRMOUT_CONFIG */211 0x00000000,212 213 0xc01b6900,214 0x000002f5,215 0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */216 0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */217 0x00000000, /* PA_SC_LINE_CNTL */218 0x00000000, /* PA_SC_AA_CONFIG */219 0x00000005, /* PA_SU_VTX_CNTL */220 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */221 0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */222 0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */223 0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */224 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */225 0x00000000,226 0x00000000,227 0x00000000,228 0x00000000,229 0x00000000,230 0x00000000,231 0x00000000,232 0x00000000,233 0x00000000,234 0x00000000,235 0x00000000,236 0x00000000,237 0x00000000,238 0x00000000,239 0x00000000,240 0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */241 0xffffffff,242 243 0xc0026900,244 0x00000316,245 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */246 0x00000010, /* */247};248 249static const u32 si_default_size = ARRAY_SIZE(si_default_state);250 251#endif252