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1/*2 * Copyright 2012 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23#ifndef __SI_DPM_H__24#define __SI_DPM_H__25 26#include "ni_dpm.h"27#include "sislands_smc.h"28 29enum si_cac_config_reg_type {30 SISLANDS_CACCONFIG_MMR = 0,31 SISLANDS_CACCONFIG_CGIND,32 SISLANDS_CACCONFIG_MAX33};34 35struct si_cac_config_reg {36 u32 offset;37 u32 mask;38 u32 shift;39 u32 value;40 enum si_cac_config_reg_type type;41};42 43struct si_powertune_data {44 u32 cac_window;45 u32 l2_lta_window_size_default;46 u8 lts_truncate_default;47 u8 shift_n_default;48 u8 operating_temp;49 struct ni_leakage_coeffients leakage_coefficients;50 u32 fixed_kt;51 u32 lkge_lut_v0_percent;52 u8 dc_cac[NISLANDS_DCCAC_MAX_LEVELS];53 bool enable_powertune_by_default;54};55 56struct si_dyn_powertune_data {57 u32 cac_leakage;58 s32 leakage_minimum_temperature;59 u32 wintime;60 u32 l2_lta_window_size;61 u8 lts_truncate;62 u8 shift_n;63 u8 dc_pwr_value;64 bool disable_uvd_powertune;65};66 67struct si_dte_data {68 u32 tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];69 u32 r[SMC_SISLANDS_DTE_MAX_FILTER_STAGES];70 u32 k;71 u32 t0;72 u32 max_t;73 u8 window_size;74 u8 temp_select;75 u8 dte_mode;76 u8 tdep_count;77 u8 t_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];78 u32 tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];79 u32 tdep_r[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE];80 u32 t_threshold;81 bool enable_dte_by_default;82};83 84struct si_clock_registers {85 u32 cg_spll_func_cntl;86 u32 cg_spll_func_cntl_2;87 u32 cg_spll_func_cntl_3;88 u32 cg_spll_func_cntl_4;89 u32 cg_spll_spread_spectrum;90 u32 cg_spll_spread_spectrum_2;91 u32 dll_cntl;92 u32 mclk_pwrmgt_cntl;93 u32 mpll_ad_func_cntl;94 u32 mpll_dq_func_cntl;95 u32 mpll_func_cntl;96 u32 mpll_func_cntl_1;97 u32 mpll_func_cntl_2;98 u32 mpll_ss1;99 u32 mpll_ss2;100};101 102struct si_mc_reg_entry {103 u32 mclk_max;104 u32 mc_data[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];105};106 107struct si_mc_reg_table {108 u8 last;109 u8 num_entries;110 u16 valid_flag;111 struct si_mc_reg_entry mc_reg_table_entry[MAX_AC_TIMING_ENTRIES];112 SMC_NIslands_MCRegisterAddress mc_reg_address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE];113};114 115#define SISLANDS_MCREGISTERTABLE_INITIAL_SLOT 0116#define SISLANDS_MCREGISTERTABLE_ACPI_SLOT 1117#define SISLANDS_MCREGISTERTABLE_ULV_SLOT 2118#define SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT 3119 120struct si_leakage_voltage_entry {121 u16 voltage;122 u16 leakage_index;123};124 125#define SISLANDS_LEAKAGE_INDEX0 0xff01126#define SISLANDS_MAX_LEAKAGE_COUNT 4127 128struct si_leakage_voltage {129 u16 count;130 struct si_leakage_voltage_entry entries[SISLANDS_MAX_LEAKAGE_COUNT];131};132 133#define SISLANDS_MAX_HARDWARE_POWERLEVELS 5134 135struct si_ulv_param {136 bool supported;137 u32 cg_ulv_control;138 u32 cg_ulv_parameter;139 u32 volt_change_delay;140 struct rv7xx_pl pl;141 bool one_pcie_lane_in_ulv;142};143 144struct si_power_info {145 /* must be first! */146 struct ni_power_info ni;147 struct si_clock_registers clock_registers;148 struct si_mc_reg_table mc_reg_table;149 struct atom_voltage_table mvdd_voltage_table;150 struct atom_voltage_table vddc_phase_shed_table;151 struct si_leakage_voltage leakage_voltage;152 u16 mvdd_bootup_value;153 struct si_ulv_param ulv;154 u32 max_cu;155 /* pcie gen */156 enum radeon_pcie_gen force_pcie_gen;157 enum radeon_pcie_gen boot_pcie_gen;158 enum radeon_pcie_gen acpi_pcie_gen;159 u32 sys_pcie_mask;160 /* flags */161 bool enable_dte;162 bool enable_ppm;163 bool vddc_phase_shed_control;164 bool pspp_notify_required;165 bool sclk_deep_sleep_above_low;166 bool voltage_control_svi2;167 bool vddci_control_svi2;168 /* smc offsets */169 u32 sram_end;170 u32 state_table_start;171 u32 soft_regs_start;172 u32 mc_reg_table_start;173 u32 arb_table_start;174 u32 cac_table_start;175 u32 dte_table_start;176 u32 spll_table_start;177 u32 papm_cfg_table_start;178 u32 fan_table_start;179 /* CAC stuff */180 const struct si_cac_config_reg *cac_weights;181 const struct si_cac_config_reg *lcac_config;182 const struct si_cac_config_reg *cac_override;183 const struct si_powertune_data *powertune_data;184 struct si_dyn_powertune_data dyn_powertune_data;185 /* DTE stuff */186 struct si_dte_data dte_data;187 /* scratch structs */188 SMC_SIslands_MCRegisters smc_mc_reg_table;189 SISLANDS_SMC_STATETABLE smc_statetable;190 PP_SIslands_PAPMParameters papm_parm;191 /* SVI2 */192 u8 svd_gpio_id;193 u8 svc_gpio_id;194 /* fan control */195 bool fan_ctrl_is_in_default_mode;196 u32 t_min;197 u32 fan_ctrl_default_mode;198 bool fan_is_controlled_by_smc;199};200 201#define SISLANDS_INITIAL_STATE_ARB_INDEX 0202#define SISLANDS_ACPI_STATE_ARB_INDEX 1203#define SISLANDS_ULV_STATE_ARB_INDEX 2204#define SISLANDS_DRIVER_STATE_ARB_INDEX 3205 206#define SISLANDS_DPM2_MAX_PULSE_SKIP 256207 208#define SISLANDS_DPM2_NEAR_TDP_DEC 10209#define SISLANDS_DPM2_ABOVE_SAFE_INC 5210#define SISLANDS_DPM2_BELOW_SAFE_INC 20211 212#define SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT 80213 214#define SISLANDS_DPM2_MAXPS_PERCENT_H 99215#define SISLANDS_DPM2_MAXPS_PERCENT_M 99216 217#define SISLANDS_DPM2_SQ_RAMP_MAX_POWER 0x3FFF218#define SISLANDS_DPM2_SQ_RAMP_MIN_POWER 0x12219#define SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15220#define SISLANDS_DPM2_SQ_RAMP_STI_SIZE 0x1E221#define SISLANDS_DPM2_SQ_RAMP_LTI_RATIO 0xF222 223#define SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN 10224 225#define SISLANDS_VRC_DFLT 0xC000B3226#define SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT 1687227#define SISLANDS_CGULVPARAMETER_DFLT 0x00040035228#define SISLANDS_CGULVCONTROL_DFLT 0x1f007550229 230u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);231u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);232void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,233 u32 max_voltage_steps,234 struct atom_voltage_table *voltage_table);235 236#endif237