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1/*2 * Copyright 2013 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23 24#ifndef SMU7_FUSION_H25#define SMU7_FUSION_H26 27#include "smu7.h"28 29#pragma pack(push, 1)30 31#define SMU7_DTE_ITERATIONS 532#define SMU7_DTE_SOURCES 533#define SMU7_DTE_SINKS 334#define SMU7_NUM_CPU_TES 235#define SMU7_NUM_GPU_TES 136#define SMU7_NUM_NON_TES 237 38// All 'soft registers' should be uint32_t.39struct SMU7_SoftRegisters {40 uint32_t RefClockFrequency;41 uint32_t PmTimerP;42 uint32_t FeatureEnables;43 uint32_t HandshakeDisables;44 45 uint8_t DisplayPhy1Config;46 uint8_t DisplayPhy2Config;47 uint8_t DisplayPhy3Config;48 uint8_t DisplayPhy4Config;49 50 uint8_t DisplayPhy5Config;51 uint8_t DisplayPhy6Config;52 uint8_t DisplayPhy7Config;53 uint8_t DisplayPhy8Config;54 55 uint32_t AverageGraphicsA;56 uint32_t AverageMemoryA;57 uint32_t AverageGioA;58 59 uint8_t SClkDpmEnabledLevels;60 uint8_t MClkDpmEnabledLevels;61 uint8_t LClkDpmEnabledLevels;62 uint8_t PCIeDpmEnabledLevels;63 64 uint8_t UVDDpmEnabledLevels;65 uint8_t SAMUDpmEnabledLevels;66 uint8_t ACPDpmEnabledLevels;67 uint8_t VCEDpmEnabledLevels;68 69 uint32_t DRAM_LOG_ADDR_H;70 uint32_t DRAM_LOG_ADDR_L;71 uint32_t DRAM_LOG_PHY_ADDR_H;72 uint32_t DRAM_LOG_PHY_ADDR_L;73 uint32_t DRAM_LOG_BUFF_SIZE;74 uint32_t UlvEnterC;75 uint32_t UlvTime;76 uint32_t Reserved[3];77 78};79 80typedef struct SMU7_SoftRegisters SMU7_SoftRegisters;81 82struct SMU7_Fusion_GraphicsLevel {83 uint32_t MinVddNb;84 85 uint32_t SclkFrequency;86 87 uint8_t Vid;88 uint8_t VidOffset;89 uint16_t AT;90 91 uint8_t PowerThrottle;92 uint8_t GnbSlow;93 uint8_t ForceNbPs1;94 uint8_t SclkDid;95 96 uint8_t DisplayWatermark;97 uint8_t EnabledForActivity;98 uint8_t EnabledForThrottle;99 uint8_t UpH;100 101 uint8_t DownH;102 uint8_t VoltageDownH;103 uint8_t DeepSleepDivId;104 105 uint8_t ClkBypassCntl;106 107 uint32_t reserved;108};109 110typedef struct SMU7_Fusion_GraphicsLevel SMU7_Fusion_GraphicsLevel;111 112struct SMU7_Fusion_GIOLevel {113 uint8_t EnabledForActivity;114 uint8_t LclkDid;115 uint8_t Vid;116 uint8_t VoltageDownH;117 118 uint32_t MinVddNb;119 120 uint16_t ResidencyCounter;121 uint8_t UpH;122 uint8_t DownH;123 124 uint32_t LclkFrequency;125 126 uint8_t ActivityLevel;127 uint8_t EnabledForThrottle;128 129 uint8_t ClkBypassCntl;130 131 uint8_t padding;132};133 134typedef struct SMU7_Fusion_GIOLevel SMU7_Fusion_GIOLevel;135 136// UVD VCLK/DCLK state (level) definition.137struct SMU7_Fusion_UvdLevel {138 uint32_t VclkFrequency;139 uint32_t DclkFrequency;140 uint16_t MinVddNb;141 uint8_t VclkDivider;142 uint8_t DclkDivider;143 144 uint8_t VClkBypassCntl;145 uint8_t DClkBypassCntl;146 147 uint8_t padding[2];148 149};150 151typedef struct SMU7_Fusion_UvdLevel SMU7_Fusion_UvdLevel;152 153// Clocks for other external blocks (VCE, ACP, SAMU).154struct SMU7_Fusion_ExtClkLevel {155 uint32_t Frequency;156 uint16_t MinVoltage;157 uint8_t Divider;158 uint8_t ClkBypassCntl;159 160 uint32_t Reserved;161};162typedef struct SMU7_Fusion_ExtClkLevel SMU7_Fusion_ExtClkLevel;163 164struct SMU7_Fusion_ACPILevel {165 uint32_t Flags;166 uint32_t MinVddNb;167 uint32_t SclkFrequency;168 uint8_t SclkDid;169 uint8_t GnbSlow;170 uint8_t ForceNbPs1;171 uint8_t DisplayWatermark;172 uint8_t DeepSleepDivId;173 uint8_t padding[3];174};175 176typedef struct SMU7_Fusion_ACPILevel SMU7_Fusion_ACPILevel;177 178struct SMU7_Fusion_NbDpm {179 uint8_t DpmXNbPsHi;180 uint8_t DpmXNbPsLo;181 uint8_t Dpm0PgNbPsHi;182 uint8_t Dpm0PgNbPsLo;183 uint8_t EnablePsi1;184 uint8_t SkipDPM0;185 uint8_t SkipPG;186 uint8_t Hysteresis;187 uint8_t EnableDpmPstatePoll;188 uint8_t padding[3];189};190 191typedef struct SMU7_Fusion_NbDpm SMU7_Fusion_NbDpm;192 193struct SMU7_Fusion_StateInfo {194 uint32_t SclkFrequency;195 uint32_t LclkFrequency;196 uint32_t VclkFrequency;197 uint32_t DclkFrequency;198 uint32_t SamclkFrequency;199 uint32_t AclkFrequency;200 uint32_t EclkFrequency;201 uint8_t DisplayWatermark;202 uint8_t McArbIndex;203 int8_t SclkIndex;204 int8_t MclkIndex;205};206 207typedef struct SMU7_Fusion_StateInfo SMU7_Fusion_StateInfo;208 209struct SMU7_Fusion_DpmTable {210 uint32_t SystemFlags;211 212 SMU7_PIDController GraphicsPIDController;213 SMU7_PIDController GioPIDController;214 215 uint8_t GraphicsDpmLevelCount;216 uint8_t GIOLevelCount;217 uint8_t UvdLevelCount;218 uint8_t VceLevelCount;219 220 uint8_t AcpLevelCount;221 uint8_t SamuLevelCount;222 uint16_t FpsHighT;223 224 SMU7_Fusion_GraphicsLevel GraphicsLevel[SMU__NUM_SCLK_DPM_STATE];225 SMU7_Fusion_ACPILevel ACPILevel;226 SMU7_Fusion_UvdLevel UvdLevel[SMU7_MAX_LEVELS_UVD];227 SMU7_Fusion_ExtClkLevel VceLevel[SMU7_MAX_LEVELS_VCE];228 SMU7_Fusion_ExtClkLevel AcpLevel[SMU7_MAX_LEVELS_ACP];229 SMU7_Fusion_ExtClkLevel SamuLevel[SMU7_MAX_LEVELS_SAMU];230 231 uint8_t UvdBootLevel;232 uint8_t VceBootLevel;233 uint8_t AcpBootLevel;234 uint8_t SamuBootLevel;235 uint8_t UVDInterval;236 uint8_t VCEInterval;237 uint8_t ACPInterval;238 uint8_t SAMUInterval;239 240 uint8_t GraphicsBootLevel;241 uint8_t GraphicsInterval;242 uint8_t GraphicsThermThrottleEnable;243 uint8_t GraphicsVoltageChangeEnable;244 245 uint8_t GraphicsClkSlowEnable;246 uint8_t GraphicsClkSlowDivider;247 uint16_t FpsLowT;248 249 uint32_t DisplayCac;250 uint32_t LowSclkInterruptT;251 252 uint32_t DRAM_LOG_ADDR_H;253 uint32_t DRAM_LOG_ADDR_L;254 uint32_t DRAM_LOG_PHY_ADDR_H;255 uint32_t DRAM_LOG_PHY_ADDR_L;256 uint32_t DRAM_LOG_BUFF_SIZE;257 258};259 260struct SMU7_Fusion_GIODpmTable {261 262 SMU7_Fusion_GIOLevel GIOLevel[SMU7_MAX_LEVELS_GIO];263 264 SMU7_PIDController GioPIDController;265 266 uint32_t GIOLevelCount;267 268 uint8_t Enable;269 uint8_t GIOVoltageChangeEnable;270 uint8_t GIOBootLevel;271 uint8_t padding;272 uint8_t padding1[2];273 uint8_t TargetState;274 uint8_t CurrenttState;275 uint8_t ThrottleOnHtc;276 uint8_t ThermThrottleStatus;277 uint8_t ThermThrottleTempSelect;278 uint8_t ThermThrottleEnable;279 uint16_t TemperatureLimitHigh;280 uint16_t TemperatureLimitLow;281 282};283 284typedef struct SMU7_Fusion_DpmTable SMU7_Fusion_DpmTable;285typedef struct SMU7_Fusion_GIODpmTable SMU7_Fusion_GIODpmTable;286 287#pragma pack(pop)288 289#endif290 291