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1/*2 * Copyright 2012 Advanced Micro Devices, Inc.3 *4 * Permission is hereby granted, free of charge, to any person obtaining a5 * copy of this software and associated documentation files (the "Software"),6 * to deal in the Software without restriction, including without limitation7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,8 * and/or sell copies of the Software, and to permit persons to whom the9 * Software is furnished to do so, subject to the following conditions:10 *11 * The above copyright notice and this permission notice shall be included in12 * all copies or substantial portions of the Software.13 *14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR20 * OTHER DEALINGS IN THE SOFTWARE.21 *22 */23#ifndef __SUMO_DPM_H__24#define __SUMO_DPM_H__25 26#include "atom.h"27#include "radeon.h"28 29#define SUMO_MAX_HARDWARE_POWERLEVELS 530#define SUMO_PM_NUMBER_OF_TC 1531 32struct sumo_pl {33 u32 sclk;34 u32 vddc_index;35 u32 ds_divider_index;36 u32 ss_divider_index;37 u32 allow_gnb_slow;38 u32 sclk_dpm_tdp_limit;39};40 41/* used for the flags field */42#define SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE (1 << 0)43#define SUMO_POWERSTATE_FLAGS_BOOST_STATE (1 << 1)44 45struct sumo_ps {46 struct sumo_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];47 u32 num_levels;48 /* flags */49 u32 flags;50};51 52#define NUMBER_OF_M3ARB_PARAM_SETS 1053#define SUMO_MAX_NUMBER_VOLTAGES 454 55struct sumo_disp_clock_voltage_mapping_table {56 u32 num_max_voltage_levels;57 u32 display_clock_frequency[SUMO_MAX_NUMBER_VOLTAGES];58};59 60struct sumo_vid_mapping_entry {61 u16 vid_2bit;62 u16 vid_7bit;63};64 65struct sumo_vid_mapping_table {66 u32 num_entries;67 struct sumo_vid_mapping_entry entries[SUMO_MAX_NUMBER_VOLTAGES];68};69 70struct sumo_sclk_voltage_mapping_entry {71 u32 sclk_frequency;72 u16 vid_2bit;73 u16 rsv;74};75 76struct sumo_sclk_voltage_mapping_table {77 u32 num_max_dpm_entries;78 struct sumo_sclk_voltage_mapping_entry entries[SUMO_MAX_HARDWARE_POWERLEVELS];79};80 81struct sumo_sys_info {82 u32 bootup_sclk;83 u32 min_sclk;84 u32 bootup_uma_clk;85 u16 bootup_nb_voltage_index;86 u8 htc_tmp_lmt;87 u8 htc_hyst_lmt;88 struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table;89 struct sumo_disp_clock_voltage_mapping_table disp_clk_voltage_mapping_table;90 struct sumo_vid_mapping_table vid_mapping_table;91 u32 csr_m3_arb_cntl_default[NUMBER_OF_M3ARB_PARAM_SETS];92 u32 csr_m3_arb_cntl_uvd[NUMBER_OF_M3ARB_PARAM_SETS];93 u32 csr_m3_arb_cntl_fs3d[NUMBER_OF_M3ARB_PARAM_SETS];94 u32 sclk_dpm_boost_margin;95 u32 sclk_dpm_throttle_margin;96 u32 sclk_dpm_tdp_limit_pg;97 u32 gnb_tdp_limit;98 u32 sclk_dpm_tdp_limit_boost;99 u32 boost_sclk;100 u32 boost_vid_2bit;101 bool enable_boost;102};103 104struct sumo_power_info {105 u32 asi;106 u32 pasi;107 u32 bsp;108 u32 bsu;109 u32 pbsp;110 u32 pbsu;111 u32 dsp;112 u32 psp;113 u32 thermal_auto_throttling;114 u32 uvd_m3_arbiter;115 u32 fw_version;116 struct sumo_sys_info sys_info;117 struct sumo_pl acpi_pl;118 struct sumo_pl boot_pl;119 struct sumo_pl boost_pl;120 bool disable_gfx_power_gating_in_uvd;121 bool driver_nbps_policy_disable;122 bool enable_alt_vddnb;123 bool enable_dynamic_m3_arbiter;124 bool enable_gfx_clock_gating;125 bool enable_gfx_power_gating;126 bool enable_mg_clock_gating;127 bool enable_sclk_ds;128 bool enable_auto_thermal_throttling;129 bool enable_dynamic_patch_ps;130 bool enable_dpm;131 bool enable_boost;132 struct radeon_ps current_rps;133 struct sumo_ps current_ps;134 struct radeon_ps requested_rps;135 struct sumo_ps requested_ps;136};137 138#define SUMO_UTC_DFLT_00 0x48139#define SUMO_UTC_DFLT_01 0x44140#define SUMO_UTC_DFLT_02 0x44141#define SUMO_UTC_DFLT_03 0x44142#define SUMO_UTC_DFLT_04 0x44143#define SUMO_UTC_DFLT_05 0x44144#define SUMO_UTC_DFLT_06 0x44145#define SUMO_UTC_DFLT_07 0x44146#define SUMO_UTC_DFLT_08 0x44147#define SUMO_UTC_DFLT_09 0x44148#define SUMO_UTC_DFLT_10 0x44149#define SUMO_UTC_DFLT_11 0x44150#define SUMO_UTC_DFLT_12 0x44151#define SUMO_UTC_DFLT_13 0x44152#define SUMO_UTC_DFLT_14 0x44153 154#define SUMO_DTC_DFLT_00 0x48155#define SUMO_DTC_DFLT_01 0x44156#define SUMO_DTC_DFLT_02 0x44157#define SUMO_DTC_DFLT_03 0x44158#define SUMO_DTC_DFLT_04 0x44159#define SUMO_DTC_DFLT_05 0x44160#define SUMO_DTC_DFLT_06 0x44161#define SUMO_DTC_DFLT_07 0x44162#define SUMO_DTC_DFLT_08 0x44163#define SUMO_DTC_DFLT_09 0x44164#define SUMO_DTC_DFLT_10 0x44165#define SUMO_DTC_DFLT_11 0x44166#define SUMO_DTC_DFLT_12 0x44167#define SUMO_DTC_DFLT_13 0x44168#define SUMO_DTC_DFLT_14 0x44169 170#define SUMO_AH_DFLT 5171 172#define SUMO_R_DFLT0 70173#define SUMO_R_DFLT1 70174#define SUMO_R_DFLT2 70175#define SUMO_R_DFLT3 70176#define SUMO_R_DFLT4 100177 178#define SUMO_L_DFLT0 0179#define SUMO_L_DFLT1 20180#define SUMO_L_DFLT2 20181#define SUMO_L_DFLT3 20182#define SUMO_L_DFLT4 20183#define SUMO_VRC_DFLT 0x30033184#define SUMO_MGCGTTLOCAL0_DFLT 0185#define SUMO_MGCGTTLOCAL1_DFLT 0186#define SUMO_GICST_DFLT 19187#define SUMO_SST_DFLT 8188#define SUMO_VOLTAGEDROPT_DFLT 1189#define SUMO_GFXPOWERGATINGT_DFLT 100190 191/* sumo_dpm.c */192void sumo_gfx_clockgating_initialize(struct radeon_device *rdev);193void sumo_program_vc(struct radeon_device *rdev, u32 vrc);194void sumo_clear_vc(struct radeon_device *rdev);195void sumo_program_sstp(struct radeon_device *rdev);196void sumo_take_smu_control(struct radeon_device *rdev, bool enable);197void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev,198 struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,199 ATOM_AVAILABLE_SCLK_LIST *table);200void sumo_construct_vid_mapping_table(struct radeon_device *rdev,201 struct sumo_vid_mapping_table *vid_mapping_table,202 ATOM_AVAILABLE_SCLK_LIST *table);203u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev,204 struct sumo_vid_mapping_table *vid_mapping_table,205 u32 vid_2bit);206u32 sumo_get_sleep_divider_from_id(u32 id);207u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev,208 u32 sclk,209 u32 min_sclk_in_sr);210struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev);211 212/* sumo_smc.c */213void sumo_initialize_m3_arb(struct radeon_device *rdev);214void sumo_smu_pg_init(struct radeon_device *rdev);215void sumo_set_tdp_limit(struct radeon_device *rdev, u32 index, u32 tdp_limit);216void sumo_smu_notify_alt_vddnb_change(struct radeon_device *rdev,217 bool powersaving, bool force_nbps1);218void sumo_boost_state_enable(struct radeon_device *rdev, bool enable);219void sumo_enable_boost_timer(struct radeon_device *rdev);220u32 sumo_get_running_fw_version(struct radeon_device *rdev);221 222#endif223