554 lines · c
1/* SPDX-License-Identifier: GPL-2.0 */2/*3 * R-Car Display Unit Registers Definitions4 *5 * Copyright (C) 2013-2015 Renesas Electronics Corporation6 *7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)8 */9 10#ifndef __RCAR_DU_REGS_H__11#define __RCAR_DU_REGS_H__12 13#define DU0_REG_OFFSET 0x0000014#define DU1_REG_OFFSET 0x3000015#define DU2_REG_OFFSET 0x4000016#define DU3_REG_OFFSET 0x7000017 18/* -----------------------------------------------------------------------------19 * Display Control Registers20 */21 22#define DSYSR 0x00000 /* display 1 */23#define DSYSR_ILTS (1 << 29)24#define DSYSR_DSEC (1 << 20)25#define DSYSR_IUPD (1 << 16)26#define DSYSR_DRES (1 << 9)27#define DSYSR_DEN (1 << 8)28#define DSYSR_TVM_MASTER (0 << 6)29#define DSYSR_TVM_SWITCH (1 << 6)30#define DSYSR_TVM_TVSYNC (2 << 6)31#define DSYSR_TVM_MASK (3 << 6)32#define DSYSR_SCM_INT_NONE (0 << 4)33#define DSYSR_SCM_INT_SYNC (2 << 4)34#define DSYSR_SCM_INT_VIDEO (3 << 4)35#define DSYSR_SCM_MASK (3 << 4)36 37#define DSMR 0x0000438#define DSMR_VSPM (1 << 28)39#define DSMR_ODPM (1 << 27)40#define DSMR_DIPM_DISP (0 << 25)41#define DSMR_DIPM_CSYNC (1 << 25)42#define DSMR_DIPM_DE (3 << 25)43#define DSMR_DIPM_MASK (3 << 25)44#define DSMR_CSPM (1 << 24)45#define DSMR_DIL (1 << 19)46#define DSMR_VSL (1 << 18)47#define DSMR_HSL (1 << 17)48#define DSMR_DDIS (1 << 16)49#define DSMR_CDEL (1 << 15)50#define DSMR_CDEM_CDE (0 << 13)51#define DSMR_CDEM_LOW (2 << 13)52#define DSMR_CDEM_HIGH (3 << 13)53#define DSMR_CDEM_MASK (3 << 13)54#define DSMR_CDED (1 << 12)55#define DSMR_ODEV (1 << 8)56#define DSMR_CSY_VH_OR (0 << 6)57#define DSMR_CSY_333 (2 << 6)58#define DSMR_CSY_222 (3 << 6)59#define DSMR_CSY_MASK (3 << 6)60 61#define DSSR 0x0000862#define DSSR_VC1FB_DSA0 (0 << 30)63#define DSSR_VC1FB_DSA1 (1 << 30)64#define DSSR_VC1FB_DSA2 (2 << 30)65#define DSSR_VC1FB_INIT (3 << 30)66#define DSSR_VC1FB_MASK (3 << 30)67#define DSSR_VC0FB_DSA0 (0 << 28)68#define DSSR_VC0FB_DSA1 (1 << 28)69#define DSSR_VC0FB_DSA2 (2 << 28)70#define DSSR_VC0FB_INIT (3 << 28)71#define DSSR_VC0FB_MASK (3 << 28)72#define DSSR_DFB(n) (1 << ((n)+15))73#define DSSR_TVR (1 << 15)74#define DSSR_FRM (1 << 14)75#define DSSR_VBK (1 << 11)76#define DSSR_RINT (1 << 9)77#define DSSR_HBK (1 << 8)78#define DSSR_ADC(n) (1 << ((n)-1))79 80#define DSRCR 0x0000c81#define DSRCR_TVCL (1 << 15)82#define DSRCR_FRCL (1 << 14)83#define DSRCR_VBCL (1 << 11)84#define DSRCR_RICL (1 << 9)85#define DSRCR_HBCL (1 << 8)86#define DSRCR_ADCL(n) (1 << ((n)-1))87#define DSRCR_MASK 0x0000cbff88 89#define DIER 0x0001090#define DIER_TVE (1 << 15)91#define DIER_FRE (1 << 14)92#define DIER_VBE (1 << 11)93#define DIER_RIE (1 << 9)94#define DIER_HBE (1 << 8)95#define DIER_ADCE(n) (1 << ((n)-1))96 97#define CPCR 0x0001498#define CPCR_CP4CE (1 << 19)99#define CPCR_CP3CE (1 << 18)100#define CPCR_CP2CE (1 << 17)101#define CPCR_CP1CE (1 << 16)102 103#define DPPR 0x00018104#define DPPR_DPE(n) (1 << ((n)*4-1))105#define DPPR_DPS(n, p) (((p)-1) << DPPR_DPS_SHIFT(n))106#define DPPR_DPS_SHIFT(n) (((n)-1)*4)107#define DPPR_BPP16 (DPPR_DPE(8) | DPPR_DPS(8, 1)) /* plane1 */108#define DPPR_BPP32_P1 (DPPR_DPE(7) | DPPR_DPS(7, 1))109#define DPPR_BPP32_P2 (DPPR_DPE(8) | DPPR_DPS(8, 2))110#define DPPR_BPP32 (DPPR_BPP32_P1 | DPPR_BPP32_P2) /* plane1 & 2 */111 112#define DEFR 0x00020113#define DEFR_CODE (0x7773 << 16)114#define DEFR_EXSL (1 << 12)115#define DEFR_EXVL (1 << 11)116#define DEFR_EXUP (1 << 5)117#define DEFR_VCUP (1 << 4)118#define DEFR_DEFE (1 << 0)119 120#define DAPCR 0x00024121#define DAPCR_CODE (0x7773 << 16)122#define DAPCR_AP2E (1 << 4)123#define DAPCR_AP1E (1 << 0)124 125#define DCPCR 0x00028126#define DCPCR_CODE (0x7773 << 16)127#define DCPCR_CA2B (1 << 13)128#define DCPCR_CD2F (1 << 12)129#define DCPCR_DC2E (1 << 8)130#define DCPCR_CAB (1 << 5)131#define DCPCR_CDF (1 << 4)132#define DCPCR_DCE (1 << 0)133 134#define DEFR2 0x00034135#define DEFR2_CODE (0x7775 << 16)136#define DEFR2_DEFE2G (1 << 0)137 138#define DEFR3 0x00038139#define DEFR3_CODE (0x7776 << 16)140#define DEFR3_EVDA (1 << 14)141#define DEFR3_EVDM_1 (1 << 12)142#define DEFR3_EVDM_2 (2 << 12)143#define DEFR3_EVDM_3 (3 << 12)144#define DEFR3_VMSM2_EMA (1 << 6)145#define DEFR3_VMSM1_ENA (1 << 4)146#define DEFR3_DEFE3 (1 << 0)147 148#define DEFR4 0x0003c149#define DEFR4_CODE (0x7777 << 16)150#define DEFR4_LRUO (1 << 5)151#define DEFR4_SPCE (1 << 4)152 153#define DVCSR 0x000d0154#define DVCSR_VCnFB2_DSA0(n) (0 << ((n)*2+16))155#define DVCSR_VCnFB2_DSA1(n) (1 << ((n)*2+16))156#define DVCSR_VCnFB2_DSA2(n) (2 << ((n)*2+16))157#define DVCSR_VCnFB2_INIT(n) (3 << ((n)*2+16))158#define DVCSR_VCnFB2_MASK(n) (3 << ((n)*2+16))159#define DVCSR_VCnFB_DSA0(n) (0 << ((n)*2))160#define DVCSR_VCnFB_DSA1(n) (1 << ((n)*2))161#define DVCSR_VCnFB_DSA2(n) (2 << ((n)*2))162#define DVCSR_VCnFB_INIT(n) (3 << ((n)*2))163#define DVCSR_VCnFB_MASK(n) (3 << ((n)*2))164 165#define DEFR5 0x000e0166#define DEFR5_CODE (0x66 << 24)167#define DEFR5_YCRGB2_DIS (0 << 14)168#define DEFR5_YCRGB2_PRI1 (1 << 14)169#define DEFR5_YCRGB2_PRI2 (2 << 14)170#define DEFR5_YCRGB2_PRI3 (3 << 14)171#define DEFR5_YCRGB2_MASK (3 << 14)172#define DEFR5_YCRGB1_DIS (0 << 12)173#define DEFR5_YCRGB1_PRI1 (1 << 12)174#define DEFR5_YCRGB1_PRI2 (2 << 12)175#define DEFR5_YCRGB1_PRI3 (3 << 12)176#define DEFR5_YCRGB1_MASK (3 << 12)177#define DEFR5_DEFE5 (1 << 0)178 179#define DDLTR 0x000e4180#define DDLTR_CODE (0x7766 << 16)181#define DDLTR_DLAR2 (1 << 6)182#define DDLTR_DLAY2 (1 << 5)183#define DDLTR_DLAY1 (1 << 1)184 185#define DEFR6 0x000e8186#define DEFR6_CODE (0x7778 << 16)187#define DEFR6_ODPM12_DSMR (0 << 10)188#define DEFR6_ODPM12_DISP (2 << 10)189#define DEFR6_ODPM12_CDE (3 << 10)190#define DEFR6_ODPM12_MASK (3 << 10)191#define DEFR6_ODPM02_DSMR (0 << 8)192#define DEFR6_ODPM02_DISP (2 << 8)193#define DEFR6_ODPM02_CDE (3 << 8)194#define DEFR6_ODPM02_MASK (3 << 8)195#define DEFR6_TCNE1 (1 << 6)196#define DEFR6_TCNE0 (1 << 4)197#define DEFR6_MLOS1 (1 << 2)198#define DEFR6_DEFAULT (DEFR6_CODE | DEFR6_TCNE1)199 200#define DEFR7 0x000ec201#define DEFR7_CODE (0x7779 << 16)202#define DEFR7_CMME1 BIT(6)203#define DEFR7_CMME0 BIT(4)204 205/* -----------------------------------------------------------------------------206 * R8A7790-only Control Registers207 */208 209#define DD1SSR 0x20008210#define DD1SSR_TVR (1 << 15)211#define DD1SSR_FRM (1 << 14)212#define DD1SSR_BUF (1 << 12)213#define DD1SSR_VBK (1 << 11)214#define DD1SSR_RINT (1 << 9)215#define DD1SSR_HBK (1 << 8)216#define DD1SSR_ADC(n) (1 << ((n)-1))217 218#define DD1SRCR 0x2000c219#define DD1SRCR_TVR (1 << 15)220#define DD1SRCR_FRM (1 << 14)221#define DD1SRCR_BUF (1 << 12)222#define DD1SRCR_VBK (1 << 11)223#define DD1SRCR_RINT (1 << 9)224#define DD1SRCR_HBK (1 << 8)225#define DD1SRCR_ADC(n) (1 << ((n)-1))226 227#define DD1IER 0x20010228#define DD1IER_TVR (1 << 15)229#define DD1IER_FRM (1 << 14)230#define DD1IER_BUF (1 << 12)231#define DD1IER_VBK (1 << 11)232#define DD1IER_RINT (1 << 9)233#define DD1IER_HBK (1 << 8)234#define DD1IER_ADC(n) (1 << ((n)-1))235 236#define DEFR8 0x20020237#define DEFR8_CODE (0x7790 << 16)238#define DEFR8_VSCS (1 << 6)239#define DEFR8_DRGBS_DU(n) ((n) << 4)240#define DEFR8_DRGBS_MASK (3 << 4)241#define DEFR8_DEFE8 (1 << 0)242 243#define DOFLR 0x20024244#define DOFLR_CODE (0x7790 << 16)245#define DOFLR_HSYCFL1 (1 << 13)246#define DOFLR_VSYCFL1 (1 << 12)247#define DOFLR_ODDFL1 (1 << 11)248#define DOFLR_DISPFL1 (1 << 10)249#define DOFLR_CDEFL1 (1 << 9)250#define DOFLR_RGBFL1 (1 << 8)251#define DOFLR_HSYCFL0 (1 << 5)252#define DOFLR_VSYCFL0 (1 << 4)253#define DOFLR_ODDFL0 (1 << 3)254#define DOFLR_DISPFL0 (1 << 2)255#define DOFLR_CDEFL0 (1 << 1)256#define DOFLR_RGBFL0 (1 << 0)257 258#define DIDSR 0x20028259#define DIDSR_CODE (0x7790 << 16)260#define DIDSR_LDCS_DCLKIN(n) (0 << (8 + (n) * 2))261#define DIDSR_LDCS_DSI(n) (2 << (8 + (n) * 2)) /* V3U only */262#define DIDSR_LDCS_LVDS0(n) (2 << (8 + (n) * 2))263#define DIDSR_LDCS_LVDS1(n) (3 << (8 + (n) * 2))264#define DIDSR_LDCS_MASK(n) (3 << (8 + (n) * 2))265#define DIDSR_PDCS_CLK(n, clk) (clk << ((n) * 2))266#define DIDSR_PDCS_MASK(n) (3 << ((n) * 2))267 268#define DEFR10 0x20038269#define DEFR10_CODE (0x7795 << 16)270#define DEFR10_VSPF1_RGB (0 << 14)271#define DEFR10_VSPF1_YC (1 << 14)272#define DEFR10_DOCF1_RGB (0 << 12)273#define DEFR10_DOCF1_YC (1 << 12)274#define DEFR10_YCDF0_YCBCR444 (0 << 11)275#define DEFR10_YCDF0_YCBCR422 (1 << 11)276#define DEFR10_VSPF0_RGB (0 << 10)277#define DEFR10_VSPF0_YC (1 << 10)278#define DEFR10_DOCF0_RGB (0 << 8)279#define DEFR10_DOCF0_YC (1 << 8)280#define DEFR10_TSEL_H3_TCON1 (0 << 1) /* DEFR102 register only (DU2/DU3) */281#define DEFR10_DEFE10 (1 << 0)282 283#define DPLLCR 0x20044284#define DPLLCR_CODE (0x95 << 24)285#define DPLLCR_PLCS1 (1 << 23)286#define DPLLCR_PLCS0 (1 << 21)287#define DPLLCR_CLKE (1 << 18)288#define DPLLCR_FDPLL(n) ((n) << 12)289#define DPLLCR_N(n) ((n) << 5)290#define DPLLCR_M(n) ((n) << 3)291#define DPLLCR_STBY (1 << 2)292#define DPLLCR_INCS_DOTCLKIN0 (0 << 0)293#define DPLLCR_INCS_DOTCLKIN1 (1 << 1)294 295#define DPLLC2R 0x20048296#define DPLLC2R_CODE (0x95 << 24)297#define DPLLC2R_SELC (1 << 12)298#define DPLLC2R_M(n) ((n) << 8)299#define DPLLC2R_FDPLL(n) ((n) << 0)300 301/* -----------------------------------------------------------------------------302 * Display Timing Generation Registers303 */304 305#define HDSR 0x00040306#define HDER 0x00044307#define VDSR 0x00048308#define VDER 0x0004c309#define HCR 0x00050310#define HSWR 0x00054311#define VCR 0x00058312#define VSPR 0x0005c313#define EQWR 0x00060314#define SPWR 0x00064315#define CLAMPSR 0x00070316#define CLAMPWR 0x00074317#define DESR 0x00078318#define DEWR 0x0007c319 320/* -----------------------------------------------------------------------------321 * Display Attribute Registers322 */323 324#define CP1TR 0x00080325#define CP2TR 0x00084326#define CP3TR 0x00088327#define CP4TR 0x0008c328 329#define DOOR 0x00090330#define DOOR_RGB(r, g, b) (((r) << 18) | ((g) << 10) | ((b) << 2))331#define CDER 0x00094332#define CDER_RGB(r, g, b) (((r) << 18) | ((g) << 10) | ((b) << 2))333#define BPOR 0x00098334#define BPOR_RGB(r, g, b) (((r) << 18) | ((g) << 10) | ((b) << 2))335 336#define RINTOFSR 0x0009c337 338#define DSHPR 0x000c8339#define DSHPR_CODE (0x7776 << 16)340#define DSHPR_PRIH (0xa << 4)341#define DSHPR_PRIL_BPP16 (0x8 << 0)342#define DSHPR_PRIL_BPP32 (0x9 << 0)343 344/* -----------------------------------------------------------------------------345 * Display Plane Registers346 */347 348#define PLANE_OFF 0x00100349 350#define PnMR 0x00100 /* plane 1 */351#define PnMR_VISL_VIN0 (0 << 26) /* use Video Input 0 */352#define PnMR_VISL_VIN1 (1 << 26) /* use Video Input 1 */353#define PnMR_VISL_VIN2 (2 << 26) /* use Video Input 2 */354#define PnMR_VISL_VIN3 (3 << 26) /* use Video Input 3 */355#define PnMR_YCDF_YUYV (1 << 20) /* YUYV format */356#define PnMR_TC_R (0 << 17) /* Tranparent color is PnTC1R */357#define PnMR_TC_CP (1 << 17) /* Tranparent color is color palette */358#define PnMR_WAE (1 << 16) /* Wrap around Enable */359#define PnMR_SPIM_TP (0 << 12) /* Transparent Color */360#define PnMR_SPIM_ALP (1 << 12) /* Alpha Blending */361#define PnMR_SPIM_EOR (2 << 12) /* EOR */362#define PnMR_SPIM_TP_OFF (1 << 14) /* No Transparent Color */363#define PnMR_CPSL_CP1 (0 << 8) /* Color Palette selected 1 */364#define PnMR_CPSL_CP2 (1 << 8) /* Color Palette selected 2 */365#define PnMR_CPSL_CP3 (2 << 8) /* Color Palette selected 3 */366#define PnMR_CPSL_CP4 (3 << 8) /* Color Palette selected 4 */367#define PnMR_DC (1 << 7) /* Display Area Change */368#define PnMR_BM_MD (0 << 4) /* Manual Display Change Mode */369#define PnMR_BM_AR (1 << 4) /* Auto Rendering Mode */370#define PnMR_BM_AD (2 << 4) /* Auto Display Change Mode */371#define PnMR_BM_VC (3 << 4) /* Video Capture Mode */372#define PnMR_DDDF_8BPP (0 << 0) /* 8bit */373#define PnMR_DDDF_16BPP (1 << 0) /* 16bit or 32bit */374#define PnMR_DDDF_ARGB (2 << 0) /* ARGB */375#define PnMR_DDDF_YC (3 << 0) /* YC */376#define PnMR_DDDF_MASK (3 << 0)377 378#define PnMWR 0x00104379 380#define PnALPHAR 0x00108381#define PnALPHAR_ABIT_1 (0 << 12)382#define PnALPHAR_ABIT_0 (1 << 12)383#define PnALPHAR_ABIT_X (2 << 12)384 385#define PnDSXR 0x00110386#define PnDSYR 0x00114387#define PnDPXR 0x00118388#define PnDPYR 0x0011c389 390#define PnDSA0R 0x00120391#define PnDSA1R 0x00124392#define PnDSA2R 0x00128393#define PnDSA_MASK 0xfffffff0394 395#define PnSPXR 0x00130396#define PnSPYR 0x00134397#define PnWASPR 0x00138398#define PnWAMWR 0x0013c399 400#define PnBTR 0x00140401 402#define PnTC1R 0x00144403#define PnTC2R 0x00148404#define PnTC3R 0x0014c405#define PnTC3R_CODE (0x66 << 24)406 407#define PnMLR 0x00150408 409#define PnSWAPR 0x00180410#define PnSWAPR_DIGN (1 << 4)411#define PnSWAPR_SPQW (1 << 3)412#define PnSWAPR_SPLW (1 << 2)413#define PnSWAPR_SPWD (1 << 1)414#define PnSWAPR_SPBY (1 << 0)415 416#define PnDDCR 0x00184417#define PnDDCR_CODE (0x7775 << 16)418#define PnDDCR_LRGB1 (1 << 11)419#define PnDDCR_LRGB0 (1 << 10)420 421#define PnDDCR2 0x00188422#define PnDDCR2_CODE (0x7776 << 16)423#define PnDDCR2_NV21 (1 << 5)424#define PnDDCR2_Y420 (1 << 4)425#define PnDDCR2_DIVU (1 << 1)426#define PnDDCR2_DIVY (1 << 0)427 428#define PnDDCR4 0x00190429#define PnDDCR4_CODE (0x7766 << 16)430#define PnDDCR4_VSPS (1 << 13)431#define PnDDCR4_SDFS_RGB (0 << 4)432#define PnDDCR4_SDFS_YC (5 << 4)433#define PnDDCR4_SDFS_MASK (7 << 4)434#define PnDDCR4_EDF_NONE (0 << 0)435#define PnDDCR4_EDF_ARGB8888 (1 << 0)436#define PnDDCR4_EDF_RGB888 (2 << 0)437#define PnDDCR4_EDF_RGB666 (3 << 0)438#define PnDDCR4_EDF_MASK (7 << 0)439 440#define APnMR 0x0a100441#define APnMR_WAE (1 << 16) /* Wrap around Enable */442#define APnMR_DC (1 << 7) /* Display Area Change */443#define APnMR_BM_MD (0 << 4) /* Manual Display Change Mode */444#define APnMR_BM_AD (2 << 4) /* Auto Display Change Mode */445 446#define APnMWR 0x0a104447 448#define APnDSXR 0x0a110449#define APnDSYR 0x0a114450#define APnDPXR 0x0a118451#define APnDPYR 0x0a11c452 453#define APnDSA0R 0x0a120454#define APnDSA1R 0x0a124455#define APnDSA2R 0x0a128456 457#define APnSPXR 0x0a130458#define APnSPYR 0x0a134459#define APnWASPR 0x0a138460#define APnWAMWR 0x0a13c461 462#define APnBTR 0x0a140463 464#define APnMLR 0x0a150465#define APnSWAPR 0x0a180466 467/* -----------------------------------------------------------------------------468 * Display Capture Registers469 */470 471#define DCMR 0x0c100472#define DCMWR 0x0c104473#define DCSAR 0x0c120474#define DCMLR 0x0c150475 476/* -----------------------------------------------------------------------------477 * Color Palette Registers478 */479 480#define CP1_000R 0x01000481#define CP1_255R 0x013fc482#define CP2_000R 0x02000483#define CP2_255R 0x023fc484#define CP3_000R 0x03000485#define CP3_255R 0x033fc486#define CP4_000R 0x04000487#define CP4_255R 0x043fc488 489/* -----------------------------------------------------------------------------490 * External Synchronization Control Registers491 */492 493#define ESCR02 0x10000494#define ESCR13 0x01000495#define ESCR_DCLKOINV (1 << 25)496#define ESCR_DCLKSEL_DCLKIN (0 << 20)497#define ESCR_DCLKSEL_CLKS (1 << 20)498#define ESCR_DCLKSEL_MASK (1 << 20)499#define ESCR_DCLKDIS (1 << 16)500#define ESCR_SYNCSEL_OFF (0 << 8)501#define ESCR_SYNCSEL_EXVSYNC (2 << 8)502#define ESCR_SYNCSEL_EXHSYNC (3 << 8)503#define ESCR_FRQSEL_MASK (0x3f << 0)504 505#define OTAR02 0x10004506#define OTAR13 0x01004507 508/* -----------------------------------------------------------------------------509 * Dual Display Output Control Registers510 */511 512#define DORCR 0x11000513#define DORCR_PG1T (1 << 30)514#define DORCR_DK1S (1 << 28)515#define DORCR_PG1D_DS0 (0 << 24)516#define DORCR_PG1D_DS1 (1 << 24)517#define DORCR_PG1D_FIX0 (2 << 24)518#define DORCR_PG1D_DOOR (3 << 24)519#define DORCR_PG1D_MASK (3 << 24)520#define DORCR_DR0D (1 << 21)521#define DORCR_PG0D_DS0 (0 << 16)522#define DORCR_PG0D_DS1 (1 << 16)523#define DORCR_PG0D_FIX0 (2 << 16)524#define DORCR_PG0D_DOOR (3 << 16)525#define DORCR_PG0D_MASK (3 << 16)526#define DORCR_RGPV (1 << 4)527#define DORCR_DPRS (1 << 0)528 529#define DPTSR 0x11004530#define DPTSR_PnDK(n) (1 << ((n) + 16))531#define DPTSR_PnTS(n) (1 << (n))532 533#define DAPTSR 0x11008534#define DAPTSR_APnDK(n) (1 << ((n) + 16))535#define DAPTSR_APnTS(n) (1 << (n))536 537#define DS1PR 0x11020538#define DS2PR 0x11024539 540/* -----------------------------------------------------------------------------541 * YC-RGB Conversion Coefficient Registers542 */543 544#define YNCR 0x11080545#define YNOR 0x11084546#define CRNOR 0x11088547#define CBNOR 0x1108c548#define RCRCR 0x11090549#define GCRCR 0x11094550#define GCBCR 0x11098551#define BCBCR 0x1109c552 553#endif /* __RCAR_DU_REGS_H__ */554