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1/* SPDX-License-Identifier: GPL-2.0+ */2/*3 * RZ/G2L Display Unit DRM driver4 *5 * Copyright (C) 2023 Renesas Electronics Corporation6 *7 * Based on rcar_du_drv.h8 */9 10#ifndef __RZG2L_DU_DRV_H__11#define __RZG2L_DU_DRV_H__12 13#include <linux/kernel.h>14 15#include <drm/drm_device.h>16 17#include "rzg2l_du_crtc.h"18#include "rzg2l_du_vsp.h"19 20struct device;21struct drm_property;22 23enum rzg2l_du_output {24 RZG2L_DU_OUTPUT_DSI0,25 RZG2L_DU_OUTPUT_DPAD0,26 RZG2L_DU_OUTPUT_MAX,27};28 29/*30 * struct rzg2l_du_output_routing - Output routing specification31 * @possible_outputs: bitmask of possible outputs32 * @port: device tree port number corresponding to this output route33 *34 * The DU has 2 possible outputs (DPAD0, DSI0). Output routing data35 * specify the valid SoC outputs, which CRTC can drive the output, and the type36 * of in-SoC encoder for the output.37 */38struct rzg2l_du_output_routing {39 unsigned int possible_outputs;40 unsigned int port;41};42 43/*44 * struct rzg2l_du_device_info - DU model-specific information45 * @channels_mask: bit mask of available DU channels46 * @routes: array of CRTC to output routes, indexed by output (RZG2L_DU_OUTPUT_*)47 */48struct rzg2l_du_device_info {49 unsigned int channels_mask;50 struct rzg2l_du_output_routing routes[RZG2L_DU_OUTPUT_MAX];51};52 53#define RZG2L_DU_MAX_CRTCS 154#define RZG2L_DU_MAX_VSPS 155#define RZG2L_DU_MAX_DSI 156 57struct rzg2l_du_device {58 struct device *dev;59 const struct rzg2l_du_device_info *info;60 61 void __iomem *mmio;62 63 struct drm_device ddev;64 65 struct rzg2l_du_crtc crtcs[RZG2L_DU_MAX_CRTCS];66 unsigned int num_crtcs;67 68 struct rzg2l_du_vsp vsps[RZG2L_DU_MAX_VSPS];69};70 71static inline struct rzg2l_du_device *to_rzg2l_du_device(struct drm_device *dev)72{73 return container_of(dev, struct rzg2l_du_device, ddev);74}75 76const char *rzg2l_du_output_name(enum rzg2l_du_output output);77 78#endif /* __RZG2L_DU_DRV_H__ */79