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1// SPDX-License-Identifier: GPL-2.0+2/*3 * RZ/G2L Display Unit Mode Setting4 *5 * Copyright (C) 2023 Renesas Electronics Corporation6 *7 * Based on rcar_du_kms.c8 */9 10#include <drm/drm_atomic.h>11#include <drm/drm_atomic_helper.h>12#include <drm/drm_crtc.h>13#include <drm/drm_device.h>14#include <drm/drm_framebuffer.h>15#include <drm/drm_gem_dma_helper.h>16#include <drm/drm_gem_framebuffer_helper.h>17#include <drm/drm_managed.h>18#include <drm/drm_probe_helper.h>19#include <drm/drm_vblank.h>20 21#include <linux/device.h>22#include <linux/of.h>23#include <linux/of_graph.h>24#include <linux/of_platform.h>25#include <linux/platform_device.h>26 27#include "rzg2l_du_crtc.h"28#include "rzg2l_du_drv.h"29#include "rzg2l_du_encoder.h"30#include "rzg2l_du_kms.h"31#include "rzg2l_du_vsp.h"32 33/* -----------------------------------------------------------------------------34 * Format helpers35 */36 37static const struct rzg2l_du_format_info rzg2l_du_format_infos[] = {38 {39 .fourcc = DRM_FORMAT_XRGB8888,40 .v4l2 = V4L2_PIX_FMT_XBGR32,41 .bpp = 32,42 .planes = 1,43 .hsub = 1,44 }, {45 .fourcc = DRM_FORMAT_ARGB8888,46 .v4l2 = V4L2_PIX_FMT_ABGR32,47 .bpp = 32,48 .planes = 1,49 .hsub = 1,50 }, {51 .fourcc = DRM_FORMAT_RGB888,52 .v4l2 = V4L2_PIX_FMT_BGR24,53 .bpp = 24,54 .planes = 1,55 .hsub = 1,56 }57};58 59const struct rzg2l_du_format_info *rzg2l_du_format_info(u32 fourcc)60{61 unsigned int i;62 63 for (i = 0; i < ARRAY_SIZE(rzg2l_du_format_infos); ++i) {64 if (rzg2l_du_format_infos[i].fourcc == fourcc)65 return &rzg2l_du_format_infos[i];66 }67 68 return NULL;69}70 71/* -----------------------------------------------------------------------------72 * Frame buffer73 */74 75int rzg2l_du_dumb_create(struct drm_file *file, struct drm_device *dev,76 struct drm_mode_create_dumb *args)77{78 unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);79 unsigned int align = 16 * args->bpp / 8;80 81 args->pitch = roundup(min_pitch, align);82 83 return drm_gem_dma_dumb_create_internal(file, dev, args);84}85 86static struct drm_framebuffer *87rzg2l_du_fb_create(struct drm_device *dev, struct drm_file *file_priv,88 const struct drm_mode_fb_cmd2 *mode_cmd)89{90 const struct rzg2l_du_format_info *format;91 unsigned int max_pitch;92 93 format = rzg2l_du_format_info(mode_cmd->pixel_format);94 if (!format) {95 dev_dbg(dev->dev, "unsupported pixel format %p4cc\n",96 &mode_cmd->pixel_format);97 return ERR_PTR(-EINVAL);98 }99 100 /*101 * On RZ/G2L the memory interface is handled by the VSP that limits the102 * pitch to 65535 bytes.103 */104 max_pitch = 65535;105 if (mode_cmd->pitches[0] > max_pitch) {106 dev_dbg(dev->dev, "invalid pitch value %u\n",107 mode_cmd->pitches[0]);108 return ERR_PTR(-EINVAL);109 }110 111 return drm_gem_fb_create(dev, file_priv, mode_cmd);112}113 114/* -----------------------------------------------------------------------------115 * Initialization116 */117 118static const struct drm_mode_config_helper_funcs rzg2l_du_mode_config_helper = {119 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,120};121 122static const struct drm_mode_config_funcs rzg2l_du_mode_config_funcs = {123 .fb_create = rzg2l_du_fb_create,124 .atomic_check = drm_atomic_helper_check,125 .atomic_commit = drm_atomic_helper_commit,126};127 128static int rzg2l_du_encoders_init_one(struct rzg2l_du_device *rcdu,129 enum rzg2l_du_output output,130 struct of_endpoint *ep)131{132 struct device_node *entity;133 int ret;134 135 /* Locate the connected entity and initialize the encoder. */136 entity = of_graph_get_remote_port_parent(ep->local_node);137 if (!entity) {138 dev_dbg(rcdu->dev, "unconnected endpoint %pOF, skipping\n",139 ep->local_node);140 return -ENODEV;141 }142 143 if (!of_device_is_available(entity)) {144 dev_dbg(rcdu->dev,145 "connected entity %pOF is disabled, skipping\n",146 entity);147 of_node_put(entity);148 return -ENODEV;149 }150 151 ret = rzg2l_du_encoder_init(rcdu, output, entity);152 if (ret && ret != -EPROBE_DEFER && ret != -ENOLINK)153 dev_warn(rcdu->dev,154 "failed to initialize encoder %pOF on output %s (%d), skipping\n",155 entity, rzg2l_du_output_name(output), ret);156 157 of_node_put(entity);158 159 return ret;160}161 162static int rzg2l_du_encoders_init(struct rzg2l_du_device *rcdu)163{164 struct device_node *np = rcdu->dev->of_node;165 struct device_node *ep_node;166 unsigned int num_encoders = 0;167 168 /*169 * Iterate over the endpoints and create one encoder for each output170 * pipeline.171 */172 for_each_endpoint_of_node(np, ep_node) {173 enum rzg2l_du_output output;174 struct of_endpoint ep;175 unsigned int i;176 int ret;177 178 ret = of_graph_parse_endpoint(ep_node, &ep);179 if (ret < 0) {180 of_node_put(ep_node);181 return ret;182 }183 184 /* Find the output route corresponding to the port number. */185 for (i = 0; i < RZG2L_DU_OUTPUT_MAX; ++i) {186 if (rcdu->info->routes[i].possible_outputs &&187 rcdu->info->routes[i].port == ep.port) {188 output = i;189 break;190 }191 }192 193 if (i == RZG2L_DU_OUTPUT_MAX) {194 dev_warn(rcdu->dev,195 "port %u references unexisting output, skipping\n",196 ep.port);197 continue;198 }199 200 /* Process the output pipeline. */201 ret = rzg2l_du_encoders_init_one(rcdu, output, &ep);202 if (ret < 0) {203 if (ret == -EPROBE_DEFER) {204 of_node_put(ep_node);205 return ret;206 }207 208 continue;209 }210 211 num_encoders++;212 }213 214 return num_encoders;215}216 217static int rzg2l_du_vsps_init(struct rzg2l_du_device *rcdu)218{219 const struct device_node *np = rcdu->dev->of_node;220 const char *vsps_prop_name = "renesas,vsps";221 struct of_phandle_args args;222 struct {223 struct device_node *np;224 unsigned int crtcs_mask;225 } vsps[RZG2L_DU_MAX_VSPS] = { { NULL, }, };226 unsigned int vsps_count = 0;227 unsigned int cells;228 unsigned int i;229 int ret;230 231 /*232 * First parse the DT vsps property to populate the list of VSPs. Each233 * entry contains a pointer to the VSP DT node and a bitmask of the234 * connected DU CRTCs.235 */236 ret = of_property_count_u32_elems(np, vsps_prop_name);237 cells = ret / rcdu->num_crtcs - 1;238 if (cells != 1)239 return -EINVAL;240 241 for (i = 0; i < rcdu->num_crtcs; ++i) {242 unsigned int j;243 244 ret = of_parse_phandle_with_fixed_args(np, vsps_prop_name,245 cells, i, &args);246 if (ret < 0)247 goto done;248 249 /*250 * Add the VSP to the list or update the corresponding existing251 * entry if the VSP has already been added.252 */253 for (j = 0; j < vsps_count; ++j) {254 if (vsps[j].np == args.np)255 break;256 }257 258 if (j < vsps_count)259 of_node_put(args.np);260 else261 vsps[vsps_count++].np = args.np;262 263 vsps[j].crtcs_mask |= BIT(i);264 265 /*266 * Store the VSP pointer and pipe index in the CRTC. If the267 * second cell of the 'renesas,vsps' specifier isn't present,268 * default to 0.269 */270 rcdu->crtcs[i].vsp = &rcdu->vsps[j];271 rcdu->crtcs[i].vsp_pipe = cells >= 1 ? args.args[0] : 0;272 }273 274 /*275 * Then initialize all the VSPs from the node pointers and CRTCs bitmask276 * computed previously.277 */278 for (i = 0; i < vsps_count; ++i) {279 struct rzg2l_du_vsp *vsp = &rcdu->vsps[i];280 281 vsp->index = i;282 vsp->dev = rcdu;283 284 ret = rzg2l_du_vsp_init(vsp, vsps[i].np, vsps[i].crtcs_mask);285 if (ret)286 goto done;287 }288 289done:290 for (i = 0; i < ARRAY_SIZE(vsps); ++i)291 of_node_put(vsps[i].np);292 293 return ret;294}295 296int rzg2l_du_modeset_init(struct rzg2l_du_device *rcdu)297{298 struct drm_device *dev = &rcdu->ddev;299 struct drm_encoder *encoder;300 unsigned int num_encoders;301 int ret;302 303 ret = drmm_mode_config_init(dev);304 if (ret)305 return ret;306 307 dev->mode_config.min_width = 0;308 dev->mode_config.min_height = 0;309 dev->mode_config.normalize_zpos = true;310 dev->mode_config.funcs = &rzg2l_du_mode_config_funcs;311 dev->mode_config.helper_private = &rzg2l_du_mode_config_helper;312 313 /*314 * The RZ DU uses the VSP1 for memory access, and is limited315 * to frame sizes of 1920x1080.316 */317 dev->mode_config.max_width = 1920;318 dev->mode_config.max_height = 1080;319 320 rcdu->num_crtcs = hweight8(rcdu->info->channels_mask);321 322 /*323 * Initialize vertical blanking interrupts handling. Start with vblank324 * disabled for all CRTCs.325 */326 ret = drm_vblank_init(dev, rcdu->num_crtcs);327 if (ret < 0)328 return ret;329 330 /* Initialize the compositors. */331 ret = rzg2l_du_vsps_init(rcdu);332 if (ret < 0)333 return ret;334 335 /* Create the CRTCs. */336 ret = rzg2l_du_crtc_create(rcdu);337 if (ret < 0)338 return ret;339 340 /* Initialize the encoders. */341 ret = rzg2l_du_encoders_init(rcdu);342 if (ret < 0)343 return dev_err_probe(rcdu->dev, ret,344 "failed to initialize encoders\n");345 346 if (ret == 0) {347 dev_err(rcdu->dev, "error: no encoder could be initialized\n");348 return -EINVAL;349 }350 351 num_encoders = ret;352 353 /*354 * Set the possible CRTCs and possible clones. There's always at least355 * one way for all encoders to clone each other, set all bits in the356 * possible clones field.357 */358 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {359 struct rzg2l_du_encoder *renc = to_rzg2l_encoder(encoder);360 const struct rzg2l_du_output_routing *route =361 &rcdu->info->routes[renc->output];362 363 encoder->possible_crtcs = route->possible_outputs;364 encoder->possible_clones = (1 << num_encoders) - 1;365 }366 367 drm_mode_config_reset(dev);368 369 drm_kms_helper_poll_init(dev);370 371 return 0;372}373