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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd4 * Author: Chris Zhong <zyw@rock-chips.com>5 */6 7#ifndef _CDN_DP_REG_H8#define _CDN_DP_REG_H9 10#include <linux/bitops.h>11 12#define ADDR_IMEM 0x1000013#define ADDR_DMEM 0x2000014 15/* APB CFG addr */16#define APB_CTRL 017#define XT_INT_CTRL 0x0418#define MAILBOX_FULL_ADDR 0x0819#define MAILBOX_EMPTY_ADDR 0x0c20#define MAILBOX0_WR_DATA 0x1021#define MAILBOX0_RD_DATA 0x1422#define KEEP_ALIVE 0x1823#define VER_L 0x1c24#define VER_H 0x2025#define VER_LIB_L_ADDR 0x2426#define VER_LIB_H_ADDR 0x2827#define SW_DEBUG_L 0x2c28#define SW_DEBUG_H 0x3029#define MAILBOX_INT_MASK 0x3430#define MAILBOX_INT_STATUS 0x3831#define SW_CLK_L 0x3c32#define SW_CLK_H 0x4033#define SW_EVENTS0 0x4434#define SW_EVENTS1 0x4835#define SW_EVENTS2 0x4c36#define SW_EVENTS3 0x5037#define XT_OCD_CTRL 0x6038#define APB_INT_MASK 0x6c39#define APB_STATUS_MASK 0x7040 41/* audio decoder addr */42#define AUDIO_SRC_CNTL 0x3000043#define AUDIO_SRC_CNFG 0x3000444#define COM_CH_STTS_BITS 0x3000845#define STTS_BIT_CH(x) (0x3000c + ((x) << 2))46#define SPDIF_CTRL_ADDR 0x3004c47#define SPDIF_CH1_CS_3100_ADDR 0x3005048#define SPDIF_CH1_CS_6332_ADDR 0x3005449#define SPDIF_CH1_CS_9564_ADDR 0x3005850#define SPDIF_CH1_CS_12796_ADDR 0x3005c51#define SPDIF_CH1_CS_159128_ADDR 0x3006052#define SPDIF_CH1_CS_191160_ADDR 0x3006453#define SPDIF_CH2_CS_3100_ADDR 0x3006854#define SPDIF_CH2_CS_6332_ADDR 0x3006c55#define SPDIF_CH2_CS_9564_ADDR 0x3007056#define SPDIF_CH2_CS_12796_ADDR 0x3007457#define SPDIF_CH2_CS_159128_ADDR 0x3007858#define SPDIF_CH2_CS_191160_ADDR 0x3007c59#define SMPL2PKT_CNTL 0x3008060#define SMPL2PKT_CNFG 0x3008461#define FIFO_CNTL 0x3008862#define FIFO_STTS 0x3008c63 64/* source pif addr */65#define SOURCE_PIF_WR_ADDR 0x3080066#define SOURCE_PIF_WR_REQ 0x3080467#define SOURCE_PIF_RD_ADDR 0x3080868#define SOURCE_PIF_RD_REQ 0x3080c69#define SOURCE_PIF_DATA_WR 0x3081070#define SOURCE_PIF_DATA_RD 0x3081471#define SOURCE_PIF_FIFO1_FLUSH 0x3081872#define SOURCE_PIF_FIFO2_FLUSH 0x3081c73#define SOURCE_PIF_STATUS 0x3082074#define SOURCE_PIF_INTERRUPT_SOURCE 0x3082475#define SOURCE_PIF_INTERRUPT_MASK 0x3082876#define SOURCE_PIF_PKT_ALLOC_REG 0x3082c77#define SOURCE_PIF_PKT_ALLOC_WR_EN 0x3083078#define SOURCE_PIF_SW_RESET 0x3083479 80/* bellow registers need access by mailbox */81/* source car addr */82#define SOURCE_HDTX_CAR 0x090083#define SOURCE_DPTX_CAR 0x090484#define SOURCE_PHY_CAR 0x090885#define SOURCE_CEC_CAR 0x090c86#define SOURCE_CBUS_CAR 0x091087#define SOURCE_PKT_CAR 0x091888#define SOURCE_AIF_CAR 0x091c89#define SOURCE_CIPHER_CAR 0x092090#define SOURCE_CRYPTO_CAR 0x092491 92/* clock meters addr */93#define CM_CTRL 0x0a0094#define CM_I2S_CTRL 0x0a0495#define CM_SPDIF_CTRL 0x0a0896#define CM_VID_CTRL 0x0a0c97#define CM_LANE_CTRL 0x0a1098#define I2S_NM_STABLE 0x0a1499#define I2S_NCTS_STABLE 0x0a18100#define SPDIF_NM_STABLE 0x0a1c101#define SPDIF_NCTS_STABLE 0x0a20102#define NMVID_MEAS_STABLE 0x0a24103#define I2S_MEAS 0x0a40104#define SPDIF_MEAS 0x0a80105#define NMVID_MEAS 0x0ac0106 107/* source vif addr */108#define BND_HSYNC2VSYNC 0x0b00109#define HSYNC2VSYNC_F1_L1 0x0b04110#define HSYNC2VSYNC_F2_L1 0x0b08111#define HSYNC2VSYNC_STATUS 0x0b0c112#define HSYNC2VSYNC_POL_CTRL 0x0b10113 114/* dptx phy addr */115#define DP_TX_PHY_CONFIG_REG 0x2000116#define DP_TX_PHY_SW_RESET 0x2004117#define DP_TX_PHY_SCRAMBLER_SEED 0x2008118#define DP_TX_PHY_TRAINING_01_04 0x200c119#define DP_TX_PHY_TRAINING_05_08 0x2010120#define DP_TX_PHY_TRAINING_09_10 0x2014121#define TEST_COR 0x23fc122 123/* dptx hpd addr */124#define HPD_IRQ_DET_MIN_TIMER 0x2100125#define HPD_IRQ_DET_MAX_TIMER 0x2104126#define HPD_UNPLGED_DET_MIN_TIMER 0x2108127#define HPD_STABLE_TIMER 0x210c128#define HPD_FILTER_TIMER 0x2110129#define HPD_EVENT_MASK 0x211c130#define HPD_EVENT_DET 0x2120131 132/* dpyx framer addr */133#define DP_FRAMER_GLOBAL_CONFIG 0x2200134#define DP_SW_RESET 0x2204135#define DP_FRAMER_TU 0x2208136#define DP_FRAMER_PXL_REPR 0x220c137#define DP_FRAMER_SP 0x2210138#define AUDIO_PACK_CONTROL 0x2214139#define DP_VC_TABLE(x) (0x2218 + ((x) << 2))140#define DP_VB_ID 0x2258141#define DP_MTPH_LVP_CONTROL 0x225c142#define DP_MTPH_SYMBOL_VALUES 0x2260143#define DP_MTPH_ECF_CONTROL 0x2264144#define DP_MTPH_ACT_CONTROL 0x2268145#define DP_MTPH_STATUS 0x226c146#define DP_INTERRUPT_SOURCE 0x2270147#define DP_INTERRUPT_MASK 0x2274148#define DP_FRONT_BACK_PORCH 0x2278149#define DP_BYTE_COUNT 0x227c150 151/* dptx stream addr */152#define MSA_HORIZONTAL_0 0x2280153#define MSA_HORIZONTAL_1 0x2284154#define MSA_VERTICAL_0 0x2288155#define MSA_VERTICAL_1 0x228c156#define MSA_MISC 0x2290157#define STREAM_CONFIG 0x2294158#define AUDIO_PACK_STATUS 0x2298159#define VIF_STATUS 0x229c160#define PCK_STUFF_STATUS_0 0x22a0161#define PCK_STUFF_STATUS_1 0x22a4162#define INFO_PACK_STATUS 0x22a8163#define RATE_GOVERNOR_STATUS 0x22ac164#define DP_HORIZONTAL 0x22b0165#define DP_VERTICAL_0 0x22b4166#define DP_VERTICAL_1 0x22b8167#define DP_BLOCK_SDP 0x22bc168 169/* dptx glbl addr */170#define DPTX_LANE_EN 0x2300171#define DPTX_ENHNCD 0x2304172#define DPTX_INT_MASK 0x2308173#define DPTX_INT_STATUS 0x230c174 175/* dp aux addr */176#define DP_AUX_HOST_CONTROL 0x2800177#define DP_AUX_INTERRUPT_SOURCE 0x2804178#define DP_AUX_INTERRUPT_MASK 0x2808179#define DP_AUX_SWAP_INVERSION_CONTROL 0x280c180#define DP_AUX_SEND_NACK_TRANSACTION 0x2810181#define DP_AUX_CLEAR_RX 0x2814182#define DP_AUX_CLEAR_TX 0x2818183#define DP_AUX_TIMER_STOP 0x281c184#define DP_AUX_TIMER_CLEAR 0x2820185#define DP_AUX_RESET_SW 0x2824186#define DP_AUX_DIVIDE_2M 0x2828187#define DP_AUX_TX_PREACHARGE_LENGTH 0x282c188#define DP_AUX_FREQUENCY_1M_MAX 0x2830189#define DP_AUX_FREQUENCY_1M_MIN 0x2834190#define DP_AUX_RX_PRE_MIN 0x2838191#define DP_AUX_RX_PRE_MAX 0x283c192#define DP_AUX_TIMER_PRESET 0x2840193#define DP_AUX_NACK_FORMAT 0x2844194#define DP_AUX_TX_DATA 0x2848195#define DP_AUX_RX_DATA 0x284c196#define DP_AUX_TX_STATUS 0x2850197#define DP_AUX_RX_STATUS 0x2854198#define DP_AUX_RX_CYCLE_COUNTER 0x2858199#define DP_AUX_MAIN_STATES 0x285c200#define DP_AUX_MAIN_TIMER 0x2860201#define DP_AUX_AFE_OUT 0x2864202 203/* crypto addr */204#define CRYPTO_HDCP_REVISION 0x5800205#define HDCP_CRYPTO_CONFIG 0x5804206#define CRYPTO_INTERRUPT_SOURCE 0x5808207#define CRYPTO_INTERRUPT_MASK 0x580c208#define CRYPTO22_CONFIG 0x5818209#define CRYPTO22_STATUS 0x581c210#define SHA_256_DATA_IN 0x583c211#define SHA_256_DATA_OUT_(x) (0x5850 + ((x) << 2))212#define AES_32_KEY_(x) (0x5870 + ((x) << 2))213#define AES_32_DATA_IN 0x5880214#define AES_32_DATA_OUT_(x) (0x5884 + ((x) << 2))215#define CRYPTO14_CONFIG 0x58a0216#define CRYPTO14_STATUS 0x58a4217#define CRYPTO14_PRNM_OUT 0x58a8218#define CRYPTO14_KM_0 0x58ac219#define CRYPTO14_KM_1 0x58b0220#define CRYPTO14_AN_0 0x58b4221#define CRYPTO14_AN_1 0x58b8222#define CRYPTO14_YOUR_KSV_0 0x58bc223#define CRYPTO14_YOUR_KSV_1 0x58c0224#define CRYPTO14_MI_0 0x58c4225#define CRYPTO14_MI_1 0x58c8226#define CRYPTO14_TI_0 0x58cc227#define CRYPTO14_KI_0 0x58d0228#define CRYPTO14_KI_1 0x58d4229#define CRYPTO14_BLOCKS_NUM 0x58d8230#define CRYPTO14_KEY_MEM_DATA_0 0x58dc231#define CRYPTO14_KEY_MEM_DATA_1 0x58e0232#define CRYPTO14_SHA1_MSG_DATA 0x58e4233#define CRYPTO14_SHA1_V_VALUE_(x) (0x58e8 + ((x) << 2))234#define TRNG_CTRL 0x58fc235#define TRNG_DATA_RDY 0x5900236#define TRNG_DATA 0x5904237 238/* cipher addr */239#define HDCP_REVISION 0x60000240#define INTERRUPT_SOURCE 0x60004241#define INTERRUPT_MASK 0x60008242#define HDCP_CIPHER_CONFIG 0x6000c243#define AES_128_KEY_0 0x60010244#define AES_128_KEY_1 0x60014245#define AES_128_KEY_2 0x60018246#define AES_128_KEY_3 0x6001c247#define AES_128_RANDOM_0 0x60020248#define AES_128_RANDOM_1 0x60024249#define CIPHER14_KM_0 0x60028250#define CIPHER14_KM_1 0x6002c251#define CIPHER14_STATUS 0x60030252#define CIPHER14_RI_PJ_STATUS 0x60034253#define CIPHER_MODE 0x60038254#define CIPHER14_AN_0 0x6003c255#define CIPHER14_AN_1 0x60040256#define CIPHER22_AUTH 0x60044257#define CIPHER14_R0_DP_STATUS 0x60048258#define CIPHER14_BOOTSTRAP 0x6004c259 260#define DPTX_FRMR_DATA_CLK_RSTN_EN BIT(11)261#define DPTX_FRMR_DATA_CLK_EN BIT(10)262#define DPTX_PHY_DATA_RSTN_EN BIT(9)263#define DPTX_PHY_DATA_CLK_EN BIT(8)264#define DPTX_PHY_CHAR_RSTN_EN BIT(7)265#define DPTX_PHY_CHAR_CLK_EN BIT(6)266#define SOURCE_AUX_SYS_CLK_RSTN_EN BIT(5)267#define SOURCE_AUX_SYS_CLK_EN BIT(4)268#define DPTX_SYS_CLK_RSTN_EN BIT(3)269#define DPTX_SYS_CLK_EN BIT(2)270#define CFG_DPTX_VIF_CLK_RSTN_EN BIT(1)271#define CFG_DPTX_VIF_CLK_EN BIT(0)272 273#define SOURCE_PHY_RSTN_EN BIT(1)274#define SOURCE_PHY_CLK_EN BIT(0)275 276#define SOURCE_PKT_SYS_RSTN_EN BIT(3)277#define SOURCE_PKT_SYS_CLK_EN BIT(2)278#define SOURCE_PKT_DATA_RSTN_EN BIT(1)279#define SOURCE_PKT_DATA_CLK_EN BIT(0)280 281#define SPDIF_CDR_CLK_RSTN_EN BIT(5)282#define SPDIF_CDR_CLK_EN BIT(4)283#define SOURCE_AIF_SYS_RSTN_EN BIT(3)284#define SOURCE_AIF_SYS_CLK_EN BIT(2)285#define SOURCE_AIF_CLK_RSTN_EN BIT(1)286#define SOURCE_AIF_CLK_EN BIT(0)287 288#define SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN BIT(3)289#define SOURCE_CIPHER_SYS_CLK_EN BIT(2)290#define SOURCE_CIPHER_CHAR_CLK_RSTN_EN BIT(1)291#define SOURCE_CIPHER_CHAR_CLK_EN BIT(0)292 293#define SOURCE_CRYPTO_SYS_CLK_RSTN_EN BIT(1)294#define SOURCE_CRYPTO_SYS_CLK_EN BIT(0)295 296#define APB_IRAM_PATH BIT(2)297#define APB_DRAM_PATH BIT(1)298#define APB_XT_RESET BIT(0)299 300#define MAILBOX_INT_MASK_BIT BIT(1)301#define PIF_INT_MASK_BIT BIT(0)302#define ALL_INT_MASK 3303 304/* mailbox */305#define MB_OPCODE_ID 0306#define MB_MODULE_ID 1307#define MB_SIZE_MSB_ID 2308#define MB_SIZE_LSB_ID 3309#define MB_DATA_ID 4310 311#define MB_MODULE_ID_DP_TX 0x01312#define MB_MODULE_ID_HDCP_TX 0x07313#define MB_MODULE_ID_HDCP_RX 0x08314#define MB_MODULE_ID_HDCP_GENERAL 0x09315#define MB_MODULE_ID_GENERAL 0x0a316 317/* general opcode */318#define GENERAL_MAIN_CONTROL 0x01319#define GENERAL_TEST_ECHO 0x02320#define GENERAL_BUS_SETTINGS 0x03321#define GENERAL_TEST_ACCESS 0x04322 323#define DPTX_SET_POWER_MNG 0x00324#define DPTX_SET_HOST_CAPABILITIES 0x01325#define DPTX_GET_EDID 0x02326#define DPTX_READ_DPCD 0x03327#define DPTX_WRITE_DPCD 0x04328#define DPTX_ENABLE_EVENT 0x05329#define DPTX_WRITE_REGISTER 0x06330#define DPTX_READ_REGISTER 0x07331#define DPTX_WRITE_FIELD 0x08332#define DPTX_TRAINING_CONTROL 0x09333#define DPTX_READ_EVENT 0x0a334#define DPTX_READ_LINK_STAT 0x0b335#define DPTX_SET_VIDEO 0x0c336#define DPTX_SET_AUDIO 0x0d337#define DPTX_GET_LAST_AUX_STAUS 0x0e338#define DPTX_SET_LINK_BREAK_POINT 0x0f339#define DPTX_FORCE_LANES 0x10340#define DPTX_HPD_STATE 0x11341 342#define FW_STANDBY 0343#define FW_ACTIVE 1344 345#define DPTX_EVENT_ENABLE_HPD BIT(0)346#define DPTX_EVENT_ENABLE_TRAINING BIT(1)347 348#define LINK_TRAINING_NOT_ACTIVE 0349#define LINK_TRAINING_RUN 1350#define LINK_TRAINING_RESTART 2351 352#define CONTROL_VIDEO_IDLE 0353#define CONTROL_VIDEO_VALID 1354 355#define TU_CNT_RST_EN BIT(15)356#define VIF_BYPASS_INTERLACE BIT(13)357#define INTERLACE_FMT_DET BIT(12)358#define INTERLACE_DTCT_WIN 0x20359 360#define DP_FRAMER_SP_INTERLACE_EN BIT(2)361#define DP_FRAMER_SP_HSP BIT(1)362#define DP_FRAMER_SP_VSP BIT(0)363 364/* capability */365#define AUX_HOST_INVERT 3366#define FAST_LT_SUPPORT 1367#define FAST_LT_NOT_SUPPORT 0368#define LANE_MAPPING_NORMAL 0x1b369#define LANE_MAPPING_FLIPPED 0xe4370#define ENHANCED 1371#define SCRAMBLER_EN BIT(4)372 373#define FULL_LT_STARTED BIT(0)374#define FASE_LT_STARTED BIT(1)375#define CLK_RECOVERY_FINISHED BIT(2)376#define EQ_PHASE_FINISHED BIT(3)377#define FASE_LT_START_FINISHED BIT(4)378#define CLK_RECOVERY_FAILED BIT(5)379#define EQ_PHASE_FAILED BIT(6)380#define FASE_LT_FAILED BIT(7)381 382#define DPTX_HPD_EVENT BIT(0)383#define DPTX_TRAINING_EVENT BIT(1)384#define HDCP_TX_STATUS_EVENT BIT(4)385#define HDCP2_TX_IS_KM_STORED_EVENT BIT(5)386#define HDCP2_TX_STORE_KM_EVENT BIT(6)387#define HDCP_TX_IS_RECEIVER_ID_VALID_EVENT BIT(7)388 389#define TU_SIZE 30390#define CDN_DP_MAX_LINK_RATE DP_LINK_BW_5_4391 392/* audio */393#define AUDIO_PACK_EN BIT(8)394#define SAMPLING_FREQ(x) (((x) & 0xf) << 16)395#define ORIGINAL_SAMP_FREQ(x) (((x) & 0xf) << 24)396#define SYNC_WR_TO_CH_ZERO BIT(1)397#define I2S_DEC_START BIT(1)398#define AUDIO_SW_RST BIT(0)399#define SMPL2PKT_EN BIT(1)400#define MAX_NUM_CH(x) (((x) & 0x1f) - 1)401#define NUM_OF_I2S_PORTS(x) ((((x) / 2 - 1) & 0x3) << 5)402#define AUDIO_TYPE_LPCM (2 << 7)403#define CFG_SUB_PCKT_NUM(x) ((((x) - 1) & 0x7) << 11)404#define AUDIO_CH_NUM(x) ((((x) - 1) & 0x1f) << 2)405#define TRANS_SMPL_WIDTH_16 0406#define TRANS_SMPL_WIDTH_24 BIT(11)407#define TRANS_SMPL_WIDTH_32 (2 << 11)408#define I2S_DEC_PORT_EN(x) (((x) & 0xf) << 17)409#define SPDIF_ENABLE BIT(21)410#define SPDIF_AVG_SEL BIT(20)411#define SPDIF_JITTER_BYPASS BIT(19)412#define SPDIF_FIFO_MID_RANGE(x) (((x) & 0xff) << 11)413#define SPDIF_JITTER_THRSH(x) (((x) & 0xff) << 3)414#define SPDIF_JITTER_AVG_WIN(x) ((x) & 0x7)415 416/* Reference cycles when using lane clock as reference */417#define LANE_REF_CYC 0x8000418 419enum voltage_swing_level {420 VOLTAGE_LEVEL_0,421 VOLTAGE_LEVEL_1,422 VOLTAGE_LEVEL_2,423 VOLTAGE_LEVEL_3,424};425 426enum pre_emphasis_level {427 PRE_EMPHASIS_LEVEL_0,428 PRE_EMPHASIS_LEVEL_1,429 PRE_EMPHASIS_LEVEL_2,430 PRE_EMPHASIS_LEVEL_3,431};432 433enum pattern_set {434 PTS1 = BIT(0),435 PTS2 = BIT(1),436 PTS3 = BIT(2),437 PTS4 = BIT(3),438 DP_NONE = BIT(4)439};440 441enum vic_color_depth {442 BCS_6 = 0x1,443 BCS_8 = 0x2,444 BCS_10 = 0x4,445 BCS_12 = 0x8,446 BCS_16 = 0x10,447};448 449enum vic_bt_type {450 BT_601 = 0x0,451 BT_709 = 0x1,452};453 454void cdn_dp_clock_reset(struct cdn_dp_device *dp);455 456void cdn_dp_set_fw_clk(struct cdn_dp_device *dp, unsigned long clk);457int cdn_dp_load_firmware(struct cdn_dp_device *dp, const u32 *i_mem,458 u32 i_size, const u32 *d_mem, u32 d_size);459int cdn_dp_set_firmware_active(struct cdn_dp_device *dp, bool enable);460int cdn_dp_set_host_cap(struct cdn_dp_device *dp, u8 lanes, bool flip);461int cdn_dp_event_config(struct cdn_dp_device *dp);462u32 cdn_dp_get_event(struct cdn_dp_device *dp);463int cdn_dp_get_hpd_status(struct cdn_dp_device *dp);464int cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr, u8 value);465int cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr, u8 *data, u16 len);466int cdn_dp_get_edid_block(void *dp, u8 *edid,467 unsigned int block, size_t length);468int cdn_dp_train_link(struct cdn_dp_device *dp);469int cdn_dp_set_video_status(struct cdn_dp_device *dp, int active);470int cdn_dp_config_video(struct cdn_dp_device *dp);471int cdn_dp_audio_stop(struct cdn_dp_device *dp, struct audio_info *audio);472int cdn_dp_audio_mute(struct cdn_dp_device *dp, bool enable);473int cdn_dp_audio_config(struct cdn_dp_device *dp, struct audio_info *audio);474#endif /* _CDN_DP_REG_H */475