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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd4 * Author:Mark Yao <mark.yao@rock-chips.com>5 */6 7#ifndef _ROCKCHIP_DRM_VOP_H8#define _ROCKCHIP_DRM_VOP_H9 10/*11 * major: IP major version, used for IP structure12 * minor: big feature change under same structure13 */14#define VOP_VERSION(major, minor) ((major) << 8 | (minor))15#define VOP_MAJOR(version) ((version) >> 8)16#define VOP_MINOR(version) ((version) & 0xff)17 18#define NUM_YUV2YUV_COEFFICIENTS 1219 20/* AFBC supports a number of configurable modes. Relevant to us is block size21 * (16x16 or 32x8), storage modifiers (SPARSE, SPLIT), and the YUV-like22 * colourspace transform (YTR). 16x16 SPARSE mode is always used. SPLIT mode23 * could be enabled via the hreg_block_split register, but is not currently24 * handled. The colourspace transform is implicitly always assumed by the25 * decoder, so consumers must use this transform as well.26 *27 * Failure to match modifiers will cause errors displaying AFBC buffers28 * produced by conformant AFBC producers, including Mesa.29 */30#define ROCKCHIP_AFBC_MOD \31 DRM_FORMAT_MOD_ARM_AFBC( \32 AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | AFBC_FORMAT_MOD_SPARSE \33 | AFBC_FORMAT_MOD_YTR \34 )35 36enum vop_data_format {37 VOP_FMT_ARGB8888 = 0,38 VOP_FMT_RGB888,39 VOP_FMT_RGB565,40 VOP_FMT_YUV420SP = 4,41 VOP_FMT_YUV422SP,42 VOP_FMT_YUV444SP,43};44 45struct vop_rect {46 int width;47 int height;48};49 50struct vop_reg {51 uint32_t mask;52 uint16_t offset;53 uint8_t shift;54 bool write_mask;55 bool relaxed;56};57 58struct vop_afbc {59 struct vop_reg enable;60 struct vop_reg win_sel;61 struct vop_reg format;62 struct vop_reg rb_swap;63 struct vop_reg uv_swap;64 struct vop_reg auto_gating_en;65 struct vop_reg block_split_en;66 struct vop_reg pic_vir_width;67 struct vop_reg tile_num;68 struct vop_reg hreg_block_split;69 struct vop_reg pic_offset;70 struct vop_reg pic_size;71 struct vop_reg dsp_offset;72 struct vop_reg transform_offset;73 struct vop_reg hdr_ptr;74 struct vop_reg half_block_en;75 struct vop_reg xmirror;76 struct vop_reg ymirror;77 struct vop_reg rotate_270;78 struct vop_reg rotate_90;79 struct vop_reg rstn;80};81 82struct vop_modeset {83 struct vop_reg htotal_pw;84 struct vop_reg hact_st_end;85 struct vop_reg hpost_st_end;86 struct vop_reg vtotal_pw;87 struct vop_reg vact_st_end;88 struct vop_reg vpost_st_end;89};90 91struct vop_output {92 struct vop_reg pin_pol;93 struct vop_reg dp_pin_pol;94 struct vop_reg dp_dclk_pol;95 struct vop_reg edp_pin_pol;96 struct vop_reg edp_dclk_pol;97 struct vop_reg hdmi_pin_pol;98 struct vop_reg hdmi_dclk_pol;99 struct vop_reg mipi_pin_pol;100 struct vop_reg mipi_dclk_pol;101 struct vop_reg rgb_pin_pol;102 struct vop_reg rgb_dclk_pol;103 struct vop_reg dp_en;104 struct vop_reg edp_en;105 struct vop_reg hdmi_en;106 struct vop_reg mipi_en;107 struct vop_reg mipi_dual_channel_en;108 struct vop_reg rgb_en;109};110 111struct vop_common {112 struct vop_reg cfg_done;113 struct vop_reg dsp_blank;114 struct vop_reg data_blank;115 struct vop_reg pre_dither_down;116 struct vop_reg dither_down_sel;117 struct vop_reg dither_down_mode;118 struct vop_reg dither_down_en;119 struct vop_reg dither_up;120 struct vop_reg dsp_lut_en;121 struct vop_reg update_gamma_lut;122 struct vop_reg lut_buffer_index;123 struct vop_reg gate_en;124 struct vop_reg mmu_en;125 struct vop_reg dma_stop;126 struct vop_reg out_mode;127 struct vop_reg standby;128};129 130struct vop_misc {131 struct vop_reg global_regdone_en;132};133 134struct vop_intr {135 const int *intrs;136 uint32_t nintrs;137 138 struct vop_reg line_flag_num[2];139 struct vop_reg enable;140 struct vop_reg clear;141 struct vop_reg status;142};143 144struct vop_scl_extension {145 struct vop_reg cbcr_vsd_mode;146 struct vop_reg cbcr_vsu_mode;147 struct vop_reg cbcr_hsd_mode;148 struct vop_reg cbcr_ver_scl_mode;149 struct vop_reg cbcr_hor_scl_mode;150 struct vop_reg yrgb_vsd_mode;151 struct vop_reg yrgb_vsu_mode;152 struct vop_reg yrgb_hsd_mode;153 struct vop_reg yrgb_ver_scl_mode;154 struct vop_reg yrgb_hor_scl_mode;155 struct vop_reg line_load_mode;156 struct vop_reg cbcr_axi_gather_num;157 struct vop_reg yrgb_axi_gather_num;158 struct vop_reg vsd_cbcr_gt2;159 struct vop_reg vsd_cbcr_gt4;160 struct vop_reg vsd_yrgb_gt2;161 struct vop_reg vsd_yrgb_gt4;162 struct vop_reg bic_coe_sel;163 struct vop_reg cbcr_axi_gather_en;164 struct vop_reg yrgb_axi_gather_en;165 struct vop_reg lb_mode;166};167 168struct vop_scl_regs {169 const struct vop_scl_extension *ext;170 171 struct vop_reg scale_yrgb_x;172 struct vop_reg scale_yrgb_y;173 struct vop_reg scale_cbcr_x;174 struct vop_reg scale_cbcr_y;175};176 177struct vop_yuv2yuv_phy {178 struct vop_reg y2r_coefficients[NUM_YUV2YUV_COEFFICIENTS];179};180 181struct vop_win_phy {182 const struct vop_scl_regs *scl;183 const uint32_t *data_formats;184 uint32_t nformats;185 const uint64_t *format_modifiers;186 187 struct vop_reg enable;188 struct vop_reg gate;189 struct vop_reg format;190 struct vop_reg fmt_10;191 struct vop_reg rb_swap;192 struct vop_reg uv_swap;193 struct vop_reg act_info;194 struct vop_reg dsp_info;195 struct vop_reg dsp_st;196 struct vop_reg yrgb_mst;197 struct vop_reg uv_mst;198 struct vop_reg yrgb_vir;199 struct vop_reg uv_vir;200 struct vop_reg y_mir_en;201 struct vop_reg x_mir_en;202 203 struct vop_reg dst_alpha_ctl;204 struct vop_reg src_alpha_ctl;205 struct vop_reg alpha_pre_mul;206 struct vop_reg alpha_mode;207 struct vop_reg alpha_en;208 struct vop_reg channel;209};210 211struct vop_win_yuv2yuv_data {212 uint32_t base;213 const struct vop_yuv2yuv_phy *phy;214 struct vop_reg y2r_en;215};216 217struct vop_win_data {218 uint32_t base;219 const struct vop_win_phy *phy;220 enum drm_plane_type type;221};222 223struct vop_data {224 uint32_t version;225 const struct vop_intr *intr;226 const struct vop_common *common;227 const struct vop_misc *misc;228 const struct vop_modeset *modeset;229 const struct vop_output *output;230 const struct vop_afbc *afbc;231 const struct vop_win_yuv2yuv_data *win_yuv2yuv;232 const struct vop_win_data *win;233 unsigned int win_size;234 unsigned int lut_size;235 struct vop_rect max_output;236 237#define VOP_FEATURE_OUTPUT_RGB10 BIT(0)238#define VOP_FEATURE_INTERNAL_RGB BIT(1)239 u64 feature;240};241 242/* interrupt define */243#define DSP_HOLD_VALID_INTR (1 << 0)244#define FS_INTR (1 << 1)245#define LINE_FLAG_INTR (1 << 2)246#define BUS_ERROR_INTR (1 << 3)247 248#define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \249 LINE_FLAG_INTR | BUS_ERROR_INTR)250 251#define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4)252#define FS_INTR_EN(x) ((x) << 5)253#define LINE_FLAG_INTR_EN(x) ((x) << 6)254#define BUS_ERROR_INTR_EN(x) ((x) << 7)255#define DSP_HOLD_VALID_INTR_MASK (1 << 4)256#define FS_INTR_MASK (1 << 5)257#define LINE_FLAG_INTR_MASK (1 << 6)258#define BUS_ERROR_INTR_MASK (1 << 7)259 260#define INTR_CLR_SHIFT 8261#define DSP_HOLD_VALID_INTR_CLR (1 << (INTR_CLR_SHIFT + 0))262#define FS_INTR_CLR (1 << (INTR_CLR_SHIFT + 1))263#define LINE_FLAG_INTR_CLR (1 << (INTR_CLR_SHIFT + 2))264#define BUS_ERROR_INTR_CLR (1 << (INTR_CLR_SHIFT + 3))265 266#define DSP_LINE_NUM(x) (((x) & 0x1fff) << 12)267#define DSP_LINE_NUM_MASK (0x1fff << 12)268 269/* src alpha ctrl define */270#define SRC_FADING_VALUE(x) (((x) & 0xff) << 24)271#define SRC_GLOBAL_ALPHA(x) (((x) & 0xff) << 16)272#define SRC_FACTOR_M0(x) (((x) & 0x7) << 6)273#define SRC_ALPHA_CAL_M0(x) (((x) & 0x1) << 5)274#define SRC_BLEND_M0(x) (((x) & 0x3) << 3)275#define SRC_ALPHA_M0(x) (((x) & 0x1) << 2)276#define SRC_COLOR_M0(x) (((x) & 0x1) << 1)277#define SRC_ALPHA_EN(x) (((x) & 0x1) << 0)278/* dst alpha ctrl define */279#define DST_FACTOR_M0(x) (((x) & 0x7) << 6)280 281enum alpha_mode {282 ALPHA_STRAIGHT,283 ALPHA_INVERSE,284};285 286enum global_blend_mode {287 ALPHA_GLOBAL,288 ALPHA_PER_PIX,289 ALPHA_PER_PIX_GLOBAL,290};291 292enum alpha_cal_mode {293 ALPHA_SATURATION,294 ALPHA_NO_SATURATION,295};296 297enum color_mode {298 ALPHA_SRC_PRE_MUL,299 ALPHA_SRC_NO_PRE_MUL,300};301 302enum factor_mode {303 ALPHA_ZERO,304 ALPHA_ONE,305 ALPHA_SRC,306 ALPHA_SRC_INVERSE,307 ALPHA_SRC_GLOBAL,308};309 310enum scale_mode {311 SCALE_NONE = 0x0,312 SCALE_UP = 0x1,313 SCALE_DOWN = 0x2314};315 316enum lb_mode {317 LB_YUV_3840X5 = 0x0,318 LB_YUV_2560X8 = 0x1,319 LB_RGB_3840X2 = 0x2,320 LB_RGB_2560X4 = 0x3,321 LB_RGB_1920X5 = 0x4,322 LB_RGB_1280X8 = 0x5323};324 325enum sacle_up_mode {326 SCALE_UP_BIL = 0x0,327 SCALE_UP_BIC = 0x1328};329 330enum scale_down_mode {331 SCALE_DOWN_BIL = 0x0,332 SCALE_DOWN_AVG = 0x1333};334 335enum dither_down_mode {336 RGB888_TO_RGB565 = 0x0,337 RGB888_TO_RGB666 = 0x1338};339 340enum dither_down_mode_sel {341 DITHER_DOWN_ALLEGRO = 0x0,342 DITHER_DOWN_FRC = 0x1343};344 345enum vop_pol {346 HSYNC_POSITIVE = 0,347 VSYNC_POSITIVE = 1,348 DEN_NEGATIVE = 2349};350 351#define FRAC_16_16(mult, div) (((mult) << 16) / (div))352#define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12353#define SCL_MAX_VSKIPLINES 4354#define MIN_SCL_FT_AFTER_VSKIP 1355 356static inline uint16_t scl_cal_scale(int src, int dst, int shift)357{358 return ((src * 2 - 3) << (shift - 1)) / (dst - 1);359}360 361static inline uint16_t scl_cal_scale2(int src, int dst)362{363 return ((src - 1) << 12) / (dst - 1);364}365 366#define GET_SCL_FT_BILI_DN(src, dst) scl_cal_scale(src, dst, 12)367#define GET_SCL_FT_BILI_UP(src, dst) scl_cal_scale(src, dst, 16)368#define GET_SCL_FT_BIC(src, dst) scl_cal_scale(src, dst, 16)369 370static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,371 int vskiplines)372{373 int act_height;374 375 act_height = DIV_ROUND_UP(src_h, vskiplines);376 377 if (act_height == dst_h)378 return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines;379 380 return GET_SCL_FT_BILI_DN(act_height, dst_h);381}382 383static inline enum scale_mode scl_get_scl_mode(int src, int dst)384{385 if (src < dst)386 return SCALE_UP;387 else if (src > dst)388 return SCALE_DOWN;389 390 return SCALE_NONE;391}392 393static inline int scl_get_vskiplines(uint32_t srch, uint32_t dsth)394{395 uint32_t vskiplines;396 397 for (vskiplines = SCL_MAX_VSKIPLINES; vskiplines > 1; vskiplines /= 2)398 if (srch >= vskiplines * dsth * MIN_SCL_FT_AFTER_VSKIP)399 break;400 401 return vskiplines;402}403 404static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)405{406 int lb_mode;407 408 if (is_yuv) {409 if (width > 1280)410 lb_mode = LB_YUV_3840X5;411 else412 lb_mode = LB_YUV_2560X8;413 } else {414 if (width > 2560)415 lb_mode = LB_RGB_3840X2;416 else if (width > 1920)417 lb_mode = LB_RGB_2560X4;418 else419 lb_mode = LB_RGB_1920X5;420 }421 422 return lb_mode;423}424 425extern const struct component_ops vop_component_ops;426#endif /* _ROCKCHIP_DRM_VOP_H */427