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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd4 * Author:5 * Sandy Huang <hjc@rock-chips.com>6 * Mark Yao <mark.yao@rock-chips.com>7 */8 9#ifndef _ROCKCHIP_LVDS_10#define _ROCKCHIP_LVDS_11 12#define RK3288_LVDS_CH0_REG0 0x0013#define RK3288_LVDS_CH0_REG0_LVDS_EN BIT(7)14#define RK3288_LVDS_CH0_REG0_TTL_EN BIT(6)15#define RK3288_LVDS_CH0_REG0_LANECK_EN BIT(5)16#define RK3288_LVDS_CH0_REG0_LANE4_EN BIT(4)17#define RK3288_LVDS_CH0_REG0_LANE3_EN BIT(3)18#define RK3288_LVDS_CH0_REG0_LANE2_EN BIT(2)19#define RK3288_LVDS_CH0_REG0_LANE1_EN BIT(1)20#define RK3288_LVDS_CH0_REG0_LANE0_EN BIT(0)21 22#define RK3288_LVDS_CH0_REG1 0x0423#define RK3288_LVDS_CH0_REG1_LANECK_BIAS BIT(5)24#define RK3288_LVDS_CH0_REG1_LANE4_BIAS BIT(4)25#define RK3288_LVDS_CH0_REG1_LANE3_BIAS BIT(3)26#define RK3288_LVDS_CH0_REG1_LANE2_BIAS BIT(2)27#define RK3288_LVDS_CH0_REG1_LANE1_BIAS BIT(1)28#define RK3288_LVDS_CH0_REG1_LANE0_BIAS BIT(0)29 30#define RK3288_LVDS_CH0_REG2 0x0831#define RK3288_LVDS_CH0_REG2_RESERVE_ON BIT(7)32#define RK3288_LVDS_CH0_REG2_LANECK_LVDS_MODE BIT(6)33#define RK3288_LVDS_CH0_REG2_LANE4_LVDS_MODE BIT(5)34#define RK3288_LVDS_CH0_REG2_LANE3_LVDS_MODE BIT(4)35#define RK3288_LVDS_CH0_REG2_LANE2_LVDS_MODE BIT(3)36#define RK3288_LVDS_CH0_REG2_LANE1_LVDS_MODE BIT(2)37#define RK3288_LVDS_CH0_REG2_LANE0_LVDS_MODE BIT(1)38#define RK3288_LVDS_CH0_REG2_PLL_FBDIV8 BIT(0)39 40#define RK3288_LVDS_CH0_REG3 0x0c41#define RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK 0xff42 43#define RK3288_LVDS_CH0_REG4 0x1044#define RK3288_LVDS_CH0_REG4_LANECK_TTL_MODE BIT(5)45#define RK3288_LVDS_CH0_REG4_LANE4_TTL_MODE BIT(4)46#define RK3288_LVDS_CH0_REG4_LANE3_TTL_MODE BIT(3)47#define RK3288_LVDS_CH0_REG4_LANE2_TTL_MODE BIT(2)48#define RK3288_LVDS_CH0_REG4_LANE1_TTL_MODE BIT(1)49#define RK3288_LVDS_CH0_REG4_LANE0_TTL_MODE BIT(0)50 51#define RK3288_LVDS_CH0_REG5 0x1452#define RK3288_LVDS_CH0_REG5_LANECK_TTL_DATA BIT(5)53#define RK3288_LVDS_CH0_REG5_LANE4_TTL_DATA BIT(4)54#define RK3288_LVDS_CH0_REG5_LANE3_TTL_DATA BIT(3)55#define RK3288_LVDS_CH0_REG5_LANE2_TTL_DATA BIT(2)56#define RK3288_LVDS_CH0_REG5_LANE1_TTL_DATA BIT(1)57#define RK3288_LVDS_CH0_REG5_LANE0_TTL_DATA BIT(0)58 59#define RK3288_LVDS_CFG_REGC 0x3060#define RK3288_LVDS_CFG_REGC_PLL_ENABLE 0x0061#define RK3288_LVDS_CFG_REGC_PLL_DISABLE 0xff62 63#define RK3288_LVDS_CH0_REGD 0x3464#define RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK 0x1f65 66#define RK3288_LVDS_CH0_REG20 0x8067#define RK3288_LVDS_CH0_REG20_MSB 0x4568#define RK3288_LVDS_CH0_REG20_LSB 0x4469 70#define RK3288_LVDS_CFG_REG21 0x8471#define RK3288_LVDS_CFG_REG21_TX_ENABLE 0x9272#define RK3288_LVDS_CFG_REG21_TX_DISABLE 0x0073#define RK3288_LVDS_CH1_OFFSET 0x10074 75#define RK3288_LVDS_GRF_SOC_CON6 0x025C76#define RK3288_LVDS_GRF_SOC_CON7 0x026077 78/* fbdiv value is split over 2 registers, with bit8 in reg2 */79#define RK3288_LVDS_PLL_FBDIV_REG2(_fbd) \80 (_fbd & BIT(8) ? RK3288_LVDS_CH0_REG2_PLL_FBDIV8 : 0)81#define RK3288_LVDS_PLL_FBDIV_REG3(_fbd) \82 (_fbd & RK3288_LVDS_CH0_REG3_PLL_FBDIV_MASK)83#define RK3288_LVDS_PLL_PREDIV_REGD(_pd) \84 (_pd & RK3288_LVDS_CH0_REGD_PLL_PREDIV_MASK)85 86#define RK3288_LVDS_SOC_CON6_SEL_VOP_LIT BIT(3)87 88#define LVDS_FMT_MASK (0x07 << 16)89#define LVDS_MSB BIT(3)90#define LVDS_DUAL BIT(4)91#define LVDS_FMT_1 BIT(5)92#define LVDS_TTL_EN BIT(6)93#define LVDS_START_PHASE_RST_1 BIT(7)94#define LVDS_DCLK_INV BIT(8)95#define LVDS_CH0_EN BIT(11)96#define LVDS_CH1_EN BIT(12)97#define LVDS_PWRDN BIT(15)98 99#define LVDS_24BIT (0 << 1)100#define LVDS_18BIT (1 << 1)101#define LVDS_FORMAT_VESA (0 << 0)102#define LVDS_FORMAT_JEIDA (1 << 0)103 104#define LVDS_VESA_24 0105#define LVDS_JEIDA_24 1106#define LVDS_VESA_18 2107#define LVDS_JEIDA_18 3108 109#define HIWORD_UPDATE(v, h, l) ((GENMASK(h, l) << 16) | ((v) << (l)))110 111#define PX30_LVDS_GRF_PD_VO_CON0 0x434112#define PX30_LVDS_TIE_CLKS(val) HIWORD_UPDATE(val, 8, 8)113#define PX30_LVDS_INVERT_CLKS(val) HIWORD_UPDATE(val, 9, 9)114#define PX30_LVDS_INVERT_DCLK(val) HIWORD_UPDATE(val, 5, 5)115 116#define PX30_LVDS_GRF_PD_VO_CON1 0x438117#define PX30_LVDS_FORMAT(val) HIWORD_UPDATE(val, 14, 13)118#define PX30_LVDS_MODE_EN(val) HIWORD_UPDATE(val, 12, 12)119#define PX30_LVDS_MSBSEL(val) HIWORD_UPDATE(val, 11, 11)120#define PX30_LVDS_P2S_EN(val) HIWORD_UPDATE(val, 6, 6)121#define PX30_LVDS_VOP_SEL(val) HIWORD_UPDATE(val, 1, 1)122 123#endif /* _ROCKCHIP_LVDS_ */124