1037 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd4 * Author:Mark Yao <mark.yao@rock-chips.com>5 */6 7#ifndef _ROCKCHIP_VOP_REG_H8#define _ROCKCHIP_VOP_REG_H9 10/* rk3288 register definition */11#define RK3288_REG_CFG_DONE 0x000012#define RK3288_VERSION_INFO 0x000413#define RK3288_SYS_CTRL 0x000814#define RK3288_SYS_CTRL1 0x000c15#define RK3288_DSP_CTRL0 0x001016#define RK3288_DSP_CTRL1 0x001417#define RK3288_DSP_BG 0x001818#define RK3288_MCU_CTRL 0x001c19#define RK3288_INTR_CTRL0 0x002020#define RK3288_INTR_CTRL1 0x002421#define RK3288_WIN0_CTRL0 0x003022#define RK3288_WIN0_CTRL1 0x003423#define RK3288_WIN0_COLOR_KEY 0x003824#define RK3288_WIN0_VIR 0x003c25#define RK3288_WIN0_YRGB_MST 0x004026#define RK3288_WIN0_CBR_MST 0x004427#define RK3288_WIN0_ACT_INFO 0x004828#define RK3288_WIN0_DSP_INFO 0x004c29#define RK3288_WIN0_DSP_ST 0x005030#define RK3288_WIN0_SCL_FACTOR_YRGB 0x005431#define RK3288_WIN0_SCL_FACTOR_CBR 0x005832#define RK3288_WIN0_SCL_OFFSET 0x005c33#define RK3288_WIN0_SRC_ALPHA_CTRL 0x006034#define RK3288_WIN0_DST_ALPHA_CTRL 0x006435#define RK3288_WIN0_FADING_CTRL 0x006836#define RK3288_WIN0_CTRL2 0x006c37 38/* win1 register */39#define RK3288_WIN1_CTRL0 0x007040#define RK3288_WIN1_CTRL1 0x007441#define RK3288_WIN1_COLOR_KEY 0x007842#define RK3288_WIN1_VIR 0x007c43#define RK3288_WIN1_YRGB_MST 0x008044#define RK3288_WIN1_CBR_MST 0x008445#define RK3288_WIN1_ACT_INFO 0x008846#define RK3288_WIN1_DSP_INFO 0x008c47#define RK3288_WIN1_DSP_ST 0x009048#define RK3288_WIN1_SCL_FACTOR_YRGB 0x009449#define RK3288_WIN1_SCL_FACTOR_CBR 0x009850#define RK3288_WIN1_SCL_OFFSET 0x009c51#define RK3288_WIN1_SRC_ALPHA_CTRL 0x00a052#define RK3288_WIN1_DST_ALPHA_CTRL 0x00a453#define RK3288_WIN1_FADING_CTRL 0x00a854/* win2 register */55#define RK3288_WIN2_CTRL0 0x00b056#define RK3288_WIN2_CTRL1 0x00b457#define RK3288_WIN2_VIR0_1 0x00b858#define RK3288_WIN2_VIR2_3 0x00bc59#define RK3288_WIN2_MST0 0x00c060#define RK3288_WIN2_DSP_INFO0 0x00c461#define RK3288_WIN2_DSP_ST0 0x00c862#define RK3288_WIN2_COLOR_KEY 0x00cc63#define RK3288_WIN2_MST1 0x00d064#define RK3288_WIN2_DSP_INFO1 0x00d465#define RK3288_WIN2_DSP_ST1 0x00d866#define RK3288_WIN2_SRC_ALPHA_CTRL 0x00dc67#define RK3288_WIN2_MST2 0x00e068#define RK3288_WIN2_DSP_INFO2 0x00e469#define RK3288_WIN2_DSP_ST2 0x00e870#define RK3288_WIN2_DST_ALPHA_CTRL 0x00ec71#define RK3288_WIN2_MST3 0x00f072#define RK3288_WIN2_DSP_INFO3 0x00f473#define RK3288_WIN2_DSP_ST3 0x00f874#define RK3288_WIN2_FADING_CTRL 0x00fc75/* win3 register */76#define RK3288_WIN3_CTRL0 0x010077#define RK3288_WIN3_CTRL1 0x010478#define RK3288_WIN3_VIR0_1 0x010879#define RK3288_WIN3_VIR2_3 0x010c80#define RK3288_WIN3_MST0 0x011081#define RK3288_WIN3_DSP_INFO0 0x011482#define RK3288_WIN3_DSP_ST0 0x011883#define RK3288_WIN3_COLOR_KEY 0x011c84#define RK3288_WIN3_MST1 0x012085#define RK3288_WIN3_DSP_INFO1 0x012486#define RK3288_WIN3_DSP_ST1 0x012887#define RK3288_WIN3_SRC_ALPHA_CTRL 0x012c88#define RK3288_WIN3_MST2 0x013089#define RK3288_WIN3_DSP_INFO2 0x013490#define RK3288_WIN3_DSP_ST2 0x013891#define RK3288_WIN3_DST_ALPHA_CTRL 0x013c92#define RK3288_WIN3_MST3 0x014093#define RK3288_WIN3_DSP_INFO3 0x014494#define RK3288_WIN3_DSP_ST3 0x014895#define RK3288_WIN3_FADING_CTRL 0x014c96/* hwc register */97#define RK3288_HWC_CTRL0 0x015098#define RK3288_HWC_CTRL1 0x015499#define RK3288_HWC_MST 0x0158100#define RK3288_HWC_DSP_ST 0x015c101#define RK3288_HWC_SRC_ALPHA_CTRL 0x0160102#define RK3288_HWC_DST_ALPHA_CTRL 0x0164103#define RK3288_HWC_FADING_CTRL 0x0168104/* post process register */105#define RK3288_POST_DSP_HACT_INFO 0x0170106#define RK3288_POST_DSP_VACT_INFO 0x0174107#define RK3288_POST_SCL_FACTOR_YRGB 0x0178108#define RK3288_POST_SCL_CTRL 0x0180109#define RK3288_POST_DSP_VACT_INFO_F1 0x0184110#define RK3288_DSP_HTOTAL_HS_END 0x0188111#define RK3288_DSP_HACT_ST_END 0x018c112#define RK3288_DSP_VTOTAL_VS_END 0x0190113#define RK3288_DSP_VACT_ST_END 0x0194114#define RK3288_DSP_VS_ST_END_F1 0x0198115#define RK3288_DSP_VACT_ST_END_F1 0x019c116/* register definition end */117 118/* rk3368 register definition */119#define RK3368_REG_CFG_DONE 0x0000120#define RK3368_VERSION_INFO 0x0004121#define RK3368_SYS_CTRL 0x0008122#define RK3368_SYS_CTRL1 0x000c123#define RK3368_DSP_CTRL0 0x0010124#define RK3368_DSP_CTRL1 0x0014125#define RK3368_DSP_BG 0x0018126#define RK3368_MCU_CTRL 0x001c127#define RK3368_LINE_FLAG 0x0020128#define RK3368_INTR_EN 0x0024129#define RK3368_INTR_CLEAR 0x0028130#define RK3368_INTR_STATUS 0x002c131#define RK3368_WIN0_CTRL0 0x0030132#define RK3368_WIN0_CTRL1 0x0034133#define RK3368_WIN0_COLOR_KEY 0x0038134#define RK3368_WIN0_VIR 0x003c135#define RK3368_WIN0_YRGB_MST 0x0040136#define RK3368_WIN0_CBR_MST 0x0044137#define RK3368_WIN0_ACT_INFO 0x0048138#define RK3368_WIN0_DSP_INFO 0x004c139#define RK3368_WIN0_DSP_ST 0x0050140#define RK3368_WIN0_SCL_FACTOR_YRGB 0x0054141#define RK3368_WIN0_SCL_FACTOR_CBR 0x0058142#define RK3368_WIN0_SCL_OFFSET 0x005c143#define RK3368_WIN0_SRC_ALPHA_CTRL 0x0060144#define RK3368_WIN0_DST_ALPHA_CTRL 0x0064145#define RK3368_WIN0_FADING_CTRL 0x0068146#define RK3368_WIN0_CTRL2 0x006c147#define RK3368_WIN1_CTRL0 0x0070148#define RK3368_WIN1_CTRL1 0x0074149#define RK3368_WIN1_COLOR_KEY 0x0078150#define RK3368_WIN1_VIR 0x007c151#define RK3368_WIN1_YRGB_MST 0x0080152#define RK3368_WIN1_CBR_MST 0x0084153#define RK3368_WIN1_ACT_INFO 0x0088154#define RK3368_WIN1_DSP_INFO 0x008c155#define RK3368_WIN1_DSP_ST 0x0090156#define RK3368_WIN1_SCL_FACTOR_YRGB 0x0094157#define RK3368_WIN1_SCL_FACTOR_CBR 0x0098158#define RK3368_WIN1_SCL_OFFSET 0x009c159#define RK3368_WIN1_SRC_ALPHA_CTRL 0x00a0160#define RK3368_WIN1_DST_ALPHA_CTRL 0x00a4161#define RK3368_WIN1_FADING_CTRL 0x00a8162#define RK3368_WIN1_CTRL2 0x00ac163#define RK3368_WIN2_CTRL0 0x00b0164#define RK3368_WIN2_CTRL1 0x00b4165#define RK3368_WIN2_VIR0_1 0x00b8166#define RK3368_WIN2_VIR2_3 0x00bc167#define RK3368_WIN2_MST0 0x00c0168#define RK3368_WIN2_DSP_INFO0 0x00c4169#define RK3368_WIN2_DSP_ST0 0x00c8170#define RK3368_WIN2_COLOR_KEY 0x00cc171#define RK3368_WIN2_MST1 0x00d0172#define RK3368_WIN2_DSP_INFO1 0x00d4173#define RK3368_WIN2_DSP_ST1 0x00d8174#define RK3368_WIN2_SRC_ALPHA_CTRL 0x00dc175#define RK3368_WIN2_MST2 0x00e0176#define RK3368_WIN2_DSP_INFO2 0x00e4177#define RK3368_WIN2_DSP_ST2 0x00e8178#define RK3368_WIN2_DST_ALPHA_CTRL 0x00ec179#define RK3368_WIN2_MST3 0x00f0180#define RK3368_WIN2_DSP_INFO3 0x00f4181#define RK3368_WIN2_DSP_ST3 0x00f8182#define RK3368_WIN2_FADING_CTRL 0x00fc183#define RK3368_WIN3_CTRL0 0x0100184#define RK3368_WIN3_CTRL1 0x0104185#define RK3368_WIN3_VIR0_1 0x0108186#define RK3368_WIN3_VIR2_3 0x010c187#define RK3368_WIN3_MST0 0x0110188#define RK3368_WIN3_DSP_INFO0 0x0114189#define RK3368_WIN3_DSP_ST0 0x0118190#define RK3368_WIN3_COLOR_KEY 0x011c191#define RK3368_WIN3_MST1 0x0120192#define RK3368_WIN3_DSP_INFO1 0x0124193#define RK3368_WIN3_DSP_ST1 0x0128194#define RK3368_WIN3_SRC_ALPHA_CTRL 0x012c195#define RK3368_WIN3_MST2 0x0130196#define RK3368_WIN3_DSP_INFO2 0x0134197#define RK3368_WIN3_DSP_ST2 0x0138198#define RK3368_WIN3_DST_ALPHA_CTRL 0x013c199#define RK3368_WIN3_MST3 0x0140200#define RK3368_WIN3_DSP_INFO3 0x0144201#define RK3368_WIN3_DSP_ST3 0x0148202#define RK3368_WIN3_FADING_CTRL 0x014c203#define RK3368_HWC_CTRL0 0x0150204#define RK3368_HWC_CTRL1 0x0154205#define RK3368_HWC_MST 0x0158206#define RK3368_HWC_DSP_ST 0x015c207#define RK3368_HWC_SRC_ALPHA_CTRL 0x0160208#define RK3368_HWC_DST_ALPHA_CTRL 0x0164209#define RK3368_HWC_FADING_CTRL 0x0168210#define RK3368_HWC_RESERVED1 0x016c211#define RK3368_POST_DSP_HACT_INFO 0x0170212#define RK3368_POST_DSP_VACT_INFO 0x0174213#define RK3368_POST_SCL_FACTOR_YRGB 0x0178214#define RK3368_POST_RESERVED 0x017c215#define RK3368_POST_SCL_CTRL 0x0180216#define RK3368_POST_DSP_VACT_INFO_F1 0x0184217#define RK3368_DSP_HTOTAL_HS_END 0x0188218#define RK3368_DSP_HACT_ST_END 0x018c219#define RK3368_DSP_VTOTAL_VS_END 0x0190220#define RK3368_DSP_VACT_ST_END 0x0194221#define RK3368_DSP_VS_ST_END_F1 0x0198222#define RK3368_DSP_VACT_ST_END_F1 0x019c223#define RK3368_PWM_CTRL 0x01a0224#define RK3368_PWM_PERIOD_HPR 0x01a4225#define RK3368_PWM_DUTY_LPR 0x01a8226#define RK3368_PWM_CNT 0x01ac227#define RK3368_BCSH_COLOR_BAR 0x01b0228#define RK3368_BCSH_BCS 0x01b4229#define RK3368_BCSH_H 0x01b8230#define RK3368_BCSH_CTRL 0x01bc231#define RK3368_CABC_CTRL0 0x01c0232#define RK3368_CABC_CTRL1 0x01c4233#define RK3368_CABC_CTRL2 0x01c8234#define RK3368_CABC_CTRL3 0x01cc235#define RK3368_CABC_GAUSS_LINE0_0 0x01d0236#define RK3368_CABC_GAUSS_LINE0_1 0x01d4237#define RK3368_CABC_GAUSS_LINE1_0 0x01d8238#define RK3368_CABC_GAUSS_LINE1_1 0x01dc239#define RK3368_CABC_GAUSS_LINE2_0 0x01e0240#define RK3368_CABC_GAUSS_LINE2_1 0x01e4241#define RK3368_FRC_LOWER01_0 0x01e8242#define RK3368_FRC_LOWER01_1 0x01ec243#define RK3368_FRC_LOWER10_0 0x01f0244#define RK3368_FRC_LOWER10_1 0x01f4245#define RK3368_FRC_LOWER11_0 0x01f8246#define RK3368_FRC_LOWER11_1 0x01fc247#define RK3368_IFBDC_CTRL 0x0200248#define RK3368_IFBDC_TILES_NUM 0x0204249#define RK3368_IFBDC_FRAME_RST_CYCLE 0x0208250#define RK3368_IFBDC_BASE_ADDR 0x020c251#define RK3368_IFBDC_MB_SIZE 0x0210252#define RK3368_IFBDC_CMP_INDEX_INIT 0x0214253#define RK3368_IFBDC_VIR 0x0220254#define RK3368_IFBDC_DEBUG0 0x0230255#define RK3368_IFBDC_DEBUG1 0x0234256#define RK3368_LATENCY_CTRL0 0x0250257#define RK3368_RD_MAX_LATENCY_NUM0 0x0254258#define RK3368_RD_LATENCY_THR_NUM0 0x0258259#define RK3368_RD_LATENCY_SAMP_NUM0 0x025c260#define RK3368_WIN0_DSP_BG 0x0260261#define RK3368_WIN1_DSP_BG 0x0264262#define RK3368_WIN2_DSP_BG 0x0268263#define RK3368_WIN3_DSP_BG 0x026c264#define RK3368_SCAN_LINE_NUM 0x0270265#define RK3368_CABC_DEBUG0 0x0274266#define RK3368_CABC_DEBUG1 0x0278267#define RK3368_CABC_DEBUG2 0x027c268#define RK3368_DBG_REG_000 0x0280269#define RK3368_DBG_REG_001 0x0284270#define RK3368_DBG_REG_002 0x0288271#define RK3368_DBG_REG_003 0x028c272#define RK3368_DBG_REG_004 0x0290273#define RK3368_DBG_REG_005 0x0294274#define RK3368_DBG_REG_006 0x0298275#define RK3368_DBG_REG_007 0x029c276#define RK3368_DBG_REG_008 0x02a0277#define RK3368_DBG_REG_016 0x02c0278#define RK3368_DBG_REG_017 0x02c4279#define RK3368_DBG_REG_018 0x02c8280#define RK3368_DBG_REG_019 0x02cc281#define RK3368_DBG_REG_020 0x02d0282#define RK3368_DBG_REG_021 0x02d4283#define RK3368_DBG_REG_022 0x02d8284#define RK3368_DBG_REG_023 0x02dc285#define RK3368_DBG_REG_028 0x02f0286#define RK3368_MMU_DTE_ADDR 0x0300287#define RK3368_MMU_STATUS 0x0304288#define RK3368_MMU_COMMAND 0x0308289#define RK3368_MMU_PAGE_FAULT_ADDR 0x030c290#define RK3368_MMU_ZAP_ONE_LINE 0x0310291#define RK3368_MMU_INT_RAWSTAT 0x0314292#define RK3368_MMU_INT_CLEAR 0x0318293#define RK3368_MMU_INT_MASK 0x031c294#define RK3368_MMU_INT_STATUS 0x0320295#define RK3368_MMU_AUTO_GATING 0x0324296#define RK3368_WIN2_LUT_ADDR 0x0400297#define RK3368_WIN3_LUT_ADDR 0x0800298#define RK3368_HWC_LUT_ADDR 0x0c00299#define RK3368_GAMMA_LUT_ADDR 0x1000300#define RK3368_CABC_GAMMA_LUT_ADDR 0x1800301#define RK3368_MCU_BYPASS_WPORT 0x2200302#define RK3368_MCU_BYPASS_RPORT 0x2300303/* rk3368 register definition end */304 305#define RK3366_REG_CFG_DONE 0x0000306#define RK3366_VERSION_INFO 0x0004307#define RK3366_SYS_CTRL 0x0008308#define RK3366_SYS_CTRL1 0x000c309#define RK3366_DSP_CTRL0 0x0010310#define RK3366_DSP_CTRL1 0x0014311#define RK3366_DSP_BG 0x0018312#define RK3366_MCU_CTRL 0x001c313#define RK3366_WB_CTRL0 0x0020314#define RK3366_WB_CTRL1 0x0024315#define RK3366_WB_YRGB_MST 0x0028316#define RK3366_WB_CBR_MST 0x002c317#define RK3366_WIN0_CTRL0 0x0030318#define RK3366_WIN0_CTRL1 0x0034319#define RK3366_WIN0_COLOR_KEY 0x0038320#define RK3366_WIN0_VIR 0x003c321#define RK3366_WIN0_YRGB_MST 0x0040322#define RK3366_WIN0_CBR_MST 0x0044323#define RK3366_WIN0_ACT_INFO 0x0048324#define RK3366_WIN0_DSP_INFO 0x004c325#define RK3366_WIN0_DSP_ST 0x0050326#define RK3366_WIN0_SCL_FACTOR_YRGB 0x0054327#define RK3366_WIN0_SCL_FACTOR_CBR 0x0058328#define RK3366_WIN0_SCL_OFFSET 0x005c329#define RK3366_WIN0_SRC_ALPHA_CTRL 0x0060330#define RK3366_WIN0_DST_ALPHA_CTRL 0x0064331#define RK3366_WIN0_FADING_CTRL 0x0068332#define RK3366_WIN0_CTRL2 0x006c333#define RK3366_WIN1_CTRL0 0x0070334#define RK3366_WIN1_CTRL1 0x0074335#define RK3366_WIN1_COLOR_KEY 0x0078336#define RK3366_WIN1_VIR 0x007c337#define RK3366_WIN1_YRGB_MST 0x0080338#define RK3366_WIN1_CBR_MST 0x0084339#define RK3366_WIN1_ACT_INFO 0x0088340#define RK3366_WIN1_DSP_INFO 0x008c341#define RK3366_WIN1_DSP_ST 0x0090342#define RK3366_WIN1_SCL_FACTOR_YRGB 0x0094343#define RK3366_WIN1_SCL_FACTOR_CBR 0x0098344#define RK3366_WIN1_SCL_OFFSET 0x009c345#define RK3366_WIN1_SRC_ALPHA_CTRL 0x00a0346#define RK3366_WIN1_DST_ALPHA_CTRL 0x00a4347#define RK3366_WIN1_FADING_CTRL 0x00a8348#define RK3366_WIN1_CTRL2 0x00ac349#define RK3366_WIN2_CTRL0 0x00b0350#define RK3366_WIN2_CTRL1 0x00b4351#define RK3366_WIN2_VIR0_1 0x00b8352#define RK3366_WIN2_VIR2_3 0x00bc353#define RK3366_WIN2_MST0 0x00c0354#define RK3366_WIN2_DSP_INFO0 0x00c4355#define RK3366_WIN2_DSP_ST0 0x00c8356#define RK3366_WIN2_COLOR_KEY 0x00cc357#define RK3366_WIN2_MST1 0x00d0358#define RK3366_WIN2_DSP_INFO1 0x00d4359#define RK3366_WIN2_DSP_ST1 0x00d8360#define RK3366_WIN2_SRC_ALPHA_CTRL 0x00dc361#define RK3366_WIN2_MST2 0x00e0362#define RK3366_WIN2_DSP_INFO2 0x00e4363#define RK3366_WIN2_DSP_ST2 0x00e8364#define RK3366_WIN2_DST_ALPHA_CTRL 0x00ec365#define RK3366_WIN2_MST3 0x00f0366#define RK3366_WIN2_DSP_INFO3 0x00f4367#define RK3366_WIN2_DSP_ST3 0x00f8368#define RK3366_WIN2_FADING_CTRL 0x00fc369#define RK3366_WIN3_CTRL0 0x0100370#define RK3366_WIN3_CTRL1 0x0104371#define RK3366_WIN3_VIR0_1 0x0108372#define RK3366_WIN3_VIR2_3 0x010c373#define RK3366_WIN3_MST0 0x0110374#define RK3366_WIN3_DSP_INFO0 0x0114375#define RK3366_WIN3_DSP_ST0 0x0118376#define RK3366_WIN3_COLOR_KEY 0x011c377#define RK3366_WIN3_MST1 0x0120378#define RK3366_WIN3_DSP_INFO1 0x0124379#define RK3366_WIN3_DSP_ST1 0x0128380#define RK3366_WIN3_SRC_ALPHA_CTRL 0x012c381#define RK3366_WIN3_MST2 0x0130382#define RK3366_WIN3_DSP_INFO2 0x0134383#define RK3366_WIN3_DSP_ST2 0x0138384#define RK3366_WIN3_DST_ALPHA_CTRL 0x013c385#define RK3366_WIN3_MST3 0x0140386#define RK3366_WIN3_DSP_INFO3 0x0144387#define RK3366_WIN3_DSP_ST3 0x0148388#define RK3366_WIN3_FADING_CTRL 0x014c389#define RK3366_HWC_CTRL0 0x0150390#define RK3366_HWC_CTRL1 0x0154391#define RK3366_HWC_MST 0x0158392#define RK3366_HWC_DSP_ST 0x015c393#define RK3366_HWC_SRC_ALPHA_CTRL 0x0160394#define RK3366_HWC_DST_ALPHA_CTRL 0x0164395#define RK3366_HWC_FADING_CTRL 0x0168396#define RK3366_HWC_RESERVED1 0x016c397#define RK3366_POST_DSP_HACT_INFO 0x0170398#define RK3366_POST_DSP_VACT_INFO 0x0174399#define RK3366_POST_SCL_FACTOR_YRGB 0x0178400#define RK3366_POST_RESERVED 0x017c401#define RK3366_POST_SCL_CTRL 0x0180402#define RK3366_POST_DSP_VACT_INFO_F1 0x0184403#define RK3366_DSP_HTOTAL_HS_END 0x0188404#define RK3366_DSP_HACT_ST_END 0x018c405#define RK3366_DSP_VTOTAL_VS_END 0x0190406#define RK3366_DSP_VACT_ST_END 0x0194407#define RK3366_DSP_VS_ST_END_F1 0x0198408#define RK3366_DSP_VACT_ST_END_F1 0x019c409#define RK3366_PWM_CTRL 0x01a0410#define RK3366_PWM_PERIOD_HPR 0x01a4411#define RK3366_PWM_DUTY_LPR 0x01a8412#define RK3366_PWM_CNT 0x01ac413#define RK3366_BCSH_COLOR_BAR 0x01b0414#define RK3366_BCSH_BCS 0x01b4415#define RK3366_BCSH_H 0x01b8416#define RK3366_BCSH_CTRL 0x01bc417#define RK3366_CABC_CTRL0 0x01c0418#define RK3366_CABC_CTRL1 0x01c4419#define RK3366_CABC_CTRL2 0x01c8420#define RK3366_CABC_CTRL3 0x01cc421#define RK3366_CABC_GAUSS_LINE0_0 0x01d0422#define RK3366_CABC_GAUSS_LINE0_1 0x01d4423#define RK3366_CABC_GAUSS_LINE1_0 0x01d8424#define RK3366_CABC_GAUSS_LINE1_1 0x01dc425#define RK3366_CABC_GAUSS_LINE2_0 0x01e0426#define RK3366_CABC_GAUSS_LINE2_1 0x01e4427#define RK3366_FRC_LOWER01_0 0x01e8428#define RK3366_FRC_LOWER01_1 0x01ec429#define RK3366_FRC_LOWER10_0 0x01f0430#define RK3366_FRC_LOWER10_1 0x01f4431#define RK3366_FRC_LOWER11_0 0x01f8432#define RK3366_FRC_LOWER11_1 0x01fc433#define RK3366_INTR_EN0 0x0280434#define RK3366_INTR_CLEAR0 0x0284435#define RK3366_INTR_STATUS0 0x0288436#define RK3366_INTR_RAW_STATUS0 0x028c437#define RK3366_INTR_EN1 0x0290438#define RK3366_INTR_CLEAR1 0x0294439#define RK3366_INTR_STATUS1 0x0298440#define RK3366_INTR_RAW_STATUS1 0x029c441#define RK3366_LINE_FLAG 0x02a0442#define RK3366_VOP_STATUS 0x02a4443#define RK3366_BLANKING_VALUE 0x02a8444#define RK3366_WIN0_DSP_BG 0x02b0445#define RK3366_WIN1_DSP_BG 0x02b4446#define RK3366_WIN2_DSP_BG 0x02b8447#define RK3366_WIN3_DSP_BG 0x02bc448#define RK3366_WIN2_LUT_ADDR 0x0400449#define RK3366_WIN3_LUT_ADDR 0x0800450#define RK3366_HWC_LUT_ADDR 0x0c00451#define RK3366_GAMMA0_LUT_ADDR 0x1000452#define RK3366_GAMMA1_LUT_ADDR 0x1400453#define RK3366_CABC_GAMMA_LUT_ADDR 0x1800454#define RK3366_MCU_BYPASS_WPORT 0x2200455#define RK3366_MCU_BYPASS_RPORT 0x2300456#define RK3366_MMU_DTE_ADDR 0x2400457#define RK3366_MMU_STATUS 0x2404458#define RK3366_MMU_COMMAND 0x2408459#define RK3366_MMU_PAGE_FAULT_ADDR 0x240c460#define RK3366_MMU_ZAP_ONE_LINE 0x2410461#define RK3366_MMU_INT_RAWSTAT 0x2414462#define RK3366_MMU_INT_CLEAR 0x2418463#define RK3366_MMU_INT_MASK 0x241c464#define RK3366_MMU_INT_STATUS 0x2420465#define RK3366_MMU_AUTO_GATING 0x2424466 467/* rk3399 register definition */468#define RK3399_REG_CFG_DONE 0x0000469#define RK3399_VERSION_INFO 0x0004470#define RK3399_SYS_CTRL 0x0008471#define RK3399_SYS_CTRL1 0x000c472#define RK3399_DSP_CTRL0 0x0010473#define RK3399_DSP_CTRL1 0x0014474#define RK3399_DSP_BG 0x0018475#define RK3399_MCU_CTRL 0x001c476#define RK3399_WB_CTRL0 0x0020477#define RK3399_WB_CTRL1 0x0024478#define RK3399_WB_YRGB_MST 0x0028479#define RK3399_WB_CBR_MST 0x002c480#define RK3399_WIN0_CTRL0 0x0030481#define RK3399_WIN0_CTRL1 0x0034482#define RK3399_WIN0_COLOR_KEY 0x0038483#define RK3399_WIN0_VIR 0x003c484#define RK3399_WIN0_YRGB_MST 0x0040485#define RK3399_WIN0_CBR_MST 0x0044486#define RK3399_WIN0_ACT_INFO 0x0048487#define RK3399_WIN0_DSP_INFO 0x004c488#define RK3399_WIN0_DSP_ST 0x0050489#define RK3399_WIN0_SCL_FACTOR_YRGB 0x0054490#define RK3399_WIN0_SCL_FACTOR_CBR 0x0058491#define RK3399_WIN0_SCL_OFFSET 0x005c492#define RK3399_WIN0_SRC_ALPHA_CTRL 0x0060493#define RK3399_WIN0_DST_ALPHA_CTRL 0x0064494#define RK3399_WIN0_FADING_CTRL 0x0068495#define RK3399_WIN0_CTRL2 0x006c496#define RK3399_WIN1_CTRL0 0x0070497#define RK3399_WIN1_CTRL1 0x0074498#define RK3399_WIN1_COLOR_KEY 0x0078499#define RK3399_WIN1_VIR 0x007c500#define RK3399_WIN1_YRGB_MST 0x0080501#define RK3399_WIN1_CBR_MST 0x0084502#define RK3399_WIN1_ACT_INFO 0x0088503#define RK3399_WIN1_DSP_INFO 0x008c504#define RK3399_WIN1_DSP_ST 0x0090505#define RK3399_WIN1_SCL_FACTOR_YRGB 0x0094506#define RK3399_WIN1_SCL_FACTOR_CBR 0x0098507#define RK3399_WIN1_SCL_OFFSET 0x009c508#define RK3399_WIN1_SRC_ALPHA_CTRL 0x00a0509#define RK3399_WIN1_DST_ALPHA_CTRL 0x00a4510#define RK3399_WIN1_FADING_CTRL 0x00a8511#define RK3399_WIN1_CTRL2 0x00ac512#define RK3399_WIN2_CTRL0 0x00b0513#define RK3399_WIN2_CTRL1 0x00b4514#define RK3399_WIN2_VIR0_1 0x00b8515#define RK3399_WIN2_VIR2_3 0x00bc516#define RK3399_WIN2_MST0 0x00c0517#define RK3399_WIN2_DSP_INFO0 0x00c4518#define RK3399_WIN2_DSP_ST0 0x00c8519#define RK3399_WIN2_COLOR_KEY 0x00cc520#define RK3399_WIN2_MST1 0x00d0521#define RK3399_WIN2_DSP_INFO1 0x00d4522#define RK3399_WIN2_DSP_ST1 0x00d8523#define RK3399_WIN2_SRC_ALPHA_CTRL 0x00dc524#define RK3399_WIN2_MST2 0x00e0525#define RK3399_WIN2_DSP_INFO2 0x00e4526#define RK3399_WIN2_DSP_ST2 0x00e8527#define RK3399_WIN2_DST_ALPHA_CTRL 0x00ec528#define RK3399_WIN2_MST3 0x00f0529#define RK3399_WIN2_DSP_INFO3 0x00f4530#define RK3399_WIN2_DSP_ST3 0x00f8531#define RK3399_WIN2_FADING_CTRL 0x00fc532#define RK3399_WIN3_CTRL0 0x0100533#define RK3399_WIN3_CTRL1 0x0104534#define RK3399_WIN3_VIR0_1 0x0108535#define RK3399_WIN3_VIR2_3 0x010c536#define RK3399_WIN3_MST0 0x0110537#define RK3399_WIN3_DSP_INFO0 0x0114538#define RK3399_WIN3_DSP_ST0 0x0118539#define RK3399_WIN3_COLOR_KEY 0x011c540#define RK3399_WIN3_MST1 0x0120541#define RK3399_WIN3_DSP_INFO1 0x0124542#define RK3399_WIN3_DSP_ST1 0x0128543#define RK3399_WIN3_SRC_ALPHA_CTRL 0x012c544#define RK3399_WIN3_MST2 0x0130545#define RK3399_WIN3_DSP_INFO2 0x0134546#define RK3399_WIN3_DSP_ST2 0x0138547#define RK3399_WIN3_DST_ALPHA_CTRL 0x013c548#define RK3399_WIN3_MST3 0x0140549#define RK3399_WIN3_DSP_INFO3 0x0144550#define RK3399_WIN3_DSP_ST3 0x0148551#define RK3399_WIN3_FADING_CTRL 0x014c552#define RK3399_HWC_CTRL0 0x0150553#define RK3399_HWC_CTRL1 0x0154554#define RK3399_HWC_MST 0x0158555#define RK3399_HWC_DSP_ST 0x015c556#define RK3399_HWC_SRC_ALPHA_CTRL 0x0160557#define RK3399_HWC_DST_ALPHA_CTRL 0x0164558#define RK3399_HWC_FADING_CTRL 0x0168559#define RK3399_HWC_RESERVED1 0x016c560#define RK3399_POST_DSP_HACT_INFO 0x0170561#define RK3399_POST_DSP_VACT_INFO 0x0174562#define RK3399_POST_SCL_FACTOR_YRGB 0x0178563#define RK3399_POST_RESERVED 0x017c564#define RK3399_POST_SCL_CTRL 0x0180565#define RK3399_POST_DSP_VACT_INFO_F1 0x0184566#define RK3399_DSP_HTOTAL_HS_END 0x0188567#define RK3399_DSP_HACT_ST_END 0x018c568#define RK3399_DSP_VTOTAL_VS_END 0x0190569#define RK3399_DSP_VACT_ST_END 0x0194570#define RK3399_DSP_VS_ST_END_F1 0x0198571#define RK3399_DSP_VACT_ST_END_F1 0x019c572#define RK3399_PWM_CTRL 0x01a0573#define RK3399_PWM_PERIOD_HPR 0x01a4574#define RK3399_PWM_DUTY_LPR 0x01a8575#define RK3399_PWM_CNT 0x01ac576#define RK3399_BCSH_COLOR_BAR 0x01b0577#define RK3399_BCSH_BCS 0x01b4578#define RK3399_BCSH_H 0x01b8579#define RK3399_BCSH_CTRL 0x01bc580#define RK3399_CABC_CTRL0 0x01c0581#define RK3399_CABC_CTRL1 0x01c4582#define RK3399_CABC_CTRL2 0x01c8583#define RK3399_CABC_CTRL3 0x01cc584#define RK3399_CABC_GAUSS_LINE0_0 0x01d0585#define RK3399_CABC_GAUSS_LINE0_1 0x01d4586#define RK3399_CABC_GAUSS_LINE1_0 0x01d8587#define RK3399_CABC_GAUSS_LINE1_1 0x01dc588#define RK3399_CABC_GAUSS_LINE2_0 0x01e0589#define RK3399_CABC_GAUSS_LINE2_1 0x01e4590#define RK3399_FRC_LOWER01_0 0x01e8591#define RK3399_FRC_LOWER01_1 0x01ec592#define RK3399_FRC_LOWER10_0 0x01f0593#define RK3399_FRC_LOWER10_1 0x01f4594#define RK3399_FRC_LOWER11_0 0x01f8595#define RK3399_FRC_LOWER11_1 0x01fc596#define RK3399_AFBCD0_CTRL 0x0200597#define RK3399_AFBCD0_HDR_PTR 0x0204598#define RK3399_AFBCD0_PIC_SIZE 0x0208599#define RK3399_AFBCD0_STATUS 0x020c600#define RK3399_AFBCD1_CTRL 0x0220601#define RK3399_AFBCD1_HDR_PTR 0x0224602#define RK3399_AFBCD1_PIC_SIZE 0x0228603#define RK3399_AFBCD1_STATUS 0x022c604#define RK3399_AFBCD2_CTRL 0x0240605#define RK3399_AFBCD2_HDR_PTR 0x0244606#define RK3399_AFBCD2_PIC_SIZE 0x0248607#define RK3399_AFBCD2_STATUS 0x024c608#define RK3399_AFBCD3_CTRL 0x0260609#define RK3399_AFBCD3_HDR_PTR 0x0264610#define RK3399_AFBCD3_PIC_SIZE 0x0268611#define RK3399_AFBCD3_STATUS 0x026c612#define RK3399_INTR_EN0 0x0280613#define RK3399_INTR_CLEAR0 0x0284614#define RK3399_INTR_STATUS0 0x0288615#define RK3399_INTR_RAW_STATUS0 0x028c616#define RK3399_INTR_EN1 0x0290617#define RK3399_INTR_CLEAR1 0x0294618#define RK3399_INTR_STATUS1 0x0298619#define RK3399_INTR_RAW_STATUS1 0x029c620#define RK3399_LINE_FLAG 0x02a0621#define RK3399_VOP_STATUS 0x02a4622#define RK3399_BLANKING_VALUE 0x02a8623#define RK3399_MCU_BYPASS_PORT 0x02ac624#define RK3399_WIN0_DSP_BG 0x02b0625#define RK3399_WIN1_DSP_BG 0x02b4626#define RK3399_WIN2_DSP_BG 0x02b8627#define RK3399_WIN3_DSP_BG 0x02bc628#define RK3399_YUV2YUV_WIN 0x02c0629#define RK3399_YUV2YUV_POST 0x02c4630#define RK3399_AUTO_GATING_EN 0x02cc631#define RK3399_DBG_POST_REG1 0x036c632#define RK3399_WIN0_CSC_COE 0x03a0633#define RK3399_WIN1_CSC_COE 0x03c0634#define RK3399_WIN2_CSC_COE 0x03e0635#define RK3399_WIN3_CSC_COE 0x0400636#define RK3399_HWC_CSC_COE 0x0420637#define RK3399_BCSH_R2Y_CSC_COE 0x0440638#define RK3399_BCSH_Y2R_CSC_COE 0x0460639#define RK3399_POST_YUV2YUV_Y2R_COE 0x0480640#define RK3399_POST_YUV2YUV_3X3_COE 0x04a0641#define RK3399_POST_YUV2YUV_R2Y_COE 0x04c0642#define RK3399_WIN0_YUV2YUV_Y2R 0x04e0643#define RK3399_WIN0_YUV2YUV_3X3 0x0500644#define RK3399_WIN0_YUV2YUV_R2Y 0x0520645#define RK3399_WIN1_YUV2YUV_Y2R 0x0540646#define RK3399_WIN1_YUV2YUV_3X3 0x0560647#define RK3399_WIN1_YUV2YUV_R2Y 0x0580648#define RK3399_WIN2_YUV2YUV_Y2R 0x05a0649#define RK3399_WIN2_YUV2YUV_3X3 0x05c0650#define RK3399_WIN2_YUV2YUV_R2Y 0x05e0651#define RK3399_WIN3_YUV2YUV_Y2R 0x0600652#define RK3399_WIN3_YUV2YUV_3X3 0x0620653#define RK3399_WIN3_YUV2YUV_R2Y 0x0640654#define RK3399_WIN2_LUT_ADDR 0x1000655#define RK3399_WIN3_LUT_ADDR 0x1400656#define RK3399_HWC_LUT_ADDR 0x1800657#define RK3399_CABC_GAMMA_LUT_ADDR 0x1c00658#define RK3399_GAMMA_LUT_ADDR 0x2000659/* rk3399 register definition end */660 661/* rk3328 register definition end */662#define RK3328_REG_CFG_DONE 0x00000000663#define RK3328_VERSION_INFO 0x00000004664#define RK3328_SYS_CTRL 0x00000008665#define RK3328_SYS_CTRL1 0x0000000c666#define RK3328_DSP_CTRL0 0x00000010667#define RK3328_DSP_CTRL1 0x00000014668#define RK3328_DSP_BG 0x00000018669#define RK3328_AUTO_GATING_EN 0x0000003c670#define RK3328_LINE_FLAG 0x00000040671#define RK3328_VOP_STATUS 0x00000044672#define RK3328_BLANKING_VALUE 0x00000048673#define RK3328_WIN0_DSP_BG 0x00000050674#define RK3328_WIN1_DSP_BG 0x00000054675#define RK3328_DBG_PERF_LATENCY_CTRL0 0x000000c0676#define RK3328_DBG_PERF_RD_MAX_LATENCY_NUM0 0x000000c4677#define RK3328_DBG_PERF_RD_LATENCY_THR_NUM0 0x000000c8678#define RK3328_DBG_PERF_RD_LATENCY_SAMP_NUM0 0x000000cc679#define RK3328_INTR_EN0 0x000000e0680#define RK3328_INTR_CLEAR0 0x000000e4681#define RK3328_INTR_STATUS0 0x000000e8682#define RK3328_INTR_RAW_STATUS0 0x000000ec683#define RK3328_INTR_EN1 0x000000f0684#define RK3328_INTR_CLEAR1 0x000000f4685#define RK3328_INTR_STATUS1 0x000000f8686#define RK3328_INTR_RAW_STATUS1 0x000000fc687#define RK3328_WIN0_CTRL0 0x00000100688#define RK3328_WIN0_CTRL1 0x00000104689#define RK3328_WIN0_COLOR_KEY 0x00000108690#define RK3328_WIN0_VIR 0x0000010c691#define RK3328_WIN0_YRGB_MST 0x00000110692#define RK3328_WIN0_CBR_MST 0x00000114693#define RK3328_WIN0_ACT_INFO 0x00000118694#define RK3328_WIN0_DSP_INFO 0x0000011c695#define RK3328_WIN0_DSP_ST 0x00000120696#define RK3328_WIN0_SCL_FACTOR_YRGB 0x00000124697#define RK3328_WIN0_SCL_FACTOR_CBR 0x00000128698#define RK3328_WIN0_SCL_OFFSET 0x0000012c699#define RK3328_WIN0_SRC_ALPHA_CTRL 0x00000130700#define RK3328_WIN0_DST_ALPHA_CTRL 0x00000134701#define RK3328_WIN0_FADING_CTRL 0x00000138702#define RK3328_WIN0_CTRL2 0x0000013c703#define RK3328_DBG_WIN0_REG0 0x000001f0704#define RK3328_DBG_WIN0_REG1 0x000001f4705#define RK3328_DBG_WIN0_REG2 0x000001f8706#define RK3328_DBG_WIN0_RESERVED 0x000001fc707#define RK3328_WIN1_CTRL0 0x00000200708#define RK3328_WIN1_CTRL1 0x00000204709#define RK3328_WIN1_COLOR_KEY 0x00000208710#define RK3328_WIN1_VIR 0x0000020c711#define RK3328_WIN1_YRGB_MST 0x00000210712#define RK3328_WIN1_CBR_MST 0x00000214713#define RK3328_WIN1_ACT_INFO 0x00000218714#define RK3328_WIN1_DSP_INFO 0x0000021c715#define RK3328_WIN1_DSP_ST 0x00000220716#define RK3328_WIN1_SCL_FACTOR_YRGB 0x00000224717#define RK3328_WIN1_SCL_FACTOR_CBR 0x00000228718#define RK3328_WIN1_SCL_OFFSET 0x0000022c719#define RK3328_WIN1_SRC_ALPHA_CTRL 0x00000230720#define RK3328_WIN1_DST_ALPHA_CTRL 0x00000234721#define RK3328_WIN1_FADING_CTRL 0x00000238722#define RK3328_WIN1_CTRL2 0x0000023c723#define RK3328_DBG_WIN1_REG0 0x000002f0724#define RK3328_DBG_WIN1_REG1 0x000002f4725#define RK3328_DBG_WIN1_REG2 0x000002f8726#define RK3328_DBG_WIN1_RESERVED 0x000002fc727#define RK3328_WIN2_CTRL0 0x00000300728#define RK3328_WIN2_CTRL1 0x00000304729#define RK3328_WIN2_COLOR_KEY 0x00000308730#define RK3328_WIN2_VIR 0x0000030c731#define RK3328_WIN2_YRGB_MST 0x00000310732#define RK3328_WIN2_CBR_MST 0x00000314733#define RK3328_WIN2_ACT_INFO 0x00000318734#define RK3328_WIN2_DSP_INFO 0x0000031c735#define RK3328_WIN2_DSP_ST 0x00000320736#define RK3328_WIN2_SCL_FACTOR_YRGB 0x00000324737#define RK3328_WIN2_SCL_FACTOR_CBR 0x00000328738#define RK3328_WIN2_SCL_OFFSET 0x0000032c739#define RK3328_WIN2_SRC_ALPHA_CTRL 0x00000330740#define RK3328_WIN2_DST_ALPHA_CTRL 0x00000334741#define RK3328_WIN2_FADING_CTRL 0x00000338742#define RK3328_WIN2_CTRL2 0x0000033c743#define RK3328_DBG_WIN2_REG0 0x000003f0744#define RK3328_DBG_WIN2_REG1 0x000003f4745#define RK3328_DBG_WIN2_REG2 0x000003f8746#define RK3328_DBG_WIN2_RESERVED 0x000003fc747#define RK3328_WIN3_CTRL0 0x00000400748#define RK3328_WIN3_CTRL1 0x00000404749#define RK3328_WIN3_COLOR_KEY 0x00000408750#define RK3328_WIN3_VIR 0x0000040c751#define RK3328_WIN3_YRGB_MST 0x00000410752#define RK3328_WIN3_CBR_MST 0x00000414753#define RK3328_WIN3_ACT_INFO 0x00000418754#define RK3328_WIN3_DSP_INFO 0x0000041c755#define RK3328_WIN3_DSP_ST 0x00000420756#define RK3328_WIN3_SCL_FACTOR_YRGB 0x00000424757#define RK3328_WIN3_SCL_FACTOR_CBR 0x00000428758#define RK3328_WIN3_SCL_OFFSET 0x0000042c759#define RK3328_WIN3_SRC_ALPHA_CTRL 0x00000430760#define RK3328_WIN3_DST_ALPHA_CTRL 0x00000434761#define RK3328_WIN3_FADING_CTRL 0x00000438762#define RK3328_WIN3_CTRL2 0x0000043c763#define RK3328_DBG_WIN3_REG0 0x000004f0764#define RK3328_DBG_WIN3_REG1 0x000004f4765#define RK3328_DBG_WIN3_REG2 0x000004f8766#define RK3328_DBG_WIN3_RESERVED 0x000004fc767 768#define RK3328_HWC_CTRL0 0x00000500769#define RK3328_HWC_CTRL1 0x00000504770#define RK3328_HWC_MST 0x00000508771#define RK3328_HWC_DSP_ST 0x0000050c772#define RK3328_HWC_SRC_ALPHA_CTRL 0x00000510773#define RK3328_HWC_DST_ALPHA_CTRL 0x00000514774#define RK3328_HWC_FADING_CTRL 0x00000518775#define RK3328_HWC_RESERVED1 0x0000051c776#define RK3328_POST_DSP_HACT_INFO 0x00000600777#define RK3328_POST_DSP_VACT_INFO 0x00000604778#define RK3328_POST_SCL_FACTOR_YRGB 0x00000608779#define RK3328_POST_RESERVED 0x0000060c780#define RK3328_POST_SCL_CTRL 0x00000610781#define RK3328_POST_DSP_VACT_INFO_F1 0x00000614782#define RK3328_DSP_HTOTAL_HS_END 0x00000618783#define RK3328_DSP_HACT_ST_END 0x0000061c784#define RK3328_DSP_VTOTAL_VS_END 0x00000620785#define RK3328_DSP_VACT_ST_END 0x00000624786#define RK3328_DSP_VS_ST_END_F1 0x00000628787#define RK3328_DSP_VACT_ST_END_F1 0x0000062c788#define RK3328_BCSH_COLOR_BAR 0x00000640789#define RK3328_BCSH_BCS 0x00000644790#define RK3328_BCSH_H 0x00000648791#define RK3328_BCSH_CTRL 0x0000064c792#define RK3328_FRC_LOWER01_0 0x00000678793#define RK3328_FRC_LOWER01_1 0x0000067c794#define RK3328_FRC_LOWER10_0 0x00000680795#define RK3328_FRC_LOWER10_1 0x00000684796#define RK3328_FRC_LOWER11_0 0x00000688797#define RK3328_FRC_LOWER11_1 0x0000068c798#define RK3328_DBG_POST_REG0 0x000006e8799#define RK3328_DBG_POST_RESERVED 0x000006ec800#define RK3328_DBG_DATAO 0x000006f0801#define RK3328_DBG_DATAO_2 0x000006f4802 803/* sdr to hdr */804#define RK3328_SDR2HDR_CTRL 0x00000700805#define RK3328_EOTF_OETF_Y0 0x00000704806#define RK3328_RESERVED0001 0x00000708807#define RK3328_RESERVED0002 0x0000070c808#define RK3328_EOTF_OETF_Y1 0x00000710809#define RK3328_EOTF_OETF_Y64 0x0000080c810#define RK3328_OETF_DX_DXPOW1 0x00000810811#define RK3328_OETF_DX_DXPOW64 0x0000090c812#define RK3328_OETF_XN1 0x00000910813#define RK3328_OETF_XN63 0x00000a08814 815/* hdr to sdr */816#define RK3328_HDR2SDR_CTRL 0x00000a10817#define RK3328_HDR2SDR_SRC_RANGE 0x00000a14818#define RK3328_HDR2SDR_NORMFACEETF 0x00000a18819#define RK3328_RESERVED0003 0x00000a1c820#define RK3328_HDR2SDR_DST_RANGE 0x00000a20821#define RK3328_HDR2SDR_NORMFACCGAMMA 0x00000a24822#define RK3328_EETF_OETF_Y0 0x00000a28823#define RK3328_SAT_Y0 0x00000a2c824#define RK3328_EETF_OETF_Y1 0x00000a30825#define RK3328_SAT_Y1 0x00000ab0826#define RK3328_SAT_Y8 0x00000acc827 828#define RK3328_HWC_LUT_ADDR 0x00000c00829 830/* rk3036 register definition */831#define RK3036_SYS_CTRL 0x00832#define RK3036_DSP_CTRL0 0x04833#define RK3036_DSP_CTRL1 0x08834#define RK3036_INT_STATUS 0x10835#define RK3036_ALPHA_CTRL 0x14836#define RK3036_WIN0_COLOR_KEY 0x18837#define RK3036_WIN1_COLOR_KEY 0x1c838#define RK3036_WIN0_YRGB_MST 0x20839#define RK3036_WIN0_CBR_MST 0x24840#define RK3036_WIN1_VIR 0x28841#define RK3036_AXI_BUS_CTRL 0x2c842#define RK3036_WIN0_VIR 0x30843#define RK3036_WIN0_ACT_INFO 0x34844#define RK3036_WIN0_DSP_INFO 0x38845#define RK3036_WIN0_DSP_ST 0x3c846#define RK3036_WIN0_SCL_FACTOR_YRGB 0x40847#define RK3036_WIN0_SCL_FACTOR_CBR 0x44848#define RK3036_WIN0_SCL_OFFSET 0x48849#define RK3036_HWC_MST 0x58850#define RK3036_HWC_DSP_ST 0x5c851#define RK3036_DSP_HTOTAL_HS_END 0x6c852#define RK3036_DSP_HACT_ST_END 0x70853#define RK3036_DSP_VTOTAL_VS_END 0x74854#define RK3036_DSP_VACT_ST_END 0x78855#define RK3036_DSP_VS_ST_END_F1 0x7c856#define RK3036_DSP_VACT_ST_END_F1 0x80857#define RK3036_GATHER_TRANSFER 0x84858#define RK3036_VERSION_INFO 0x94859#define RK3036_REG_CFG_DONE 0x90860#define RK3036_WIN1_MST 0xa0861#define RK3036_WIN1_ACT_INFO 0xb4862#define RK3036_WIN1_DSP_INFO 0xb8863#define RK3036_WIN1_DSP_ST 0xbc864#define RK3036_WIN1_SCL_FACTOR_YRGB 0xc0865#define RK3036_WIN1_SCL_OFFSET 0xc8866#define RK3036_BCSH_CTRL 0xd0867#define RK3036_BCSH_COLOR_BAR 0xd4868#define RK3036_BCSH_BCS 0xd8869#define RK3036_BCSH_H 0xdc870#define RK3036_WIN1_LUT_ADDR 0x400871#define RK3036_HWC_LUT_ADDR 0x800872/* rk3036 register definition end */873 874/* rk3126 register definition */875#define RK3126_INT_SCALER 0x0c876 877/* win1 register */878#define RK3126_WIN1_MST 0x4c879#define RK3126_WIN1_DSP_INFO 0x50880#define RK3126_WIN1_DSP_ST 0x54881/* rk3126 register definition end */882 883/* px30 register definition */884#define PX30_REG_CFG_DONE 0x00000885#define PX30_VERSION 0x00004886#define PX30_DSP_BG 0x00008887#define PX30_MCU_CTRL 0x0000c888#define PX30_SYS_CTRL0 0x00010889#define PX30_SYS_CTRL1 0x00014890#define PX30_SYS_CTRL2 0x00018891#define PX30_DSP_CTRL0 0x00020892#define PX30_DSP_CTRL2 0x00028893#define PX30_VOP_STATUS 0x0002c894#define PX30_LINE_FLAG 0x00030895#define PX30_INTR_EN 0x00034896#define PX30_INTR_CLEAR 0x00038897#define PX30_INTR_STATUS 0x0003c898#define PX30_WIN0_CTRL0 0x00050899#define PX30_WIN0_CTRL1 0x00054900#define PX30_WIN0_COLOR_KEY 0x00058901#define PX30_WIN0_VIR 0x0005c902#define PX30_WIN0_YRGB_MST0 0x00060903#define PX30_WIN0_CBR_MST0 0x00064904#define PX30_WIN0_ACT_INFO 0x00068905#define PX30_WIN0_DSP_INFO 0x0006c906#define PX30_WIN0_DSP_ST 0x00070907#define PX30_WIN0_SCL_FACTOR_YRGB 0x00074908#define PX30_WIN0_SCL_FACTOR_CBR 0x00078909#define PX30_WIN0_SCL_OFFSET 0x0007c910#define PX30_WIN0_ALPHA_CTRL 0x00080911#define PX30_WIN1_CTRL0 0x00090912#define PX30_WIN1_CTRL1 0x00094913#define PX30_WIN1_VIR 0x00098914#define PX30_WIN1_MST 0x000a0915#define PX30_WIN1_DSP_INFO 0x000a4916#define PX30_WIN1_DSP_ST 0x000a8917#define PX30_WIN1_COLOR_KEY 0x000ac918#define PX30_WIN1_ALPHA_CTRL 0x000bc919#define PX30_HWC_CTRL0 0x000e0920#define PX30_HWC_CTRL1 0x000e4921#define PX30_HWC_MST 0x000e8922#define PX30_HWC_DSP_ST 0x000ec923#define PX30_HWC_ALPHA_CTRL 0x000f0924#define PX30_DSP_HTOTAL_HS_END 0x00100925#define PX30_DSP_HACT_ST_END 0x00104926#define PX30_DSP_VTOTAL_VS_END 0x00108927#define PX30_DSP_VACT_ST_END 0x0010c928#define PX30_DSP_VS_ST_END_F1 0x00110929#define PX30_DSP_VACT_ST_END_F1 0x00114930#define PX30_BCSH_CTRL 0x00160931#define PX30_BCSH_COL_BAR 0x00164932#define PX30_BCSH_BCS 0x00168933#define PX30_BCSH_H 0x0016c934#define PX30_FRC_LOWER01_0 0x00170935#define PX30_FRC_LOWER01_1 0x00174936#define PX30_FRC_LOWER10_0 0x00178937#define PX30_FRC_LOWER10_1 0x0017c938#define PX30_FRC_LOWER11_0 0x00180939#define PX30_FRC_LOWER11_1 0x00184940#define PX30_MCU_RW_BYPASS_PORT 0x0018c941#define PX30_WIN2_CTRL0 0x00190942#define PX30_WIN2_CTRL1 0x00194943#define PX30_WIN2_VIR0_1 0x00198944#define PX30_WIN2_VIR2_3 0x0019c945#define PX30_WIN2_MST0 0x001a0946#define PX30_WIN2_DSP_INFO0 0x001a4947#define PX30_WIN2_DSP_ST0 0x001a8948#define PX30_WIN2_COLOR_KEY 0x001ac949#define PX30_WIN2_ALPHA_CTRL 0x001bc950#define PX30_BLANKING_VALUE 0x001f4951#define PX30_FLAG_REG_FRM_VALID 0x001f8952#define PX30_FLAG_REG 0x001fc953#define PX30_HWC_LUT_ADDR 0x00600954#define PX30_GAMMA_LUT_ADDR 0x00a00955/* px30 register definition end */956 957/* rk3188 register definition */958#define RK3188_SYS_CTRL 0x00959#define RK3188_DSP_CTRL0 0x04960#define RK3188_DSP_CTRL1 0x08961#define RK3188_INT_STATUS 0x10962#define RK3188_ALPHA_CTRL 0x14963#define RK3188_WIN0_YRGB_MST0 0x20964#define RK3188_WIN0_CBR_MST0 0x24965#define RK3188_WIN0_YRGB_MST1 0x28966#define RK3188_WIN0_CBR_MST1 0x2c967#define RK3188_WIN_VIR 0x30968#define RK3188_WIN0_ACT_INFO 0x34969#define RK3188_WIN0_DSP_INFO 0x38970#define RK3188_WIN0_DSP_ST 0x3c971#define RK3188_WIN0_SCL_FACTOR_YRGB 0x40972#define RK3188_WIN0_SCL_FACTOR_CBR 0x44973#define RK3188_WIN1_MST 0x4c974#define RK3188_WIN1_DSP_INFO 0x50975#define RK3188_WIN1_DSP_ST 0x54976#define RK3188_DSP_HTOTAL_HS_END 0x6c977#define RK3188_DSP_HACT_ST_END 0x70978#define RK3188_DSP_VTOTAL_VS_END 0x74979#define RK3188_DSP_VACT_ST_END 0x78980#define RK3188_REG_CFG_DONE 0x90981/* rk3188 register definition end */982 983/* rk3066 register definition */984#define RK3066_SYS_CTRL0 0x00985#define RK3066_SYS_CTRL1 0x04986#define RK3066_DSP_CTRL0 0x08987#define RK3066_DSP_CTRL1 0x0c988#define RK3066_INT_STATUS 0x10989#define RK3066_MCU_CTRL 0x14990#define RK3066_BLEND_CTRL 0x18991#define RK3066_WIN0_COLOR_KEY_CTRL 0x1c992#define RK3066_WIN1_COLOR_KEY_CTRL 0x20993#define RK3066_WIN2_COLOR_KEY_CTRL 0x24994#define RK3066_WIN0_YRGB_MST0 0x28995#define RK3066_WIN0_CBR_MST0 0x2c996#define RK3066_WIN0_YRGB_MST1 0x30997#define RK3066_WIN0_CBR_MST1 0x34998#define RK3066_WIN0_VIR 0x38999#define RK3066_WIN0_ACT_INFO 0x3c1000#define RK3066_WIN0_DSP_INFO 0x401001#define RK3066_WIN0_DSP_ST 0x441002#define RK3066_WIN0_SCL_FACTOR_YRGB 0x481003#define RK3066_WIN0_SCL_FACTOR_CBR 0x4c1004#define RK3066_WIN0_SCL_OFFSET 0x501005#define RK3066_WIN1_YRGB_MST 0x541006#define RK3066_WIN1_CBR_MST 0x581007#define RK3066_WIN1_VIR 0x5c1008#define RK3066_WIN1_ACT_INFO 0x601009#define RK3066_WIN1_DSP_INFO 0x641010#define RK3066_WIN1_DSP_ST 0x681011#define RK3066_WIN1_SCL_FACTOR_YRGB 0x6c1012#define RK3066_WIN1_SCL_FACTOR_CBR 0x701013#define RK3066_WIN1_SCL_OFFSET 0x741014#define RK3066_WIN2_MST 0x781015#define RK3066_WIN2_VIR 0x7c1016#define RK3066_WIN2_DSP_INFO 0x801017#define RK3066_WIN2_DSP_ST 0x841018#define RK3066_HWC_MST 0x881019#define RK3066_HWC_DSP_ST 0x8c1020#define RK3066_HWC_COLOR_LUT0 0x901021#define RK3066_HWC_COLOR_LUT1 0x941022#define RK3066_HWC_COLOR_LUT2 0x981023#define RK3066_DSP_HTOTAL_HS_END 0x9c1024#define RK3066_DSP_HACT_ST_END 0xa01025#define RK3066_DSP_VTOTAL_VS_END 0xa41026#define RK3066_DSP_VACT_ST_END 0xa81027#define RK3066_DSP_VS_ST_END_F1 0xac1028#define RK3066_DSP_VACT_ST_END_F1 0xb01029#define RK3066_REG_CFG_DONE 0xc01030#define RK3066_MCU_BYPASS_WPORT 0x1001031#define RK3066_MCU_BYPASS_RPORT 0x2001032#define RK3066_WIN2_LUT_ADDR 0x4001033#define RK3066_DSP_LUT_ADDR 0x8001034/* rk3066 register definition end */1035 1036#endif /* _ROCKCHIP_VOP_REG_H */1037