74 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (C) 2013 NVIDIA Corporation4 */5 6#ifndef DRM_TEGRA_DPAUX_H7#define DRM_TEGRA_DPAUX_H8 9#define DPAUX_CTXSW 0x0010 11#define DPAUX_INTR_EN_AUX 0x0112#define DPAUX_INTR_AUX 0x0513#define DPAUX_INTR_AUX_DONE (1 << 3)14#define DPAUX_INTR_IRQ_EVENT (1 << 2)15#define DPAUX_INTR_UNPLUG_EVENT (1 << 1)16#define DPAUX_INTR_PLUG_EVENT (1 << 0)17 18#define DPAUX_DP_AUXDATA_WRITE(x) (0x09 + ((x) << 2))19#define DPAUX_DP_AUXDATA_READ(x) (0x19 + ((x) << 2))20#define DPAUX_DP_AUXADDR 0x2921 22#define DPAUX_DP_AUXCTL 0x2d23#define DPAUX_DP_AUXCTL_TRANSACTREQ (1 << 16)24#define DPAUX_DP_AUXCTL_CMD_AUX_RD (9 << 12)25#define DPAUX_DP_AUXCTL_CMD_AUX_WR (8 << 12)26#define DPAUX_DP_AUXCTL_CMD_MOT_RQ (6 << 12)27#define DPAUX_DP_AUXCTL_CMD_MOT_RD (5 << 12)28#define DPAUX_DP_AUXCTL_CMD_MOT_WR (4 << 12)29#define DPAUX_DP_AUXCTL_CMD_I2C_RQ (2 << 12)30#define DPAUX_DP_AUXCTL_CMD_I2C_RD (1 << 12)31#define DPAUX_DP_AUXCTL_CMD_I2C_WR (0 << 12)32#define DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY (1 << 8)33#define DPAUX_DP_AUXCTL_CMDLEN(x) ((x) & 0xff)34 35#define DPAUX_DP_AUXSTAT 0x3136#define DPAUX_DP_AUXSTAT_HPD_STATUS (1 << 28)37#define DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK (0xf0000)38#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR (1 << 11)39#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR (1 << 10)40#define DPAUX_DP_AUXSTAT_RX_ERROR (1 << 9)41#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR (1 << 8)42#define DPAUX_DP_AUXSTAT_REPLY_MASK (0xff)43 44#define DPAUX_DP_AUX_SINKSTAT_LO 0x3545#define DPAUX_DP_AUX_SINKSTAT_HI 0x3946 47#define DPAUX_HPD_CONFIG 0x3d48#define DPAUX_HPD_CONFIG_UNPLUG_MIN_TIME(x) (((x) & 0xffff) << 16)49#define DPAUX_HPD_CONFIG_PLUG_MIN_TIME(x) ((x) & 0xffff)50 51#define DPAUX_HPD_IRQ_CONFIG 0x4152#define DPAUX_HPD_IRQ_CONFIG_MIN_LOW_TIME(x) ((x) & 0xffff)53 54#define DPAUX_DP_AUX_CONFIG 0x4555 56#define DPAUX_HYBRID_PADCTL 0x4957#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV (1 << 15)58#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV (1 << 14)59#define DPAUX_HYBRID_PADCTL_AUX_CMH(x) (((x) & 0x3) << 12)60#define DPAUX_HYBRID_PADCTL_AUX_DRVZ(x) (((x) & 0x7) << 8)61#define DPAUX_HYBRID_PADCTL_AUX_DRVI(x) (((x) & 0x3f) << 2)62#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV (1 << 1)63#define DPAUX_HYBRID_PADCTL_MODE_I2C (1 << 0)64#define DPAUX_HYBRID_PADCTL_MODE_AUX (0 << 0)65 66#define DPAUX_HYBRID_SPARE 0x4d67#define DPAUX_HYBRID_SPARE_PAD_POWER_DOWN (1 << 0)68 69#define DPAUX_SCRATCH_REG0 0x5170#define DPAUX_SCRATCH_REG1 0x5571#define DPAUX_SCRATCH_REG2 0x5972 73#endif74