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1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright (C) 2012 Avionic Design GmbH4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.5 */6 7#ifndef TEGRA_HDMI_H8#define TEGRA_HDMI_H 19 10/* register definitions */11#define HDMI_CTXSW 0x0012 13#define HDMI_NV_PDISP_SOR_STATE0 0x0114#define SOR_STATE_UPDATE (1 << 0)15 16#define HDMI_NV_PDISP_SOR_STATE1 0x0217#define SOR_STATE_ASY_HEAD_OPMODE_AWAKE (2 << 0)18#define SOR_STATE_ASY_ORMODE_NORMAL (1 << 2)19#define SOR_STATE_ATTACHED (1 << 3)20 21#define HDMI_NV_PDISP_SOR_STATE2 0x0322#define SOR_STATE_ASY_OWNER_NONE (0 << 0)23#define SOR_STATE_ASY_OWNER_HEAD0 (1 << 0)24#define SOR_STATE_ASY_SUBOWNER_NONE (0 << 4)25#define SOR_STATE_ASY_SUBOWNER_SUBHEAD0 (1 << 4)26#define SOR_STATE_ASY_SUBOWNER_SUBHEAD1 (2 << 4)27#define SOR_STATE_ASY_SUBOWNER_BOTH (3 << 4)28#define SOR_STATE_ASY_CRCMODE_ACTIVE (0 << 6)29#define SOR_STATE_ASY_CRCMODE_COMPLETE (1 << 6)30#define SOR_STATE_ASY_CRCMODE_NON_ACTIVE (2 << 6)31#define SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A (1 << 8)32#define SOR_STATE_ASY_PROTOCOL_CUSTOM (15 << 8)33#define SOR_STATE_ASY_HSYNCPOL_POS (0 << 12)34#define SOR_STATE_ASY_HSYNCPOL_NEG (1 << 12)35#define SOR_STATE_ASY_VSYNCPOL_POS (0 << 13)36#define SOR_STATE_ASY_VSYNCPOL_NEG (1 << 13)37#define SOR_STATE_ASY_DEPOL_POS (0 << 14)38#define SOR_STATE_ASY_DEPOL_NEG (1 << 14)39 40#define HDMI_NV_PDISP_RG_HDCP_AN_MSB 0x0441#define HDMI_NV_PDISP_RG_HDCP_AN_LSB 0x0542#define HDMI_NV_PDISP_RG_HDCP_CN_MSB 0x0643#define HDMI_NV_PDISP_RG_HDCP_CN_LSB 0x0744#define HDMI_NV_PDISP_RG_HDCP_AKSV_MSB 0x0845#define HDMI_NV_PDISP_RG_HDCP_AKSV_LSB 0x0946#define HDMI_NV_PDISP_RG_HDCP_BKSV_MSB 0x0a47#define HDMI_NV_PDISP_RG_HDCP_BKSV_LSB 0x0b48#define HDMI_NV_PDISP_RG_HDCP_CKSV_MSB 0x0c49#define HDMI_NV_PDISP_RG_HDCP_CKSV_LSB 0x0d50#define HDMI_NV_PDISP_RG_HDCP_DKSV_MSB 0x0e51#define HDMI_NV_PDISP_RG_HDCP_DKSV_LSB 0x0f52#define HDMI_NV_PDISP_RG_HDCP_CTRL 0x1053#define HDMI_NV_PDISP_RG_HDCP_CMODE 0x1154#define HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB 0x1255#define HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB 0x1356#define HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB 0x1457#define HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2 0x1558#define HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1 0x1659#define HDMI_NV_PDISP_RG_HDCP_RI 0x1760#define HDMI_NV_PDISP_RG_HDCP_CS_MSB 0x1861#define HDMI_NV_PDISP_RG_HDCP_CS_LSB 0x1962#define HDMI_NV_PDISP_HDMI_AUDIO_EMU0 0x1a63#define HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0 0x1b64#define HDMI_NV_PDISP_HDMI_AUDIO_EMU1 0x1c65#define HDMI_NV_PDISP_HDMI_AUDIO_EMU2 0x1d66 67#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL 0x1e68#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS 0x1f69#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER 0x2070#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW 0x2171#define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH 0x2272#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL 0x2373#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS 0x2474#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER 0x2575#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW 0x2676#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH 0x2777#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW 0x2878#define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH 0x2979 80#define INFOFRAME_CTRL_ENABLE (1 << 0)81 82#define INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0)83#define INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8)84#define INFOFRAME_HEADER_LEN(x) (((x) & 0x0f) << 16)85 86#define HDMI_NV_PDISP_HDMI_GENERIC_CTRL 0x2a87#define GENERIC_CTRL_ENABLE (1 << 0)88#define GENERIC_CTRL_OTHER (1 << 4)89#define GENERIC_CTRL_SINGLE (1 << 8)90#define GENERIC_CTRL_HBLANK (1 << 12)91#define GENERIC_CTRL_AUDIO (1 << 16)92 93#define HDMI_NV_PDISP_HDMI_GENERIC_STATUS 0x2b94#define HDMI_NV_PDISP_HDMI_GENERIC_HEADER 0x2c95#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW 0x2d96#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH 0x2e97#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW 0x2f98#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH 0x3099#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW 0x31100#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH 0x32101#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW 0x33102#define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH 0x34103 104#define HDMI_NV_PDISP_HDMI_ACR_CTRL 0x35105#define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW 0x36106#define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH 0x37107#define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW 0x38108#define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH 0x39109#define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW 0x3a110#define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH 0x3b111#define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW 0x3c112#define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH 0x3d113#define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW 0x3e114#define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH 0x3f115#define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW 0x40116#define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH 0x41117#define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW 0x42118#define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH 0x43119 120#define ACR_SUBPACK_CTS(x) (((x) & 0xffffff) << 8)121#define ACR_SUBPACK_N(x) (((x) & 0xffffff) << 0)122#define ACR_ENABLE (1 << 31)123 124#define HDMI_NV_PDISP_HDMI_CTRL 0x44125#define HDMI_CTRL_REKEY(x) (((x) & 0x7f) << 0)126#define HDMI_CTRL_MAX_AC_PACKET(x) (((x) & 0x1f) << 16)127#define HDMI_CTRL_ENABLE (1 << 30)128 129#define HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT 0x45130#define HDMI_NV_PDISP_HDMI_VSYNC_WINDOW 0x46131#define VSYNC_WINDOW_END(x) (((x) & 0x3ff) << 0)132#define VSYNC_WINDOW_START(x) (((x) & 0x3ff) << 16)133#define VSYNC_WINDOW_ENABLE (1 << 31)134 135#define HDMI_NV_PDISP_HDMI_GCP_CTRL 0x47136#define HDMI_NV_PDISP_HDMI_GCP_STATUS 0x48137#define HDMI_NV_PDISP_HDMI_GCP_SUBPACK 0x49138#define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1 0x4a139#define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2 0x4b140#define HDMI_NV_PDISP_HDMI_EMU0 0x4c141#define HDMI_NV_PDISP_HDMI_EMU1 0x4d142#define HDMI_NV_PDISP_HDMI_EMU1_RDATA 0x4e143 144#define HDMI_NV_PDISP_HDMI_SPARE 0x4f145#define SPARE_HW_CTS (1 << 0)146#define SPARE_FORCE_SW_CTS (1 << 1)147#define SPARE_CTS_RESET_VAL(x) (((x) & 0x7) << 16)148 149#define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1 0x50150#define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2 0x51151#define HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL 0x53152#define HDMI_NV_PDISP_SOR_CAP 0x54153#define HDMI_NV_PDISP_SOR_PWR 0x55154#define SOR_PWR_NORMAL_STATE_PD (0 << 0)155#define SOR_PWR_NORMAL_STATE_PU (1 << 0)156#define SOR_PWR_NORMAL_START_NORMAL (0 << 1)157#define SOR_PWR_NORMAL_START_ALT (1 << 1)158#define SOR_PWR_SAFE_STATE_PD (0 << 16)159#define SOR_PWR_SAFE_STATE_PU (1 << 16)160#define SOR_PWR_SETTING_NEW_DONE (0 << 31)161#define SOR_PWR_SETTING_NEW_PENDING (1 << 31)162#define SOR_PWR_SETTING_NEW_TRIGGER (1 << 31)163 164#define HDMI_NV_PDISP_SOR_TEST 0x56165#define HDMI_NV_PDISP_SOR_PLL0 0x57166#define SOR_PLL_PWR (1 << 0)167#define SOR_PLL_PDBG (1 << 1)168#define SOR_PLL_VCAPD (1 << 2)169#define SOR_PLL_PDPORT (1 << 3)170#define SOR_PLL_RESISTORSEL (1 << 4)171#define SOR_PLL_PULLDOWN (1 << 5)172#define SOR_PLL_VCOCAP(x) (((x) & 0xf) << 8)173#define SOR_PLL_BG_V17_S(x) (((x) & 0xf) << 12)174#define SOR_PLL_FILTER(x) (((x) & 0xf) << 16)175#define SOR_PLL_ICHPMP(x) (((x) & 0xf) << 24)176#define SOR_PLL_TX_REG_LOAD(x) (((x) & 0xf) << 28)177 178#define HDMI_NV_PDISP_SOR_PLL1 0x58179#define SOR_PLL_TMDS_TERM_ENABLE (1 << 8)180#define SOR_PLL_TMDS_TERMADJ(x) (((x) & 0xf) << 9)181#define SOR_PLL_LOADADJ(x) (((x) & 0xf) << 20)182#define SOR_PLL_PE_EN (1 << 28)183#define SOR_PLL_HALF_FULL_PE (1 << 29)184#define SOR_PLL_S_D_PIN_PE (1 << 30)185 186#define HDMI_NV_PDISP_SOR_PLL2 0x59187 188#define HDMI_NV_PDISP_SOR_CSTM 0x5a189#define SOR_CSTM_ROTCLK(x) (((x) & 0xf) << 24)190#define SOR_CSTM_PLLDIV (1 << 21)191#define SOR_CSTM_LVDS_ENABLE (1 << 16)192#define SOR_CSTM_MODE_LVDS (0 << 12)193#define SOR_CSTM_MODE_TMDS (1 << 12)194#define SOR_CSTM_MODE_MASK (3 << 12)195 196#define HDMI_NV_PDISP_SOR_LVDS 0x5b197#define HDMI_NV_PDISP_SOR_CRCA 0x5c198#define HDMI_NV_PDISP_SOR_CRCB 0x5d199#define HDMI_NV_PDISP_SOR_BLANK 0x5e200#define HDMI_NV_PDISP_SOR_SEQ_CTL 0x5f201#define SOR_SEQ_PU_PC(x) (((x) & 0xf) << 0)202#define SOR_SEQ_PU_PC_ALT(x) (((x) & 0xf) << 4)203#define SOR_SEQ_PD_PC(x) (((x) & 0xf) << 8)204#define SOR_SEQ_PD_PC_ALT(x) (((x) & 0xf) << 12)205#define SOR_SEQ_PC(x) (((x) & 0xf) << 16)206#define SOR_SEQ_STATUS (1 << 28)207#define SOR_SEQ_SWITCH (1 << 30)208 209#define HDMI_NV_PDISP_SOR_SEQ_INST(x) (0x60 + (x))210 211#define SOR_SEQ_INST_WAIT_TIME(x) (((x) & 0x3ff) << 0)212#define SOR_SEQ_INST_WAIT_UNITS_VSYNC (2 << 12)213#define SOR_SEQ_INST_HALT (1 << 15)214#define SOR_SEQ_INST_PIN_A_LOW (0 << 21)215#define SOR_SEQ_INST_PIN_A_HIGH (1 << 21)216#define SOR_SEQ_INST_PIN_B_LOW (0 << 22)217#define SOR_SEQ_INST_PIN_B_HIGH (1 << 22)218#define SOR_SEQ_INST_DRIVE_PWM_OUT_LO (1 << 23)219 220#define HDMI_NV_PDISP_SOR_VCRCA0 0x72221#define HDMI_NV_PDISP_SOR_VCRCA1 0x73222#define HDMI_NV_PDISP_SOR_CCRCA0 0x74223#define HDMI_NV_PDISP_SOR_CCRCA1 0x75224#define HDMI_NV_PDISP_SOR_EDATAA0 0x76225#define HDMI_NV_PDISP_SOR_EDATAA1 0x77226#define HDMI_NV_PDISP_SOR_COUNTA0 0x78227#define HDMI_NV_PDISP_SOR_COUNTA1 0x79228#define HDMI_NV_PDISP_SOR_DEBUGA0 0x7a229#define HDMI_NV_PDISP_SOR_DEBUGA1 0x7b230#define HDMI_NV_PDISP_SOR_TRIG 0x7c231#define HDMI_NV_PDISP_SOR_MSCHECK 0x7d232 233#define HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT 0x7e234#define DRIVE_CURRENT_LANE0(x) (((x) & 0x3f) << 0)235#define DRIVE_CURRENT_LANE1(x) (((x) & 0x3f) << 8)236#define DRIVE_CURRENT_LANE2(x) (((x) & 0x3f) << 16)237#define DRIVE_CURRENT_LANE3(x) (((x) & 0x3f) << 24)238#define DRIVE_CURRENT_LANE0_T114(x) (((x) & 0x7f) << 0)239#define DRIVE_CURRENT_LANE1_T114(x) (((x) & 0x7f) << 8)240#define DRIVE_CURRENT_LANE2_T114(x) (((x) & 0x7f) << 16)241#define DRIVE_CURRENT_LANE3_T114(x) (((x) & 0x7f) << 24)242 243#define DRIVE_CURRENT_1_500_mA 0x00244#define DRIVE_CURRENT_1_875_mA 0x01245#define DRIVE_CURRENT_2_250_mA 0x02246#define DRIVE_CURRENT_2_625_mA 0x03247#define DRIVE_CURRENT_3_000_mA 0x04248#define DRIVE_CURRENT_3_375_mA 0x05249#define DRIVE_CURRENT_3_750_mA 0x06250#define DRIVE_CURRENT_4_125_mA 0x07251#define DRIVE_CURRENT_4_500_mA 0x08252#define DRIVE_CURRENT_4_875_mA 0x09253#define DRIVE_CURRENT_5_250_mA 0x0a254#define DRIVE_CURRENT_5_625_mA 0x0b255#define DRIVE_CURRENT_6_000_mA 0x0c256#define DRIVE_CURRENT_6_375_mA 0x0d257#define DRIVE_CURRENT_6_750_mA 0x0e258#define DRIVE_CURRENT_7_125_mA 0x0f259#define DRIVE_CURRENT_7_500_mA 0x10260#define DRIVE_CURRENT_7_875_mA 0x11261#define DRIVE_CURRENT_8_250_mA 0x12262#define DRIVE_CURRENT_8_625_mA 0x13263#define DRIVE_CURRENT_9_000_mA 0x14264#define DRIVE_CURRENT_9_375_mA 0x15265#define DRIVE_CURRENT_9_750_mA 0x16266#define DRIVE_CURRENT_10_125_mA 0x17267#define DRIVE_CURRENT_10_500_mA 0x18268#define DRIVE_CURRENT_10_875_mA 0x19269#define DRIVE_CURRENT_11_250_mA 0x1a270#define DRIVE_CURRENT_11_625_mA 0x1b271#define DRIVE_CURRENT_12_000_mA 0x1c272#define DRIVE_CURRENT_12_375_mA 0x1d273#define DRIVE_CURRENT_12_750_mA 0x1e274#define DRIVE_CURRENT_13_125_mA 0x1f275#define DRIVE_CURRENT_13_500_mA 0x20276#define DRIVE_CURRENT_13_875_mA 0x21277#define DRIVE_CURRENT_14_250_mA 0x22278#define DRIVE_CURRENT_14_625_mA 0x23279#define DRIVE_CURRENT_15_000_mA 0x24280#define DRIVE_CURRENT_15_375_mA 0x25281#define DRIVE_CURRENT_15_750_mA 0x26282#define DRIVE_CURRENT_16_125_mA 0x27283#define DRIVE_CURRENT_16_500_mA 0x28284#define DRIVE_CURRENT_16_875_mA 0x29285#define DRIVE_CURRENT_17_250_mA 0x2a286#define DRIVE_CURRENT_17_625_mA 0x2b287#define DRIVE_CURRENT_18_000_mA 0x2c288#define DRIVE_CURRENT_18_375_mA 0x2d289#define DRIVE_CURRENT_18_750_mA 0x2e290#define DRIVE_CURRENT_19_125_mA 0x2f291#define DRIVE_CURRENT_19_500_mA 0x30292#define DRIVE_CURRENT_19_875_mA 0x31293#define DRIVE_CURRENT_20_250_mA 0x32294#define DRIVE_CURRENT_20_625_mA 0x33295#define DRIVE_CURRENT_21_000_mA 0x34296#define DRIVE_CURRENT_21_375_mA 0x35297#define DRIVE_CURRENT_21_750_mA 0x36298#define DRIVE_CURRENT_22_125_mA 0x37299#define DRIVE_CURRENT_22_500_mA 0x38300#define DRIVE_CURRENT_22_875_mA 0x39301#define DRIVE_CURRENT_23_250_mA 0x3a302#define DRIVE_CURRENT_23_625_mA 0x3b303#define DRIVE_CURRENT_24_000_mA 0x3c304#define DRIVE_CURRENT_24_375_mA 0x3d305#define DRIVE_CURRENT_24_750_mA 0x3e306 307#define DRIVE_CURRENT_0_000_mA_T114 0x00308#define DRIVE_CURRENT_0_400_mA_T114 0x01309#define DRIVE_CURRENT_0_800_mA_T114 0x02310#define DRIVE_CURRENT_1_200_mA_T114 0x03311#define DRIVE_CURRENT_1_600_mA_T114 0x04312#define DRIVE_CURRENT_2_000_mA_T114 0x05313#define DRIVE_CURRENT_2_400_mA_T114 0x06314#define DRIVE_CURRENT_2_800_mA_T114 0x07315#define DRIVE_CURRENT_3_200_mA_T114 0x08316#define DRIVE_CURRENT_3_600_mA_T114 0x09317#define DRIVE_CURRENT_4_000_mA_T114 0x0a318#define DRIVE_CURRENT_4_400_mA_T114 0x0b319#define DRIVE_CURRENT_4_800_mA_T114 0x0c320#define DRIVE_CURRENT_5_200_mA_T114 0x0d321#define DRIVE_CURRENT_5_600_mA_T114 0x0e322#define DRIVE_CURRENT_6_000_mA_T114 0x0f323#define DRIVE_CURRENT_6_400_mA_T114 0x10324#define DRIVE_CURRENT_6_800_mA_T114 0x11325#define DRIVE_CURRENT_7_200_mA_T114 0x12326#define DRIVE_CURRENT_7_600_mA_T114 0x13327#define DRIVE_CURRENT_8_000_mA_T114 0x14328#define DRIVE_CURRENT_8_400_mA_T114 0x15329#define DRIVE_CURRENT_8_800_mA_T114 0x16330#define DRIVE_CURRENT_9_200_mA_T114 0x17331#define DRIVE_CURRENT_9_600_mA_T114 0x18332#define DRIVE_CURRENT_10_000_mA_T114 0x19333#define DRIVE_CURRENT_10_400_mA_T114 0x1a334#define DRIVE_CURRENT_10_800_mA_T114 0x1b335#define DRIVE_CURRENT_11_200_mA_T114 0x1c336#define DRIVE_CURRENT_11_600_mA_T114 0x1d337#define DRIVE_CURRENT_12_000_mA_T114 0x1e338#define DRIVE_CURRENT_12_400_mA_T114 0x1f339#define DRIVE_CURRENT_12_800_mA_T114 0x20340#define DRIVE_CURRENT_13_200_mA_T114 0x21341#define DRIVE_CURRENT_13_600_mA_T114 0x22342#define DRIVE_CURRENT_14_000_mA_T114 0x23343#define DRIVE_CURRENT_14_400_mA_T114 0x24344#define DRIVE_CURRENT_14_800_mA_T114 0x25345#define DRIVE_CURRENT_15_200_mA_T114 0x26346#define DRIVE_CURRENT_15_600_mA_T114 0x27347#define DRIVE_CURRENT_16_000_mA_T114 0x28348#define DRIVE_CURRENT_16_400_mA_T114 0x29349#define DRIVE_CURRENT_16_800_mA_T114 0x2a350#define DRIVE_CURRENT_17_200_mA_T114 0x2b351#define DRIVE_CURRENT_17_600_mA_T114 0x2c352#define DRIVE_CURRENT_18_000_mA_T114 0x2d353#define DRIVE_CURRENT_18_400_mA_T114 0x2e354#define DRIVE_CURRENT_18_800_mA_T114 0x2f355#define DRIVE_CURRENT_19_200_mA_T114 0x30356#define DRIVE_CURRENT_19_600_mA_T114 0x31357#define DRIVE_CURRENT_20_000_mA_T114 0x32358#define DRIVE_CURRENT_20_400_mA_T114 0x33359#define DRIVE_CURRENT_20_800_mA_T114 0x34360#define DRIVE_CURRENT_21_200_mA_T114 0x35361#define DRIVE_CURRENT_21_600_mA_T114 0x36362#define DRIVE_CURRENT_22_000_mA_T114 0x37363#define DRIVE_CURRENT_22_400_mA_T114 0x38364#define DRIVE_CURRENT_22_800_mA_T114 0x39365#define DRIVE_CURRENT_23_200_mA_T114 0x3a366#define DRIVE_CURRENT_23_600_mA_T114 0x3b367#define DRIVE_CURRENT_24_000_mA_T114 0x3c368#define DRIVE_CURRENT_24_400_mA_T114 0x3d369#define DRIVE_CURRENT_24_800_mA_T114 0x3e370#define DRIVE_CURRENT_25_200_mA_T114 0x3f371#define DRIVE_CURRENT_25_400_mA_T114 0x40372#define DRIVE_CURRENT_25_800_mA_T114 0x41373#define DRIVE_CURRENT_26_200_mA_T114 0x42374#define DRIVE_CURRENT_26_600_mA_T114 0x43375#define DRIVE_CURRENT_27_000_mA_T114 0x44376#define DRIVE_CURRENT_27_400_mA_T114 0x45377#define DRIVE_CURRENT_27_800_mA_T114 0x46378#define DRIVE_CURRENT_28_200_mA_T114 0x47379 380#define HDMI_NV_PDISP_AUDIO_DEBUG0 0x7f381#define HDMI_NV_PDISP_AUDIO_DEBUG1 0x80382#define HDMI_NV_PDISP_AUDIO_DEBUG2 0x81383 384#define HDMI_NV_PDISP_AUDIO_FS(x) (0x82 + (x))385#define AUDIO_FS_LOW(x) (((x) & 0xfff) << 0)386#define AUDIO_FS_HIGH(x) (((x) & 0xfff) << 16)387 388#define HDMI_NV_PDISP_AUDIO_PULSE_WIDTH 0x89389#define HDMI_NV_PDISP_AUDIO_THRESHOLD 0x8a390#define HDMI_NV_PDISP_AUDIO_CNTRL0 0x8b391#define AUDIO_CNTRL0_ERROR_TOLERANCE(x) (((x) & 0xff) << 0)392#define AUDIO_CNTRL0_SOURCE_SELECT_AUTO (0 << 20)393#define AUDIO_CNTRL0_SOURCE_SELECT_SPDIF (1 << 20)394#define AUDIO_CNTRL0_SOURCE_SELECT_HDAL (2 << 20)395#define AUDIO_CNTRL0_FRAMES_PER_BLOCK(x) (((x) & 0xff) << 24)396 397#define HDMI_NV_PDISP_AUDIO_N 0x8c398#define AUDIO_N_VALUE(x) (((x) & 0xfffff) << 0)399#define AUDIO_N_RESETF (1 << 20)400#define AUDIO_N_GENERATE_NORMAL (0 << 24)401#define AUDIO_N_GENERATE_ALTERNATE (1 << 24)402 403#define HDMI_NV_PDISP_HDCPRIF_ROM_TIMING 0x94404#define HDMI_NV_PDISP_SOR_REFCLK 0x95405#define SOR_REFCLK_DIV_INT(x) (((x) & 0xff) << 8)406#define SOR_REFCLK_DIV_FRAC(x) (((x) & 0x03) << 6)407 408#define HDMI_NV_PDISP_CRC_CONTROL 0x96409#define HDMI_NV_PDISP_INPUT_CONTROL 0x97410#define HDMI_SRC_DISPLAYA (0 << 0)411#define HDMI_SRC_DISPLAYB (1 << 0)412#define ARM_VIDEO_RANGE_FULL (0 << 1)413#define ARM_VIDEO_RANGE_LIMITED (1 << 1)414 415#define HDMI_NV_PDISP_SCRATCH 0x98416#define HDMI_NV_PDISP_PE_CURRENT 0x99417#define PE_CURRENT0(x) (((x) & 0xf) << 0)418#define PE_CURRENT1(x) (((x) & 0xf) << 8)419#define PE_CURRENT2(x) (((x) & 0xf) << 16)420#define PE_CURRENT3(x) (((x) & 0xf) << 24)421 422#define PE_CURRENT_0_0_mA 0x0423#define PE_CURRENT_0_5_mA 0x1424#define PE_CURRENT_1_0_mA 0x2425#define PE_CURRENT_1_5_mA 0x3426#define PE_CURRENT_2_0_mA 0x4427#define PE_CURRENT_2_5_mA 0x5428#define PE_CURRENT_3_0_mA 0x6429#define PE_CURRENT_3_5_mA 0x7430#define PE_CURRENT_4_0_mA 0x8431#define PE_CURRENT_4_5_mA 0x9432#define PE_CURRENT_5_0_mA 0xa433#define PE_CURRENT_5_5_mA 0xb434#define PE_CURRENT_6_0_mA 0xc435#define PE_CURRENT_6_5_mA 0xd436#define PE_CURRENT_7_0_mA 0xe437#define PE_CURRENT_7_5_mA 0xf438 439#define PE_CURRENT_0_mA_T114 0x0440#define PE_CURRENT_1_mA_T114 0x1441#define PE_CURRENT_2_mA_T114 0x2442#define PE_CURRENT_3_mA_T114 0x3443#define PE_CURRENT_4_mA_T114 0x4444#define PE_CURRENT_5_mA_T114 0x5445#define PE_CURRENT_6_mA_T114 0x6446#define PE_CURRENT_7_mA_T114 0x7447#define PE_CURRENT_8_mA_T114 0x8448#define PE_CURRENT_9_mA_T114 0x9449#define PE_CURRENT_10_mA_T114 0xa450#define PE_CURRENT_11_mA_T114 0xb451#define PE_CURRENT_12_mA_T114 0xc452#define PE_CURRENT_13_mA_T114 0xd453#define PE_CURRENT_14_mA_T114 0xe454#define PE_CURRENT_15_mA_T114 0xf455 456#define HDMI_NV_PDISP_KEY_CTRL 0x9a457#define HDMI_NV_PDISP_KEY_DEBUG0 0x9b458#define HDMI_NV_PDISP_KEY_DEBUG1 0x9c459#define HDMI_NV_PDISP_KEY_DEBUG2 0x9d460#define HDMI_NV_PDISP_KEY_HDCP_KEY_0 0x9e461#define HDMI_NV_PDISP_KEY_HDCP_KEY_1 0x9f462#define HDMI_NV_PDISP_KEY_HDCP_KEY_2 0xa0463#define HDMI_NV_PDISP_KEY_HDCP_KEY_3 0xa1464#define HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG 0xa2465#define HDMI_NV_PDISP_KEY_SKEY_INDEX 0xa3466 467#define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0 0xac468#define SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO (0 << 20)469#define SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF (1 << 20)470#define SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL (2 << 20)471#define SOR_AUDIO_CNTRL0_INJECT_NULLSMPL (1 << 29)472#define HDMI_NV_PDISP_SOR_AUDIO_SPARE0 0xae473#define SOR_AUDIO_SPARE0_HBR_ENABLE (1 << 27)474#define HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0 0xba475#define SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID (1 << 30)476#define SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK 0xffff477#define HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1 0xbb478#define HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR 0xbc479#define HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE 0xbd480#define SOR_AUDIO_HDA_PRESENSE_VALID (1 << 1)481#define SOR_AUDIO_HDA_PRESENSE_PRESENT (1 << 0)482 483#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 0xbf484#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 0xc0485#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 0xc1486#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 0xc2487#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 0xc3488#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 0xc4489#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 0xc5490#define HDMI_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT 0xc5491 492#define HDMI_NV_PDISP_INT_STATUS 0xcc493#define INT_SCRATCH (1 << 3)494#define INT_CP_REQUEST (1 << 2)495#define INT_CODEC_SCRATCH1 (1 << 1)496#define INT_CODEC_SCRATCH0 (1 << 0)497#define HDMI_NV_PDISP_INT_MASK 0xcd498#define HDMI_NV_PDISP_INT_ENABLE 0xce499 500#define HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT 0xd1501#define PEAK_CURRENT_LANE0(x) (((x) & 0x7f) << 0)502#define PEAK_CURRENT_LANE1(x) (((x) & 0x7f) << 8)503#define PEAK_CURRENT_LANE2(x) (((x) & 0x7f) << 16)504#define PEAK_CURRENT_LANE3(x) (((x) & 0x7f) << 24)505 506#define PEAK_CURRENT_0_000_mA 0x00507#define PEAK_CURRENT_0_200_mA 0x01508#define PEAK_CURRENT_0_400_mA 0x02509#define PEAK_CURRENT_0_600_mA 0x03510#define PEAK_CURRENT_0_800_mA 0x04511#define PEAK_CURRENT_1_000_mA 0x05512#define PEAK_CURRENT_1_200_mA 0x06513#define PEAK_CURRENT_1_400_mA 0x07514#define PEAK_CURRENT_1_600_mA 0x08515#define PEAK_CURRENT_1_800_mA 0x09516#define PEAK_CURRENT_2_000_mA 0x0a517#define PEAK_CURRENT_2_200_mA 0x0b518#define PEAK_CURRENT_2_400_mA 0x0c519#define PEAK_CURRENT_2_600_mA 0x0d520#define PEAK_CURRENT_2_800_mA 0x0e521#define PEAK_CURRENT_3_000_mA 0x0f522#define PEAK_CURRENT_3_200_mA 0x10523#define PEAK_CURRENT_3_400_mA 0x11524#define PEAK_CURRENT_3_600_mA 0x12525#define PEAK_CURRENT_3_800_mA 0x13526#define PEAK_CURRENT_4_000_mA 0x14527#define PEAK_CURRENT_4_200_mA 0x15528#define PEAK_CURRENT_4_400_mA 0x16529#define PEAK_CURRENT_4_600_mA 0x17530#define PEAK_CURRENT_4_800_mA 0x18531#define PEAK_CURRENT_5_000_mA 0x19532#define PEAK_CURRENT_5_200_mA 0x1a533#define PEAK_CURRENT_5_400_mA 0x1b534#define PEAK_CURRENT_5_600_mA 0x1c535#define PEAK_CURRENT_5_800_mA 0x1d536#define PEAK_CURRENT_6_000_mA 0x1e537#define PEAK_CURRENT_6_200_mA 0x1f538#define PEAK_CURRENT_6_400_mA 0x20539#define PEAK_CURRENT_6_600_mA 0x21540#define PEAK_CURRENT_6_800_mA 0x22541#define PEAK_CURRENT_7_000_mA 0x23542#define PEAK_CURRENT_7_200_mA 0x24543#define PEAK_CURRENT_7_400_mA 0x25544#define PEAK_CURRENT_7_600_mA 0x26545#define PEAK_CURRENT_7_800_mA 0x27546#define PEAK_CURRENT_8_000_mA 0x28547#define PEAK_CURRENT_8_200_mA 0x29548#define PEAK_CURRENT_8_400_mA 0x2a549#define PEAK_CURRENT_8_600_mA 0x2b550#define PEAK_CURRENT_8_800_mA 0x2c551#define PEAK_CURRENT_9_000_mA 0x2d552#define PEAK_CURRENT_9_200_mA 0x2e553#define PEAK_CURRENT_9_400_mA 0x2f554 555#define HDMI_NV_PDISP_SOR_PAD_CTLS0 0xd2556 557#endif /* TEGRA_HDMI_H */558