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1/* SPDX-License-Identifier: GPL-2.0-only */2 3#ifndef UDL_PROTO_H4#define UDL_PROTO_H5 6#include <linux/bits.h>7 8#define UDL_MSG_BULK 0xaf9 10/* Register access */11#define UDL_CMD_WRITEREG 0x20 /* See register constants below */12 13/* Framebuffer access */14#define UDL_CMD_WRITERAW8 0x60 /* 8 bit raw write command. */15#define UDL_CMD_WRITERL8 0x61 /* 8 bit run length command. */16#define UDL_CMD_WRITECOPY8 0x62 /* 8 bit copy command. */17#define UDL_CMD_WRITERLX8 0x63 /* 8 bit extended run length command. */18#define UDL_CMD_WRITERAW16 0x68 /* 16 bit raw write command. */19#define UDL_CMD_WRITERL16 0x69 /* 16 bit run length command. */20#define UDL_CMD_WRITECOPY16 0x6a /* 16 bit copy command. */21#define UDL_CMD_WRITERLX16 0x6b /* 16 bit extended run length command. */22 23/* Color depth */24#define UDL_REG_COLORDEPTH 0x0025#define UDL_COLORDEPTH_16BPP 026#define UDL_COLORDEPTH_24BPP 127 28/* Display-mode settings */29#define UDL_REG_XDISPLAYSTART 0x0130#define UDL_REG_XDISPLAYEND 0x0331#define UDL_REG_YDISPLAYSTART 0x0532#define UDL_REG_YDISPLAYEND 0x0733#define UDL_REG_XENDCOUNT 0x0934#define UDL_REG_HSYNCSTART 0x0b35#define UDL_REG_HSYNCEND 0x0d36#define UDL_REG_HPIXELS 0x0f37#define UDL_REG_YENDCOUNT 0x1138#define UDL_REG_VSYNCSTART 0x1339#define UDL_REG_VSYNCEND 0x1540#define UDL_REG_VPIXELS 0x1741#define UDL_REG_PIXELCLOCK5KHZ 0x1b42 43/* On/Off for driving the DisplayLink framebuffer to the display */44#define UDL_REG_BLANKMODE 0x1f45#define UDL_BLANKMODE_ON 0x00 /* hsync and vsync on, visible */46#define UDL_BLANKMODE_BLANKED 0x01 /* hsync and vsync on, blanked */47#define UDL_BLANKMODE_VSYNC_OFF 0x03 /* vsync off, blanked */48#define UDL_BLANKMODE_HSYNC_OFF 0x05 /* hsync off, blanked */49#define UDL_BLANKMODE_POWERDOWN 0x07 /* powered off; requires modeset */50 51/* Framebuffer address */52#define UDL_REG_BASE16BPP_ADDR2 0x2053#define UDL_REG_BASE16BPP_ADDR1 0x2154#define UDL_REG_BASE16BPP_ADDR0 0x2255#define UDL_REG_BASE8BPP_ADDR2 0x2656#define UDL_REG_BASE8BPP_ADDR1 0x2757#define UDL_REG_BASE8BPP_ADDR0 0x2858 59#define UDL_BASE_ADDR0_MASK GENMASK(7, 0)60#define UDL_BASE_ADDR1_MASK GENMASK(15, 8)61#define UDL_BASE_ADDR2_MASK GENMASK(23, 16)62 63/* Lock/unlock video registers */64#define UDL_REG_VIDREG 0xff65#define UDL_VIDREG_LOCK 0x0066#define UDL_VIDREG_UNLOCK 0xff67 68#endif69