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1// SPDX-License-Identifier: GPL-2.0+2/* Copyright (C) 2014-2018 Broadcom */3 4/**5 * DOC: Broadcom V3D Graphics Driver6 *7 * This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs.8 * For V3D 2.x support, see the VC4 driver.9 *10 * The V3D GPU includes a tiled render (composed of a bin and render11 * pipelines), the TFU (texture formatting unit), and the CSD (compute12 * shader dispatch).13 */14 15#include <linux/clk.h>16#include <linux/device.h>17#include <linux/dma-mapping.h>18#include <linux/io.h>19#include <linux/module.h>20#include <linux/of_platform.h>21#include <linux/platform_device.h>22#include <linux/sched/clock.h>23#include <linux/reset.h>24 25#include <drm/drm_drv.h>26#include <drm/drm_managed.h>27#include <uapi/drm/v3d_drm.h>28 29#include "v3d_drv.h"30#include "v3d_regs.h"31 32#define DRIVER_NAME "v3d"33#define DRIVER_DESC "Broadcom V3D graphics"34#define DRIVER_DATE "20180419"35#define DRIVER_MAJOR 136#define DRIVER_MINOR 037#define DRIVER_PATCHLEVEL 038 39static int v3d_get_param_ioctl(struct drm_device *dev, void *data,40 struct drm_file *file_priv)41{42 struct v3d_dev *v3d = to_v3d_dev(dev);43 struct drm_v3d_get_param *args = data;44 static const u32 reg_map[] = {45 [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG,46 [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1,47 [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2,48 [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3,49 [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0,50 [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1,51 [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2,52 };53 54 if (args->pad != 0)55 return -EINVAL;56 57 /* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need58 * to explicitly allow it in the "the register in our59 * parameter map" check.60 */61 if (args->param < ARRAY_SIZE(reg_map) &&62 (reg_map[args->param] ||63 args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) {64 u32 offset = reg_map[args->param];65 66 if (args->value != 0)67 return -EINVAL;68 69 if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 &&70 args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) {71 args->value = V3D_CORE_READ(0, offset);72 } else {73 args->value = V3D_READ(offset);74 }75 return 0;76 }77 78 switch (args->param) {79 case DRM_V3D_PARAM_SUPPORTS_TFU:80 args->value = 1;81 return 0;82 case DRM_V3D_PARAM_SUPPORTS_CSD:83 args->value = v3d_has_csd(v3d);84 return 0;85 case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH:86 args->value = 1;87 return 0;88 case DRM_V3D_PARAM_SUPPORTS_PERFMON:89 args->value = (v3d->ver >= 40);90 return 0;91 case DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT:92 args->value = 1;93 return 0;94 case DRM_V3D_PARAM_SUPPORTS_CPU_QUEUE:95 args->value = 1;96 return 0;97 case DRM_V3D_PARAM_MAX_PERF_COUNTERS:98 args->value = v3d->perfmon_info.max_counters;99 return 0;100 default:101 DRM_DEBUG("Unknown parameter %d\n", args->param);102 return -EINVAL;103 }104}105 106static int107v3d_open(struct drm_device *dev, struct drm_file *file)108{109 struct v3d_dev *v3d = to_v3d_dev(dev);110 struct v3d_file_priv *v3d_priv;111 struct drm_gpu_scheduler *sched;112 int i;113 114 v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL);115 if (!v3d_priv)116 return -ENOMEM;117 118 v3d_priv->v3d = v3d;119 120 for (i = 0; i < V3D_MAX_QUEUES; i++) {121 sched = &v3d->queue[i].sched;122 drm_sched_entity_init(&v3d_priv->sched_entity[i],123 DRM_SCHED_PRIORITY_NORMAL, &sched,124 1, NULL);125 126 memset(&v3d_priv->stats[i], 0, sizeof(v3d_priv->stats[i]));127 seqcount_init(&v3d_priv->stats[i].lock);128 }129 130 v3d_perfmon_open_file(v3d_priv);131 file->driver_priv = v3d_priv;132 133 return 0;134}135 136static void137v3d_postclose(struct drm_device *dev, struct drm_file *file)138{139 struct v3d_file_priv *v3d_priv = file->driver_priv;140 enum v3d_queue q;141 142 for (q = 0; q < V3D_MAX_QUEUES; q++)143 drm_sched_entity_destroy(&v3d_priv->sched_entity[q]);144 145 v3d_perfmon_close_file(v3d_priv);146 kfree(v3d_priv);147}148 149void v3d_get_stats(const struct v3d_stats *stats, u64 timestamp,150 u64 *active_runtime, u64 *jobs_completed)151{152 unsigned int seq;153 154 do {155 seq = read_seqcount_begin(&stats->lock);156 *active_runtime = stats->enabled_ns;157 if (stats->start_ns)158 *active_runtime += timestamp - stats->start_ns;159 *jobs_completed = stats->jobs_completed;160 } while (read_seqcount_retry(&stats->lock, seq));161}162 163static void v3d_show_fdinfo(struct drm_printer *p, struct drm_file *file)164{165 struct v3d_file_priv *file_priv = file->driver_priv;166 u64 timestamp = local_clock();167 enum v3d_queue queue;168 169 for (queue = 0; queue < V3D_MAX_QUEUES; queue++) {170 struct v3d_stats *stats = &file_priv->stats[queue];171 u64 active_runtime, jobs_completed;172 173 v3d_get_stats(stats, timestamp, &active_runtime, &jobs_completed);174 175 /* Note that, in case of a GPU reset, the time spent during an176 * attempt of executing the job is not computed in the runtime.177 */178 drm_printf(p, "drm-engine-%s: \t%llu ns\n",179 v3d_queue_to_string(queue), active_runtime);180 181 /* Note that we only count jobs that completed. Therefore, jobs182 * that were resubmitted due to a GPU reset are not computed.183 */184 drm_printf(p, "v3d-jobs-%s: \t%llu jobs\n",185 v3d_queue_to_string(queue), jobs_completed);186 }187 188 drm_show_memory_stats(p, file);189}190 191static const struct file_operations v3d_drm_fops = {192 .owner = THIS_MODULE,193 DRM_GEM_FOPS,194 .show_fdinfo = drm_show_fdinfo,195};196 197/* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP198 * protection between clients. Note that render nodes would be199 * able to submit CLs that could access BOs from clients authenticated200 * with the master node. The TFU doesn't use the GMP, so it would201 * need to stay DRM_AUTH until we do buffer size/offset validation.202 */203static const struct drm_ioctl_desc v3d_drm_ioctls[] = {204 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),205 DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW),206 DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW),207 DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW),208 DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW),209 DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW),210 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),211 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CSD, v3d_submit_csd_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),212 DRM_IOCTL_DEF_DRV(V3D_PERFMON_CREATE, v3d_perfmon_create_ioctl, DRM_RENDER_ALLOW),213 DRM_IOCTL_DEF_DRV(V3D_PERFMON_DESTROY, v3d_perfmon_destroy_ioctl, DRM_RENDER_ALLOW),214 DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_VALUES, v3d_perfmon_get_values_ioctl, DRM_RENDER_ALLOW),215 DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CPU, v3d_submit_cpu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),216 DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_COUNTER, v3d_perfmon_get_counter_ioctl, DRM_RENDER_ALLOW),217};218 219static const struct drm_driver v3d_drm_driver = {220 .driver_features = (DRIVER_GEM |221 DRIVER_RENDER |222 DRIVER_SYNCOBJ),223 224 .open = v3d_open,225 .postclose = v3d_postclose,226 227#if defined(CONFIG_DEBUG_FS)228 .debugfs_init = v3d_debugfs_init,229#endif230 231 .gem_create_object = v3d_create_object,232 .gem_prime_import_sg_table = v3d_prime_import_sg_table,233 234 .ioctls = v3d_drm_ioctls,235 .num_ioctls = ARRAY_SIZE(v3d_drm_ioctls),236 .fops = &v3d_drm_fops,237 .show_fdinfo = v3d_show_fdinfo,238 239 .name = DRIVER_NAME,240 .desc = DRIVER_DESC,241 .date = DRIVER_DATE,242 .major = DRIVER_MAJOR,243 .minor = DRIVER_MINOR,244 .patchlevel = DRIVER_PATCHLEVEL,245};246 247static const struct of_device_id v3d_of_match[] = {248 { .compatible = "brcm,2711-v3d" },249 { .compatible = "brcm,2712-v3d" },250 { .compatible = "brcm,7268-v3d" },251 { .compatible = "brcm,7278-v3d" },252 {},253};254MODULE_DEVICE_TABLE(of, v3d_of_match);255 256static int257map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name)258{259 *regs = devm_platform_ioremap_resource_byname(v3d_to_pdev(v3d), name);260 return PTR_ERR_OR_ZERO(*regs);261}262 263static int v3d_platform_drm_probe(struct platform_device *pdev)264{265 struct device *dev = &pdev->dev;266 struct drm_device *drm;267 struct v3d_dev *v3d;268 int ret;269 u32 mmu_debug;270 u32 ident1, ident3;271 u64 mask;272 273 v3d = devm_drm_dev_alloc(dev, &v3d_drm_driver, struct v3d_dev, drm);274 if (IS_ERR(v3d))275 return PTR_ERR(v3d);276 277 drm = &v3d->drm;278 279 platform_set_drvdata(pdev, drm);280 281 ret = map_regs(v3d, &v3d->hub_regs, "hub");282 if (ret)283 return ret;284 285 ret = map_regs(v3d, &v3d->core_regs[0], "core0");286 if (ret)287 return ret;288 289 mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO);290 mask = DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH));291 ret = dma_set_mask_and_coherent(dev, mask);292 if (ret)293 return ret;294 295 v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH);296 297 ident1 = V3D_READ(V3D_HUB_IDENT1);298 v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 +299 V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV));300 v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES);301 WARN_ON(v3d->cores > 1); /* multicore not yet implemented */302 303 ident3 = V3D_READ(V3D_HUB_IDENT3);304 v3d->rev = V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPREV);305 306 v3d_perfmon_init(v3d);307 308 v3d->reset = devm_reset_control_get_exclusive(dev, NULL);309 if (IS_ERR(v3d->reset)) {310 ret = PTR_ERR(v3d->reset);311 312 if (ret == -EPROBE_DEFER)313 return ret;314 315 v3d->reset = NULL;316 ret = map_regs(v3d, &v3d->bridge_regs, "bridge");317 if (ret) {318 dev_err(dev,319 "Failed to get reset control or bridge regs\n");320 return ret;321 }322 }323 324 if (v3d->ver < 41) {325 ret = map_regs(v3d, &v3d->gca_regs, "gca");326 if (ret)327 return ret;328 }329 330 v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr,331 GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO);332 if (!v3d->mmu_scratch) {333 dev_err(dev, "Failed to allocate MMU scratch page\n");334 return -ENOMEM;335 }336 337 ret = v3d_gem_init(drm);338 if (ret)339 goto dma_free;340 341 ret = v3d_irq_init(v3d);342 if (ret)343 goto gem_destroy;344 345 ret = drm_dev_register(drm, 0);346 if (ret)347 goto irq_disable;348 349 ret = v3d_sysfs_init(dev);350 if (ret)351 goto drm_unregister;352 353 return 0;354 355drm_unregister:356 drm_dev_unregister(drm);357irq_disable:358 v3d_irq_disable(v3d);359gem_destroy:360 v3d_gem_destroy(drm);361dma_free:362 dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr);363 return ret;364}365 366static void v3d_platform_drm_remove(struct platform_device *pdev)367{368 struct drm_device *drm = platform_get_drvdata(pdev);369 struct v3d_dev *v3d = to_v3d_dev(drm);370 struct device *dev = &pdev->dev;371 372 v3d_sysfs_destroy(dev);373 374 drm_dev_unregister(drm);375 376 v3d_gem_destroy(drm);377 378 dma_free_wc(v3d->drm.dev, 4096, v3d->mmu_scratch,379 v3d->mmu_scratch_paddr);380}381 382static struct platform_driver v3d_platform_driver = {383 .probe = v3d_platform_drm_probe,384 .remove_new = v3d_platform_drm_remove,385 .driver = {386 .name = "v3d",387 .of_match_table = v3d_of_match,388 },389};390 391module_platform_driver(v3d_platform_driver);392 393MODULE_ALIAS("platform:v3d-drm");394MODULE_DESCRIPTION("Broadcom V3D DRM Driver");395MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");396MODULE_LICENSE("GPL v2");397