1112 lines · c
1/* SPDX-License-Identifier: GPL-2.0-only */2/*3 * Copyright © 2014-2015 Broadcom4 */5 6#ifndef VC4_REGS_H7#define VC4_REGS_H8 9#include <linux/bitfield.h>10#include <linux/bitops.h>11 12#define VC4_MASK(high, low) ((u32)GENMASK(high, low))13/* Using the GNU statement expression extension */14#define VC4_SET_FIELD(value, field) \15 ({ \16 WARN_ON(!FIELD_FIT(field##_MASK, value)); \17 FIELD_PREP(field##_MASK, value); \18 })19 20#define VC4_GET_FIELD(word, field) FIELD_GET(field##_MASK, word)21 22#define V3D_IDENT0 0x0000023# define V3D_EXPECTED_IDENT0 \24 ((2 << 24) | \25 ('V' << 0) | \26 ('3' << 8) | \27 ('D' << 16))28 29#define V3D_IDENT1 0x0000430/* Multiples of 1kb */31# define V3D_IDENT1_VPM_SIZE_MASK VC4_MASK(31, 28)32# define V3D_IDENT1_VPM_SIZE_SHIFT 2833# define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16)34# define V3D_IDENT1_NSEM_SHIFT 1635# define V3D_IDENT1_TUPS_MASK VC4_MASK(15, 12)36# define V3D_IDENT1_TUPS_SHIFT 1237# define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8)38# define V3D_IDENT1_QUPS_SHIFT 839# define V3D_IDENT1_NSLC_MASK VC4_MASK(7, 4)40# define V3D_IDENT1_NSLC_SHIFT 441# define V3D_IDENT1_REV_MASK VC4_MASK(3, 0)42# define V3D_IDENT1_REV_SHIFT 043 44#define V3D_IDENT2 0x0000845#define V3D_SCRATCH 0x0001046#define V3D_L2CACTL 0x0002047# define V3D_L2CACTL_L2CCLR BIT(2)48# define V3D_L2CACTL_L2CDIS BIT(1)49# define V3D_L2CACTL_L2CENA BIT(0)50 51#define V3D_SLCACTL 0x0002452# define V3D_SLCACTL_T1CC_MASK VC4_MASK(27, 24)53# define V3D_SLCACTL_T1CC_SHIFT 2454# define V3D_SLCACTL_T0CC_MASK VC4_MASK(19, 16)55# define V3D_SLCACTL_T0CC_SHIFT 1656# define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8)57# define V3D_SLCACTL_UCC_SHIFT 858# define V3D_SLCACTL_ICC_MASK VC4_MASK(3, 0)59# define V3D_SLCACTL_ICC_SHIFT 060 61#define V3D_INTCTL 0x0003062#define V3D_INTENA 0x0003463#define V3D_INTDIS 0x0003864# define V3D_INT_SPILLUSE BIT(3)65# define V3D_INT_OUTOMEM BIT(2)66# define V3D_INT_FLDONE BIT(1)67# define V3D_INT_FRDONE BIT(0)68 69#define V3D_CT0CS 0x0010070#define V3D_CT1CS 0x0010471#define V3D_CTNCS(n) (V3D_CT0CS + 4 * n)72# define V3D_CTRSTA BIT(15)73# define V3D_CTSEMA BIT(12)74# define V3D_CTRTSD BIT(8)75# define V3D_CTRUN BIT(5)76# define V3D_CTSUBS BIT(4)77# define V3D_CTERR BIT(3)78# define V3D_CTMODE BIT(0)79 80#define V3D_CT0EA 0x0010881#define V3D_CT1EA 0x0010c82#define V3D_CTNEA(n) (V3D_CT0EA + 4 * (n))83#define V3D_CT0CA 0x0011084#define V3D_CT1CA 0x0011485#define V3D_CTNCA(n) (V3D_CT0CA + 4 * (n))86#define V3D_CT00RA0 0x0011887#define V3D_CT01RA0 0x0011c88#define V3D_CTNRA0(n) (V3D_CT00RA0 + 4 * (n))89#define V3D_CT0LC 0x0012090#define V3D_CT1LC 0x0012491#define V3D_CTNLC(n) (V3D_CT0LC + 4 * (n))92#define V3D_CT0PC 0x0012893#define V3D_CT1PC 0x0012c94#define V3D_CTNPC(n) (V3D_CT0PC + 4 * (n))95 96#define V3D_PCS 0x0013097# define V3D_BMOOM BIT(8)98# define V3D_RMBUSY BIT(3)99# define V3D_RMACTIVE BIT(2)100# define V3D_BMBUSY BIT(1)101# define V3D_BMACTIVE BIT(0)102 103#define V3D_BFC 0x00134104#define V3D_RFC 0x00138105#define V3D_BPCA 0x00300106#define V3D_BPCS 0x00304107#define V3D_BPOA 0x00308108#define V3D_BPOS 0x0030c109#define V3D_BXCF 0x00310110#define V3D_SQRSV0 0x00410111#define V3D_SQRSV1 0x00414112#define V3D_SQCNTL 0x00418113#define V3D_SRQPC 0x00430114#define V3D_SRQUA 0x00434115#define V3D_SRQUL 0x00438116#define V3D_SRQCS 0x0043c117#define V3D_VPACNTL 0x00500118#define V3D_VPMBASE 0x00504119#define V3D_PCTRC 0x00670120#define V3D_PCTRE 0x00674121# define V3D_PCTRE_EN BIT(31)122#define V3D_PCTR(x) (0x00680 + ((x) * 8))123#define V3D_PCTRS(x) (0x00684 + ((x) * 8))124#define V3D_DBGE 0x00f00125#define V3D_FDBGO 0x00f04126#define V3D_FDBGB 0x00f08127#define V3D_FDBGR 0x00f0c128#define V3D_FDBGS 0x00f10129#define V3D_ERRSTAT 0x00f20130 131#define PV_CONTROL 0x00132# define PV5_CONTROL_FIFO_LEVEL_HIGH_MASK VC4_MASK(26, 25)133# define PV5_CONTROL_FIFO_LEVEL_HIGH_SHIFT 25134# define PV_CONTROL_FORMAT_MASK VC4_MASK(23, 21)135# define PV_CONTROL_FORMAT_SHIFT 21136# define PV_CONTROL_FORMAT_24 0137# define PV_CONTROL_FORMAT_DSIV_16 1138# define PV_CONTROL_FORMAT_DSIC_16 2139# define PV_CONTROL_FORMAT_DSIV_18 3140# define PV_CONTROL_FORMAT_DSIV_24 4141 142# define PV_CONTROL_FIFO_LEVEL_MASK VC4_MASK(20, 15)143# define PV_CONTROL_FIFO_LEVEL_SHIFT 15144# define PV_CONTROL_CLR_AT_START BIT(14)145# define PV_CONTROL_TRIGGER_UNDERFLOW BIT(13)146# define PV_CONTROL_WAIT_HSTART BIT(12)147# define PV_CONTROL_PIXEL_REP_MASK VC4_MASK(5, 4)148# define PV_CONTROL_PIXEL_REP_SHIFT 4149# define PV_CONTROL_CLK_SELECT_DSI 0150# define PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI 1151# define PV_CONTROL_CLK_SELECT_VEC 2152# define PV_CONTROL_CLK_SELECT_MASK VC4_MASK(3, 2)153# define PV_CONTROL_CLK_SELECT_SHIFT 2154# define PV_CONTROL_FIFO_CLR BIT(1)155# define PV_CONTROL_EN BIT(0)156 157#define PV_V_CONTROL 0x04158# define PV_VCONTROL_ODD_DELAY_MASK VC4_MASK(22, 6)159# define PV_VCONTROL_ODD_DELAY_SHIFT 6160# define PV_VCONTROL_ODD_FIRST BIT(5)161# define PV_VCONTROL_INTERLACE BIT(4)162# define PV_VCONTROL_DSI BIT(3)163# define PV_VCONTROL_COMMAND BIT(2)164# define PV_VCONTROL_CONTINUOUS BIT(1)165# define PV_VCONTROL_VIDEN BIT(0)166 167#define PV_VSYNCD_EVEN 0x08168 169#define PV_HORZA 0x0c170# define PV_HORZA_HBP_MASK VC4_MASK(31, 16)171# define PV_HORZA_HBP_SHIFT 16172# define PV_HORZA_HSYNC_MASK VC4_MASK(15, 0)173# define PV_HORZA_HSYNC_SHIFT 0174 175#define PV_HORZB 0x10176# define PV_HORZB_HFP_MASK VC4_MASK(31, 16)177# define PV_HORZB_HFP_SHIFT 16178# define PV_HORZB_HACTIVE_MASK VC4_MASK(15, 0)179# define PV_HORZB_HACTIVE_SHIFT 0180 181#define PV_VERTA 0x14182# define PV_VERTA_VBP_MASK VC4_MASK(31, 16)183# define PV_VERTA_VBP_SHIFT 16184# define PV_VERTA_VSYNC_MASK VC4_MASK(15, 0)185# define PV_VERTA_VSYNC_SHIFT 0186 187#define PV_VERTB 0x18188# define PV_VERTB_VFP_MASK VC4_MASK(31, 16)189# define PV_VERTB_VFP_SHIFT 16190# define PV_VERTB_VACTIVE_MASK VC4_MASK(15, 0)191# define PV_VERTB_VACTIVE_SHIFT 0192 193#define PV_VERTA_EVEN 0x1c194#define PV_VERTB_EVEN 0x20195 196#define PV_INTEN 0x24197#define PV_INTSTAT 0x28198# define PV_INT_VID_IDLE BIT(9)199# define PV_INT_VFP_END BIT(8)200# define PV_INT_VFP_START BIT(7)201# define PV_INT_VACT_START BIT(6)202# define PV_INT_VBP_START BIT(5)203# define PV_INT_VSYNC_START BIT(4)204# define PV_INT_HFP_START BIT(3)205# define PV_INT_HACT_START BIT(2)206# define PV_INT_HBP_START BIT(1)207# define PV_INT_HSYNC_START BIT(0)208 209#define PV_STAT 0x2c210 211#define PV_HACT_ACT 0x30212 213#define PV_MUX_CFG 0x34214# define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_MASK VC4_MASK(5, 2)215# define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_SHIFT 2216# define PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP 8217 218#define SCALER_CHANNELS_COUNT 3219 220#define SCALER_DISPCTRL 0x00000000221/* Global register for clock gating the HVS */222# define SCALER_DISPCTRL_ENABLE BIT(31)223# define SCALER_DISPCTRL_PANIC0_MASK VC4_MASK(25, 24)224# define SCALER_DISPCTRL_PANIC0_SHIFT 24225# define SCALER_DISPCTRL_PANIC1_MASK VC4_MASK(27, 26)226# define SCALER_DISPCTRL_PANIC1_SHIFT 26227# define SCALER_DISPCTRL_PANIC2_MASK VC4_MASK(29, 28)228# define SCALER_DISPCTRL_PANIC2_SHIFT 28229# define SCALER_DISPCTRL_DSP3_MUX_MASK VC4_MASK(19, 18)230# define SCALER_DISPCTRL_DSP3_MUX_SHIFT 18231 232/* Enables Display 0 short line and underrun contribution to233 * SCALER_DISPSTAT_IRQDISP0. Note that short frame contributions are234 * always enabled.235 */236# define SCALER_DISPCTRL_DSPEISLUR(x) BIT(13 + (x))237# define SCALER5_DISPCTRL_DSPEISLUR(x) BIT(9 + ((x) * 4))238/* Enables Display 0 end-of-line-N contribution to239 * SCALER_DISPSTAT_IRQDISP0240 */241# define SCALER_DISPCTRL_DSPEIEOLN(x) BIT(8 + ((x) * 2))242# define SCALER5_DISPCTRL_DSPEIEOLN(x) BIT(8 + ((x) * 4))243/* Enables Display 0 EOF contribution to SCALER_DISPSTAT_IRQDISP0 */244# define SCALER_DISPCTRL_DSPEIEOF(x) BIT(7 + ((x) * 2))245# define SCALER5_DISPCTRL_DSPEIEOF(x) BIT(7 + ((x) * 4))246 247# define SCALER5_DISPCTRL_DSPEIVST(x) BIT(6 + ((x) * 4))248 249# define SCALER_DISPCTRL_SLVRDEIRQ BIT(6) /* HVS4 only */250# define SCALER_DISPCTRL_SLVWREIRQ BIT(5) /* HVS4 only */251# define SCALER5_DISPCTRL_SLVEIRQ BIT(5)252# define SCALER_DISPCTRL_DMAEIRQ BIT(4)253/* Enables interrupt generation on the enabled EOF/EOLN/EISLUR254 * bits and short frames..255 */256# define SCALER_DISPCTRL_DISPEIRQ(x) BIT(1 + (x))257/* Enables interrupt generation on scaler profiler interrupt. */258# define SCALER_DISPCTRL_SCLEIRQ BIT(0)259 260#define SCALER_DISPSTAT 0x00000004261# define SCALER_DISPSTAT_RESP_MASK VC4_MASK(15, 14)262# define SCALER_DISPSTAT_RESP_SHIFT 14263# define SCALER_DISPSTAT_RESP_OKAY 0264# define SCALER_DISPSTAT_RESP_EXOKAY 1265# define SCALER_DISPSTAT_RESP_SLVERR 2266# define SCALER_DISPSTAT_RESP_DECERR 3267 268# define SCALER_DISPSTAT_COBLOW(x) BIT(13 + ((x) * 8))269/* Set when the DISPEOLN line is done compositing. */270# define SCALER_DISPSTAT_EOLN(x) BIT(12 + ((x) * 8))271/* Set when VSTART is seen but there are still pixels in the current272 * output line.273 */274# define SCALER_DISPSTAT_ESFRAME(x) BIT(11 + ((x) * 8))275/* Set when HSTART is seen but there are still pixels in the current276 * output line.277 */278# define SCALER_DISPSTAT_ESLINE(x) BIT(10 + ((x) * 8))279/* Set when the downstream tries to read from the display FIFO280 * while it's empty.281 */282# define SCALER_DISPSTAT_EUFLOW(x) BIT(9 + ((x) * 8))283/* Set when the display mode changes from RUN to EOF */284# define SCALER_DISPSTAT_EOF(x) BIT(8 + ((x) * 8))285 286# define SCALER_DISPSTAT_IRQMASK(x) VC4_MASK(13 + ((x) * 8), \287 8 + ((x) * 8))288 289/* Set on AXI invalid DMA ID error. */290# define SCALER_DISPSTAT_DMA_ERROR BIT(7)291/* Set on AXI slave read decode error */292# define SCALER_DISPSTAT_IRQSLVRD BIT(6)293/* Set on AXI slave write decode error */294# define SCALER_DISPSTAT_IRQSLVWR BIT(5)295/* Set when SCALER_DISPSTAT_DMA_ERROR is set, or296 * SCALER_DISPSTAT_RESP_ERROR is not SCALER_DISPSTAT_RESP_OKAY.297 */298# define SCALER_DISPSTAT_IRQDMA BIT(4)299/* Set when any of the EOF/EOLN/ESFRAME/ESLINE bits are set and their300 * corresponding interrupt bit is enabled in DISPCTRL.301 */302# define SCALER_DISPSTAT_IRQDISP(x) BIT(1 + (x))303/* On read, the profiler interrupt. On write, clear *all* interrupt bits. */304# define SCALER_DISPSTAT_IRQSCL BIT(0)305 306#define SCALER_DISPID 0x00000008307#define SCALER_DISPECTRL 0x0000000c308# define SCALER_DISPECTRL_DSP2_MUX_SHIFT 31309# define SCALER_DISPECTRL_DSP2_MUX_MASK VC4_MASK(31, 31)310 311#define SCALER_DISPPROF 0x00000010312 313#define SCALER_DISPDITHER 0x00000014314# define SCALER_DISPDITHER_DSP5_MUX_SHIFT 30315# define SCALER_DISPDITHER_DSP5_MUX_MASK VC4_MASK(31, 30)316 317#define SCALER_DISPEOLN 0x00000018318# define SCALER_DISPEOLN_DSP4_MUX_SHIFT 30319# define SCALER_DISPEOLN_DSP4_MUX_MASK VC4_MASK(31, 30)320 321#define SCALER_DISPLIST0 0x00000020322#define SCALER_DISPLIST1 0x00000024323#define SCALER_DISPLIST2 0x00000028324#define SCALER_DISPLSTAT 0x0000002c325#define SCALER_DISPLISTX(x) (SCALER_DISPLIST0 + \326 (x) * (SCALER_DISPLIST1 - \327 SCALER_DISPLIST0))328 329#define SCALER_DISPLACT0 0x00000030330#define SCALER_DISPLACT1 0x00000034331#define SCALER_DISPLACT2 0x00000038332#define SCALER_DISPLACTX(x) (SCALER_DISPLACT0 + \333 (x) * (SCALER_DISPLACT1 - \334 SCALER_DISPLACT0))335 336#define SCALER_DISPCTRL0 0x00000040337# define SCALER_DISPCTRLX_ENABLE BIT(31)338# define SCALER_DISPCTRLX_RESET BIT(30)339/* Generates a single frame when VSTART is seen and stops at the last340 * pixel read from the FIFO.341 */342# define SCALER_DISPCTRLX_ONESHOT BIT(29)343/* Processes a single context in the dlist and then task switch,344 * instead of an entire line.345 */346# define SCALER_DISPCTRLX_ONECTX BIT(28)347/* Set to have DISPSLAVE return 2 16bpp pixels and no status data. */348# define SCALER_DISPCTRLX_FIFO32 BIT(27)349/* Turns on output to the DISPSLAVE register instead of the normal350 * FIFO.351 */352# define SCALER_DISPCTRLX_FIFOREG BIT(26)353 354# define SCALER_DISPCTRLX_WIDTH_MASK VC4_MASK(23, 12)355# define SCALER_DISPCTRLX_WIDTH_SHIFT 12356# define SCALER_DISPCTRLX_HEIGHT_MASK VC4_MASK(11, 0)357# define SCALER_DISPCTRLX_HEIGHT_SHIFT 0358 359# define SCALER5_DISPCTRLX_WIDTH_MASK VC4_MASK(28, 16)360# define SCALER5_DISPCTRLX_WIDTH_SHIFT 16361/* Generates a single frame when VSTART is seen and stops at the last362 * pixel read from the FIFO.363 */364# define SCALER5_DISPCTRLX_ONESHOT BIT(15)365/* Processes a single context in the dlist and then task switch,366 * instead of an entire line.367 */368# define SCALER5_DISPCTRLX_ONECTX_MASK VC4_MASK(14, 13)369# define SCALER5_DISPCTRLX_ONECTX_SHIFT 13370# define SCALER5_DISPCTRLX_HEIGHT_MASK VC4_MASK(12, 0)371# define SCALER5_DISPCTRLX_HEIGHT_SHIFT 0372 373#define SCALER_DISPBKGND0 0x00000044374# define SCALER_DISPBKGND_AUTOHS BIT(31)375# define SCALER5_DISPBKGND_BCK2BCK BIT(31)376# define SCALER_DISPBKGND_INTERLACE BIT(30)377# define SCALER_DISPBKGND_GAMMA BIT(29)378# define SCALER_DISPBKGND_TESTMODE_MASK VC4_MASK(28, 25)379# define SCALER_DISPBKGND_TESTMODE_SHIFT 25380/* Enables filling the scaler line with the RGB value in the low 24381 * bits before compositing. Costs cycles, so should be skipped if382 * opaque display planes will cover everything.383 */384# define SCALER_DISPBKGND_FILL BIT(24)385 386#define SCALER_DISPSTAT0 0x00000048387# define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30)388# define SCALER_DISPSTATX_MODE_SHIFT 30389# define SCALER_DISPSTATX_MODE_DISABLED 0390# define SCALER_DISPSTATX_MODE_INIT 1391# define SCALER_DISPSTATX_MODE_RUN 2392# define SCALER_DISPSTATX_MODE_EOF 3393# define SCALER_DISPSTATX_FULL BIT(29)394# define SCALER_DISPSTATX_EMPTY BIT(28)395# define SCALER_DISPSTATX_LINE_MASK VC4_MASK(11, 0)396# define SCALER_DISPSTATX_LINE_SHIFT 0397 398#define SCALER_DISPBASE0 0x0000004c399/* Last pixel in the COB (display FIFO memory) allocated to this HVS400 * channel. Must be 4-pixel aligned (and thus 4 pixels less than the401 * next COB base).402 */403# define SCALER_DISPBASEX_TOP_MASK VC4_MASK(31, 16)404# define SCALER_DISPBASEX_TOP_SHIFT 16405/* First pixel in the COB (display FIFO memory) allocated to this HVS406 * channel. Must be 4-pixel aligned.407 */408# define SCALER_DISPBASEX_BASE_MASK VC4_MASK(15, 0)409# define SCALER_DISPBASEX_BASE_SHIFT 0410 411#define SCALER_DISPCTRL1 0x00000050412#define SCALER_DISPBKGND1 0x00000054413#define SCALER_DISPBKGNDX(x) (SCALER_DISPBKGND0 + \414 (x) * (SCALER_DISPBKGND1 - \415 SCALER_DISPBKGND0))416#define SCALER_DISPSTAT1 0x00000058417# define SCALER_DISPSTAT1_FRCNT0_MASK VC4_MASK(23, 18)418# define SCALER_DISPSTAT1_FRCNT0_SHIFT 18419# define SCALER_DISPSTAT1_FRCNT1_MASK VC4_MASK(17, 12)420# define SCALER_DISPSTAT1_FRCNT1_SHIFT 12421 422#define SCALER_DISPSTATX(x) (SCALER_DISPSTAT0 + \423 (x) * (SCALER_DISPSTAT1 - \424 SCALER_DISPSTAT0))425 426#define SCALER_DISPBASE1 0x0000005c427#define SCALER_DISPBASEX(x) (SCALER_DISPBASE0 + \428 (x) * (SCALER_DISPBASE1 - \429 SCALER_DISPBASE0))430#define SCALER_DISPCTRL2 0x00000060431#define SCALER_DISPCTRLX(x) (SCALER_DISPCTRL0 + \432 (x) * (SCALER_DISPCTRL1 - \433 SCALER_DISPCTRL0))434#define SCALER_DISPBKGND2 0x00000064435 436#define SCALER_DISPSTAT2 0x00000068437# define SCALER_DISPSTAT2_FRCNT2_MASK VC4_MASK(17, 12)438# define SCALER_DISPSTAT2_FRCNT2_SHIFT 12439 440#define SCALER_DISPBASE2 0x0000006c441#define SCALER_DISPALPHA2 0x00000070442#define SCALER_GAMADDR 0x00000078443# define SCALER_GAMADDR_AUTOINC BIT(31)444/* Enables all gamma ramp SRAMs, not just those of CRTCs with gamma445 * enabled.446 */447# define SCALER_GAMADDR_SRAMENB BIT(30)448 449#define SCALER_OLEDOFFS 0x00000080450/* Clamps R to [16,235] and G/B to [16,240]. */451# define SCALER_OLEDOFFS_YUVCLAMP BIT(31)452 453/* Chooses which display FIFO the matrix applies to. */454# define SCALER_OLEDOFFS_DISPFIFO_MASK VC4_MASK(25, 24)455# define SCALER_OLEDOFFS_DISPFIFO_SHIFT 24456# define SCALER_OLEDOFFS_DISPFIFO_DISABLED 0457# define SCALER_OLEDOFFS_DISPFIFO_0 1458# define SCALER_OLEDOFFS_DISPFIFO_1 2459# define SCALER_OLEDOFFS_DISPFIFO_2 3460 461/* Offsets are 8-bit 2s-complement. */462# define SCALER_OLEDOFFS_RED_MASK VC4_MASK(23, 16)463# define SCALER_OLEDOFFS_RED_SHIFT 16464# define SCALER_OLEDOFFS_GREEN_MASK VC4_MASK(15, 8)465# define SCALER_OLEDOFFS_GREEN_SHIFT 8466# define SCALER_OLEDOFFS_BLUE_MASK VC4_MASK(7, 0)467# define SCALER_OLEDOFFS_BLUE_SHIFT 0468 469/* The coefficients are S0.9 fractions. */470#define SCALER_OLEDCOEF0 0x00000084471# define SCALER_OLEDCOEF0_B_TO_R_MASK VC4_MASK(29, 20)472# define SCALER_OLEDCOEF0_B_TO_R_SHIFT 20473# define SCALER_OLEDCOEF0_B_TO_G_MASK VC4_MASK(19, 10)474# define SCALER_OLEDCOEF0_B_TO_G_SHIFT 10475# define SCALER_OLEDCOEF0_B_TO_B_MASK VC4_MASK(9, 0)476# define SCALER_OLEDCOEF0_B_TO_B_SHIFT 0477 478#define SCALER_OLEDCOEF1 0x00000088479# define SCALER_OLEDCOEF1_G_TO_R_MASK VC4_MASK(29, 20)480# define SCALER_OLEDCOEF1_G_TO_R_SHIFT 20481# define SCALER_OLEDCOEF1_G_TO_G_MASK VC4_MASK(19, 10)482# define SCALER_OLEDCOEF1_G_TO_G_SHIFT 10483# define SCALER_OLEDCOEF1_G_TO_B_MASK VC4_MASK(9, 0)484# define SCALER_OLEDCOEF1_G_TO_B_SHIFT 0485 486#define SCALER_OLEDCOEF2 0x0000008c487# define SCALER_OLEDCOEF2_R_TO_R_MASK VC4_MASK(29, 20)488# define SCALER_OLEDCOEF2_R_TO_R_SHIFT 20489# define SCALER_OLEDCOEF2_R_TO_G_MASK VC4_MASK(19, 10)490# define SCALER_OLEDCOEF2_R_TO_G_SHIFT 10491# define SCALER_OLEDCOEF2_R_TO_B_MASK VC4_MASK(9, 0)492# define SCALER_OLEDCOEF2_R_TO_B_SHIFT 0493 494/* Slave addresses for DMAing from HVS composition output to other495 * devices. The top bits are valid only in !FIFO32 mode.496 */497#define SCALER_DISPSLAVE0 0x000000c0498#define SCALER_DISPSLAVE1 0x000000c9499#define SCALER_DISPSLAVE2 0x000000d0500# define SCALER_DISPSLAVE_ISSUE_VSTART BIT(31)501# define SCALER_DISPSLAVE_ISSUE_HSTART BIT(30)502/* Set when the current line has been read and an HSTART is required. */503# define SCALER_DISPSLAVE_EOL BIT(26)504/* Set when the display FIFO is empty. */505# define SCALER_DISPSLAVE_EMPTY BIT(25)506/* Set when there is RGB data ready to read. */507# define SCALER_DISPSLAVE_VALID BIT(24)508# define SCALER_DISPSLAVE_RGB_MASK VC4_MASK(23, 0)509# define SCALER_DISPSLAVE_RGB_SHIFT 0510 511#define SCALER_GAMDATA 0x000000e0512#define SCALER_DLIST_START 0x00002000513#define SCALER_DLIST_SIZE 0x00004000514 515#define SCALER5_DLIST_START 0x00004000516 517# define VC4_HDMI_SW_RESET_FORMAT_DETECT BIT(1)518# define VC4_HDMI_SW_RESET_HDMI BIT(0)519 520# define VC4_HDMI_HOTPLUG_CONNECTED BIT(0)521 522# define VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE BIT(27)523# define VC4_HDMI_MAI_CONFIG_BIT_REVERSE BIT(26)524# define VC4_HDMI_MAI_CHANNEL_MASK_MASK VC4_MASK(15, 0)525# define VC4_HDMI_MAI_CHANNEL_MASK_SHIFT 0526 527# define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT BIT(29)528# define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS BIT(24)529# define VC4_HDMI_AUDIO_PACKET_FORCE_SAMPLE_PRESENT BIT(19)530# define VC4_HDMI_AUDIO_PACKET_FORCE_B_FRAME BIT(18)531# define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_MASK VC4_MASK(13, 10)532# define VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER_SHIFT 10533/* If set, then multichannel, otherwise 2 channel. */534# define VC4_HDMI_AUDIO_PACKET_AUDIO_LAYOUT BIT(9)535/* If set, then AUDIO_LAYOUT overrides audio_cea_mask */536# define VC4_HDMI_AUDIO_PACKET_FORCE_AUDIO_LAYOUT BIT(8)537# define VC4_HDMI_AUDIO_PACKET_CEA_MASK_MASK VC4_MASK(7, 0)538# define VC4_HDMI_AUDIO_PACKET_CEA_MASK_SHIFT 0539 540# define VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT_MASK VC4_MASK(23, 16)541# define VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT_SHIFT 16542 543enum {544 VC4_HDMI_MAI_FORMAT_PCM = 2,545 VC4_HDMI_MAI_FORMAT_HBR = 200,546};547 548# define VC4_HDMI_MAI_FORMAT_SAMPLE_RATE_MASK VC4_MASK(15, 8)549# define VC4_HDMI_MAI_FORMAT_SAMPLE_RATE_SHIFT 8550 551enum {552 VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED = 0,553 VC4_HDMI_MAI_SAMPLE_RATE_8000 = 1,554 VC4_HDMI_MAI_SAMPLE_RATE_11025 = 2,555 VC4_HDMI_MAI_SAMPLE_RATE_12000 = 3,556 VC4_HDMI_MAI_SAMPLE_RATE_16000 = 4,557 VC4_HDMI_MAI_SAMPLE_RATE_22050 = 5,558 VC4_HDMI_MAI_SAMPLE_RATE_24000 = 6,559 VC4_HDMI_MAI_SAMPLE_RATE_32000 = 7,560 VC4_HDMI_MAI_SAMPLE_RATE_44100 = 8,561 VC4_HDMI_MAI_SAMPLE_RATE_48000 = 9,562 VC4_HDMI_MAI_SAMPLE_RATE_64000 = 10,563 VC4_HDMI_MAI_SAMPLE_RATE_88200 = 11,564 VC4_HDMI_MAI_SAMPLE_RATE_96000 = 12,565 VC4_HDMI_MAI_SAMPLE_RATE_128000 = 13,566 VC4_HDMI_MAI_SAMPLE_RATE_176400 = 14,567 VC4_HDMI_MAI_SAMPLE_RATE_192000 = 15,568};569 570# define VC4_HDMI_RAM_PACKET_ENABLE BIT(16)571 572/* When set, the CTS_PERIOD counts based on MAI bus sync pulse instead573 * of pixel clock.574 */575# define VC4_HDMI_CRP_USE_MAI_BUS_SYNC_FOR_CTS BIT(26)576/* When set, no CRP packets will be sent. */577# define VC4_HDMI_CRP_CFG_DISABLE BIT(25)578/* If set, generates CTS values based on N, audio clock, and video579 * clock. N must be divisible by 128.580 */581# define VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN BIT(24)582# define VC4_HDMI_CRP_CFG_N_MASK VC4_MASK(19, 0)583# define VC4_HDMI_CRP_CFG_N_SHIFT 0584 585# define VC4_HDMI_HORZA_VPOS BIT(14)586# define VC4_HDMI_HORZA_HPOS BIT(13)587/* Horizontal active pixels (hdisplay). */588# define VC4_HDMI_HORZA_HAP_MASK VC4_MASK(12, 0)589# define VC4_HDMI_HORZA_HAP_SHIFT 0590 591/* Horizontal back porch (htotal - hsync_end). */592# define VC4_HDMI_HORZB_HBP_MASK VC4_MASK(29, 20)593# define VC4_HDMI_HORZB_HBP_SHIFT 20594/* Horizontal sync pulse (hsync_end - hsync_start). */595# define VC4_HDMI_HORZB_HSP_MASK VC4_MASK(19, 10)596# define VC4_HDMI_HORZB_HSP_SHIFT 10597/* Horizontal front porch (hsync_start - hdisplay). */598# define VC4_HDMI_HORZB_HFP_MASK VC4_MASK(9, 0)599# define VC4_HDMI_HORZB_HFP_SHIFT 0600 601# define VC4_HDMI_FIFO_CTL_RECENTER_DONE BIT(14)602# define VC4_HDMI_FIFO_CTL_USE_EMPTY BIT(13)603# define VC4_HDMI_FIFO_CTL_ON_VB BIT(7)604# define VC4_HDMI_FIFO_CTL_RECENTER BIT(6)605# define VC4_HDMI_FIFO_CTL_FIFO_RESET BIT(5)606# define VC4_HDMI_FIFO_CTL_USE_PLL_LOCK BIT(4)607# define VC4_HDMI_FIFO_CTL_INV_CLK_XFR BIT(3)608# define VC4_HDMI_FIFO_CTL_CAPTURE_PTR BIT(2)609# define VC4_HDMI_FIFO_CTL_USE_FULL BIT(1)610# define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N BIT(0)611# define VC4_HDMI_FIFO_VALID_WRITE_MASK 0xefff612 613# define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT BIT(15)614# define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS BIT(5)615# define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT BIT(3)616# define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE BIT(1)617# define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI BIT(0)618 619/* Vertical sync pulse (vsync_end - vsync_start). */620# define VC4_HDMI_VERTA_VSP_MASK VC4_MASK(24, 20)621# define VC4_HDMI_VERTA_VSP_SHIFT 20622/* Vertical front porch (vsync_start - vdisplay). */623# define VC4_HDMI_VERTA_VFP_MASK VC4_MASK(19, 13)624# define VC4_HDMI_VERTA_VFP_SHIFT 13625/* Vertical active lines (vdisplay). */626# define VC4_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)627# define VC4_HDMI_VERTA_VAL_SHIFT 0628 629/* Vertical sync pulse offset (for interlaced) */630# define VC4_HDMI_VERTB_VSPO_MASK VC4_MASK(21, 9)631# define VC4_HDMI_VERTB_VSPO_SHIFT 9632/* Vertical pack porch (vtotal - vsync_end). */633# define VC4_HDMI_VERTB_VBP_MASK VC4_MASK(8, 0)634# define VC4_HDMI_VERTB_VBP_SHIFT 0635 636/* Set when the transmission has ended. */637# define VC4_HDMI_CEC_TX_EOM BIT(31)638/* If set, transmission was acked on the 1st or 2nd attempt (only one639 * retry is attempted). If in continuous mode, this means TX needs to640 * be filled if !TX_EOM.641 */642# define VC4_HDMI_CEC_TX_STATUS_GOOD BIT(30)643# define VC4_HDMI_CEC_RX_EOM BIT(29)644# define VC4_HDMI_CEC_RX_STATUS_GOOD BIT(28)645/* Number of bytes received for the message. */646# define VC4_HDMI_CEC_REC_WRD_CNT_MASK VC4_MASK(27, 24)647# define VC4_HDMI_CEC_REC_WRD_CNT_SHIFT 24648/* Sets continuous receive mode. Generates interrupt after each 8649 * bytes to signal that RX_DATA should be consumed, and at RX_EOM.650 *651 * If disabled, maximum 16 bytes will be received (including header),652 * and interrupt at RX_EOM. Later bytes will be acked but not put653 * into the RX_DATA.654 */655# define VC4_HDMI_CEC_RX_CONTINUE BIT(23)656# define VC4_HDMI_CEC_TX_CONTINUE BIT(22)657/* Set this after a CEC interrupt. */658# define VC4_HDMI_CEC_CLEAR_RECEIVE_OFF BIT(21)659/* Starts a TX. Will wait for appropriate idel time before CEC660 * activity. Must be cleared in between transmits.661 */662# define VC4_HDMI_CEC_START_XMIT_BEGIN BIT(20)663# define VC4_HDMI_CEC_MESSAGE_LENGTH_MASK VC4_MASK(19, 16)664# define VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT 16665/* Device's CEC address */666# define VC4_HDMI_CEC_ADDR_MASK VC4_MASK(15, 12)667# define VC4_HDMI_CEC_ADDR_SHIFT 12668/* Divides off of HSM clock to generate CEC bit clock. */669/* With the current defaults the CEC bit clock is 40 kHz = 25 usec */670# define VC4_HDMI_CEC_DIV_CLK_CNT_MASK VC4_MASK(11, 0)671# define VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT 0672 673/* Set these fields to how many bit clock cycles get to that many674 * microseconds.675 */676# define VC4_HDMI_CEC_CNT_TO_1500_US_MASK VC4_MASK(30, 24)677# define VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT 24678# define VC4_HDMI_CEC_CNT_TO_1300_US_MASK VC4_MASK(23, 17)679# define VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT 17680# define VC4_HDMI_CEC_CNT_TO_800_US_MASK VC4_MASK(16, 11)681# define VC4_HDMI_CEC_CNT_TO_800_US_SHIFT 11682# define VC4_HDMI_CEC_CNT_TO_600_US_MASK VC4_MASK(10, 5)683# define VC4_HDMI_CEC_CNT_TO_600_US_SHIFT 5684# define VC4_HDMI_CEC_CNT_TO_400_US_MASK VC4_MASK(4, 0)685# define VC4_HDMI_CEC_CNT_TO_400_US_SHIFT 0686 687# define VC4_HDMI_CEC_CNT_TO_2750_US_MASK VC4_MASK(31, 24)688# define VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT 24689# define VC4_HDMI_CEC_CNT_TO_2400_US_MASK VC4_MASK(23, 16)690# define VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT 16691# define VC4_HDMI_CEC_CNT_TO_2050_US_MASK VC4_MASK(15, 8)692# define VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT 8693# define VC4_HDMI_CEC_CNT_TO_1700_US_MASK VC4_MASK(7, 0)694# define VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT 0695 696# define VC4_HDMI_CEC_CNT_TO_4300_US_MASK VC4_MASK(31, 24)697# define VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT 24698# define VC4_HDMI_CEC_CNT_TO_3900_US_MASK VC4_MASK(23, 16)699# define VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT 16700# define VC4_HDMI_CEC_CNT_TO_3600_US_MASK VC4_MASK(15, 8)701# define VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT 8702# define VC4_HDMI_CEC_CNT_TO_3500_US_MASK VC4_MASK(7, 0)703# define VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT 0704 705# define VC4_HDMI_CEC_TX_SW_RESET BIT(27)706# define VC4_HDMI_CEC_RX_SW_RESET BIT(26)707# define VC4_HDMI_CEC_PAD_SW_RESET BIT(25)708# define VC4_HDMI_CEC_MUX_TP_OUT_CEC BIT(24)709# define VC4_HDMI_CEC_RX_CEC_INT BIT(23)710# define VC4_HDMI_CEC_CLK_PRELOAD_MASK VC4_MASK(22, 16)711# define VC4_HDMI_CEC_CLK_PRELOAD_SHIFT 16712# define VC4_HDMI_CEC_CNT_TO_4700_US_MASK VC4_MASK(15, 8)713# define VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT 8714# define VC4_HDMI_CEC_CNT_TO_4500_US_MASK VC4_MASK(7, 0)715# define VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT 0716 717# define VC4_HDMI_TX_PHY_RNG_PWRDN BIT(25)718 719# define VC4_HDMI_CPU_CEC BIT(6)720# define VC4_HDMI_CPU_HOTPLUG BIT(0)721 722/* Debug: Current receive value on the CEC pad. */723# define VC4_HD_CECRXD BIT(9)724/* Debug: Override CEC output to 0. */725# define VC4_HD_CECOVR BIT(8)726# define VC4_HD_M_REGISTER_FILE_STANDBY (3 << 6)727# define VC4_HD_M_RAM_STANDBY (3 << 4)728# define VC4_HD_M_SW_RST BIT(2)729# define VC4_HD_M_ENABLE BIT(0)730 731/* Set when audio stream is received at a slower rate than the732 * sampling period, so MAI fifo goes empty. Write 1 to clear.733 */734# define VC4_HD_MAI_CTL_DLATE BIT(15)735# define VC4_HD_MAI_CTL_BUSY BIT(14)736# define VC4_HD_MAI_CTL_CHALIGN BIT(13)737# define VC4_HD_MAI_CTL_WHOLSMP BIT(12)738# define VC4_HD_MAI_CTL_FULL BIT(11)739# define VC4_HD_MAI_CTL_EMPTY BIT(10)740# define VC4_HD_MAI_CTL_FLUSH BIT(9)741/* If set, MAI bus generates SPDIF (bit 31) parity instead of passing742 * through.743 */744# define VC4_HD_MAI_CTL_PAREN BIT(8)745# define VC4_HD_MAI_CTL_CHNUM_MASK VC4_MASK(7, 4)746# define VC4_HD_MAI_CTL_CHNUM_SHIFT 4747# define VC4_HD_MAI_CTL_ENABLE BIT(3)748/* Underflow error status bit, write 1 to clear. */749# define VC4_HD_MAI_CTL_ERRORE BIT(2)750/* Overflow error status bit, write 1 to clear. */751# define VC4_HD_MAI_CTL_ERRORF BIT(1)752/* Single-shot reset bit. Read value is undefined. */753# define VC4_HD_MAI_CTL_RESET BIT(0)754 755# define VC4_HD_MAI_THR_PANICHIGH_MASK VC4_MASK(29, 24)756# define VC4_HD_MAI_THR_PANICHIGH_SHIFT 24757# define VC4_HD_MAI_THR_PANICLOW_MASK VC4_MASK(21, 16)758# define VC4_HD_MAI_THR_PANICLOW_SHIFT 16759# define VC4_HD_MAI_THR_DREQHIGH_MASK VC4_MASK(13, 8)760# define VC4_HD_MAI_THR_DREQHIGH_SHIFT 8761# define VC4_HD_MAI_THR_DREQLOW_MASK VC4_MASK(5, 0)762# define VC4_HD_MAI_THR_DREQLOW_SHIFT 0763 764/* Divider from HDMI HSM clock to MAI serial clock. Sampling period765 * converges to N / (M + 1) cycles.766 */767# define VC4_HD_MAI_SMP_N_MASK VC4_MASK(31, 8)768# define VC4_HD_MAI_SMP_N_SHIFT 8769# define VC4_HD_MAI_SMP_M_MASK VC4_MASK(7, 0)770# define VC4_HD_MAI_SMP_M_SHIFT 0771 772# define VC4_HD_VID_CTL_ENABLE BIT(31)773# define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30)774# define VC4_HD_VID_CTL_FRAME_COUNTER_RESET BIT(29)775# define VC4_HD_VID_CTL_VSYNC_LOW BIT(28)776# define VC4_HD_VID_CTL_HSYNC_LOW BIT(27)777# define VC4_HD_VID_CTL_CLRSYNC BIT(24)778# define VC4_HD_VID_CTL_CLRRGB BIT(23)779# define VC4_HD_VID_CTL_BLANKPIX BIT(18)780 781# define VC4_HD_CSC_CTL_ORDER_MASK VC4_MASK(7, 5)782# define VC4_HD_CSC_CTL_ORDER_SHIFT 5783# define VC4_HD_CSC_CTL_ORDER_RGB 0784# define VC4_HD_CSC_CTL_ORDER_BGR 1785# define VC4_HD_CSC_CTL_ORDER_BRG 2786# define VC4_HD_CSC_CTL_ORDER_GRB 3787# define VC4_HD_CSC_CTL_ORDER_GBR 4788# define VC4_HD_CSC_CTL_ORDER_RBG 5789# define VC4_HD_CSC_CTL_PADMSB BIT(4)790# define VC4_HD_CSC_CTL_MODE_MASK VC4_MASK(3, 2)791# define VC4_HD_CSC_CTL_MODE_SHIFT 2792# define VC4_HD_CSC_CTL_MODE_RGB_TO_SD_YPRPB 0793# define VC4_HD_CSC_CTL_MODE_RGB_TO_HD_YPRPB 1794# define VC4_HD_CSC_CTL_MODE_CUSTOM 3795# define VC4_HD_CSC_CTL_RGB2YCC BIT(1)796# define VC4_HD_CSC_CTL_ENABLE BIT(0)797 798# define VC5_MT_CP_CSC_CTL_USE_444_TO_422 BIT(6)799# define VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_MASK \800 VC4_MASK(5, 4)801# define VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD \802 3803# define VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION BIT(3)804# define VC5_MT_CP_CSC_CTL_ENABLE BIT(2)805# define VC5_MT_CP_CSC_CTL_MODE_MASK VC4_MASK(1, 0)806 807# define VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_MASK \808 VC4_MASK(7, 6)809# define VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE \810 2811 812# define VC4_DVP_HT_CLOCK_STOP_PIXEL BIT(1)813 814# define VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_MASK \815 VC4_MASK(3, 2)816# define VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY \817 2818 819/* HVS display list information. */820#define HVS_BOOTLOADER_DLIST_END 32821 822enum hvs_pixel_format {823 /* 8bpp */824 HVS_PIXEL_FORMAT_RGB332 = 0,825 /* 16bpp */826 HVS_PIXEL_FORMAT_RGBA4444 = 1,827 HVS_PIXEL_FORMAT_RGB555 = 2,828 HVS_PIXEL_FORMAT_RGBA5551 = 3,829 HVS_PIXEL_FORMAT_RGB565 = 4,830 /* 24bpp */831 HVS_PIXEL_FORMAT_RGB888 = 5,832 HVS_PIXEL_FORMAT_RGBA6666 = 6,833 /* 32bpp */834 HVS_PIXEL_FORMAT_RGBA8888 = 7,835 836 HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE = 8,837 HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE = 9,838 HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE = 10,839 HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE = 11,840 HVS_PIXEL_FORMAT_H264 = 12,841 HVS_PIXEL_FORMAT_PALETTE = 13,842 HVS_PIXEL_FORMAT_YUV444_RGB = 14,843 HVS_PIXEL_FORMAT_AYUV444_RGB = 15,844 HVS_PIXEL_FORMAT_RGBA1010102 = 16,845 HVS_PIXEL_FORMAT_YCBCR_10BIT = 17,846};847 848/* Note: the LSB is the rightmost character shown. Only valid for849 * HVS_PIXEL_FORMAT_RGB8888, not RGB888.850 */851/* For modes 332, 4444, 555, 5551, 6666, 8888, 10:10:10:2 */852#define HVS_PIXEL_ORDER_RGBA 0853#define HVS_PIXEL_ORDER_BGRA 1854#define HVS_PIXEL_ORDER_ARGB 2855#define HVS_PIXEL_ORDER_ABGR 3856 857/* For modes 666 and 888 (4 & 5) */858#define HVS_PIXEL_ORDER_XBRG 0859#define HVS_PIXEL_ORDER_XRBG 1860#define HVS_PIXEL_ORDER_XRGB 2861#define HVS_PIXEL_ORDER_XBGR 3862 863/* For YCbCr modes (8-12, and 17) */864#define HVS_PIXEL_ORDER_XYCBCR 0865#define HVS_PIXEL_ORDER_XYCRCB 1866#define HVS_PIXEL_ORDER_YXCBCR 2867#define HVS_PIXEL_ORDER_YXCRCB 3868 869#define SCALER_CTL0_END BIT(31)870#define SCALER_CTL0_VALID BIT(30)871 872#define SCALER_CTL0_SIZE_MASK VC4_MASK(29, 24)873#define SCALER_CTL0_SIZE_SHIFT 24874 875#define SCALER_CTL0_TILING_MASK VC4_MASK(21, 20)876#define SCALER_CTL0_TILING_SHIFT 20877#define SCALER_CTL0_TILING_LINEAR 0878#define SCALER_CTL0_TILING_64B 1879#define SCALER_CTL0_TILING_128B 2880#define SCALER_CTL0_TILING_256B_OR_T 3881 882#define SCALER_CTL0_ALPHA_MASK BIT(19)883#define SCALER_CTL0_HFLIP BIT(16)884#define SCALER_CTL0_VFLIP BIT(15)885 886#define SCALER_CTL0_KEY_MODE_MASK VC4_MASK(18, 17)887#define SCALER_CTL0_KEY_MODE_SHIFT 17888#define SCALER_CTL0_KEY_DISABLED 0889#define SCALER_CTL0_KEY_LUMA_OR_COMMON_RGB 1890#define SCALER_CTL0_KEY_MATCH 2 /* turn transparent */891#define SCALER_CTL0_KEY_REPLACE 3 /* replace with value from key mask word 2 */892 893#define SCALER_CTL0_ORDER_MASK VC4_MASK(14, 13)894#define SCALER_CTL0_ORDER_SHIFT 13895 896#define SCALER_CTL0_RGBA_EXPAND_MASK VC4_MASK(12, 11)897#define SCALER_CTL0_RGBA_EXPAND_SHIFT 11898#define SCALER_CTL0_RGBA_EXPAND_ZERO 0899#define SCALER_CTL0_RGBA_EXPAND_LSB 1900#define SCALER_CTL0_RGBA_EXPAND_MSB 2901#define SCALER_CTL0_RGBA_EXPAND_ROUND 3902 903#define SCALER5_CTL0_ALPHA_EXPAND BIT(12)904 905#define SCALER5_CTL0_RGB_EXPAND BIT(11)906 907#define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8)908#define SCALER_CTL0_SCL1_SHIFT 8909 910#define SCALER_CTL0_SCL0_MASK VC4_MASK(7, 5)911#define SCALER_CTL0_SCL0_SHIFT 5912 913#define SCALER_CTL0_SCL_H_PPF_V_PPF 0914#define SCALER_CTL0_SCL_H_TPZ_V_PPF 1915#define SCALER_CTL0_SCL_H_PPF_V_TPZ 2916#define SCALER_CTL0_SCL_H_TPZ_V_TPZ 3917#define SCALER_CTL0_SCL_H_PPF_V_NONE 4918#define SCALER_CTL0_SCL_H_NONE_V_PPF 5919#define SCALER_CTL0_SCL_H_NONE_V_TPZ 6920#define SCALER_CTL0_SCL_H_TPZ_V_NONE 7921 922/* Set to indicate no scaling. */923#define SCALER_CTL0_UNITY BIT(4)924#define SCALER5_CTL0_UNITY BIT(15)925 926#define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0)927#define SCALER_CTL0_PIXEL_FORMAT_SHIFT 0928 929#define SCALER5_CTL0_PIXEL_FORMAT_MASK VC4_MASK(4, 0)930 931#define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24)932#define SCALER_POS0_FIXED_ALPHA_SHIFT 24933 934#define SCALER_POS0_START_Y_MASK VC4_MASK(23, 12)935#define SCALER_POS0_START_Y_SHIFT 12936 937#define SCALER_POS0_START_X_MASK VC4_MASK(11, 0)938#define SCALER_POS0_START_X_SHIFT 0939 940#define SCALER5_POS0_START_Y_MASK VC4_MASK(27, 16)941#define SCALER5_POS0_START_Y_SHIFT 16942 943#define SCALER5_POS0_START_X_MASK VC4_MASK(13, 0)944#define SCALER5_POS0_START_X_SHIFT 0945 946#define SCALER5_POS0_VFLIP BIT(31)947#define SCALER5_POS0_HFLIP BIT(15)948 949#define SCALER5_CTL2_ALPHA_MODE_MASK VC4_MASK(31, 30)950#define SCALER5_CTL2_ALPHA_MODE_SHIFT 30951#define SCALER5_CTL2_ALPHA_MODE_PIPELINE 0952#define SCALER5_CTL2_ALPHA_MODE_FIXED 1953#define SCALER5_CTL2_ALPHA_MODE_FIXED_NONZERO 2954#define SCALER5_CTL2_ALPHA_MODE_FIXED_OVER_0x07 3955 956#define SCALER5_CTL2_ALPHA_PREMULT BIT(29)957 958#define SCALER5_CTL2_ALPHA_MIX BIT(28)959 960#define SCALER5_CTL2_ALPHA_LOC BIT(25)961 962#define SCALER5_CTL2_MAP_SEL_MASK VC4_MASK(18, 17)963#define SCALER5_CTL2_MAP_SEL_SHIFT 17964 965#define SCALER5_CTL2_GAMMA BIT(16)966 967#define SCALER5_CTL2_ALPHA_MASK VC4_MASK(15, 4)968#define SCALER5_CTL2_ALPHA_SHIFT 4969 970#define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16)971#define SCALER_POS1_SCL_HEIGHT_SHIFT 16972 973#define SCALER_POS1_SCL_WIDTH_MASK VC4_MASK(11, 0)974#define SCALER_POS1_SCL_WIDTH_SHIFT 0975 976#define SCALER5_POS1_SCL_HEIGHT_MASK VC4_MASK(28, 16)977#define SCALER5_POS1_SCL_HEIGHT_SHIFT 16978 979#define SCALER5_POS1_SCL_WIDTH_MASK VC4_MASK(12, 0)980#define SCALER5_POS1_SCL_WIDTH_SHIFT 0981 982#define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30)983#define SCALER_POS2_ALPHA_MODE_SHIFT 30984#define SCALER_POS2_ALPHA_MODE_PIPELINE 0985#define SCALER_POS2_ALPHA_MODE_FIXED 1986#define SCALER_POS2_ALPHA_MODE_FIXED_NONZERO 2987#define SCALER_POS2_ALPHA_MODE_FIXED_OVER_0x07 3988#define SCALER_POS2_ALPHA_PREMULT BIT(29)989#define SCALER_POS2_ALPHA_MIX BIT(28)990 991#define SCALER_POS2_HEIGHT_MASK VC4_MASK(27, 16)992#define SCALER_POS2_HEIGHT_SHIFT 16993 994#define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0)995#define SCALER_POS2_WIDTH_SHIFT 0996 997#define SCALER5_POS2_HEIGHT_MASK VC4_MASK(28, 16)998#define SCALER5_POS2_HEIGHT_SHIFT 16999 1000#define SCALER5_POS2_WIDTH_MASK VC4_MASK(12, 0)1001#define SCALER5_POS2_WIDTH_SHIFT 01002 1003/* Color Space Conversion words. Some values are S2.8 signed1004 * integers, except that the 2 integer bits map as {0x0: 0, 0x1: 1,1005 * 0x2: 2, 0x3: -1}1006 */1007/* bottom 8 bits of S2.8 contribution of Cr to Blue */1008#define SCALER_CSC0_COEF_CR_BLU_MASK VC4_MASK(31, 24)1009#define SCALER_CSC0_COEF_CR_BLU_SHIFT 241010/* Signed offset to apply to Y before CSC. (Y' = Y + YY_OFS) */1011#define SCALER_CSC0_COEF_YY_OFS_MASK VC4_MASK(23, 16)1012#define SCALER_CSC0_COEF_YY_OFS_SHIFT 161013/* Signed offset to apply to CB before CSC (Cb' = Cb - 128 + CB_OFS). */1014#define SCALER_CSC0_COEF_CB_OFS_MASK VC4_MASK(15, 8)1015#define SCALER_CSC0_COEF_CB_OFS_SHIFT 81016/* Signed offset to apply to CB before CSC (Cr' = Cr - 128 + CR_OFS). */1017#define SCALER_CSC0_COEF_CR_OFS_MASK VC4_MASK(7, 0)1018#define SCALER_CSC0_COEF_CR_OFS_SHIFT 01019#define SCALER_CSC0_ITR_R_601_5 0x00f000001020#define SCALER_CSC0_ITR_R_709_3 0x00f000001021#define SCALER_CSC0_ITR_R_2020 0x00f000001022#define SCALER_CSC0_JPEG_JFIF 0x000000001023#define SCALER_CSC0_ITR_R_709_3_FR 0x000000001024#define SCALER_CSC0_ITR_R_2020_FR 0x000000001025 1026/* S2.8 contribution of Cb to Green */1027#define SCALER_CSC1_COEF_CB_GRN_MASK VC4_MASK(31, 22)1028#define SCALER_CSC1_COEF_CB_GRN_SHIFT 221029/* S2.8 contribution of Cr to Green */1030#define SCALER_CSC1_COEF_CR_GRN_MASK VC4_MASK(21, 12)1031#define SCALER_CSC1_COEF_CR_GRN_SHIFT 121032/* S2.8 contribution of Y to all of RGB */1033#define SCALER_CSC1_COEF_YY_ALL_MASK VC4_MASK(11, 2)1034#define SCALER_CSC1_COEF_YY_ALL_SHIFT 21035/* top 2 bits of S2.8 contribution of Cr to Blue */1036#define SCALER_CSC1_COEF_CR_BLU_MASK VC4_MASK(1, 0)1037#define SCALER_CSC1_COEF_CR_BLU_SHIFT 01038#define SCALER_CSC1_ITR_R_601_5 0xe73304a81039#define SCALER_CSC1_ITR_R_709_3 0xf27784a81040#define SCALER_CSC1_ITR_R_2020 0xf43594a81041#define SCALER_CSC1_JPEG_JFIF 0xea3494001042#define SCALER_CSC1_ITR_R_709_3_FR 0xf43884001043#define SCALER_CSC1_ITR_R_2020_FR 0xf5b6d4001044 1045/* S2.8 contribution of Cb to Red */1046#define SCALER_CSC2_COEF_CB_RED_MASK VC4_MASK(29, 20)1047#define SCALER_CSC2_COEF_CB_RED_SHIFT 201048/* S2.8 contribution of Cr to Red */1049#define SCALER_CSC2_COEF_CR_RED_MASK VC4_MASK(19, 10)1050#define SCALER_CSC2_COEF_CR_RED_SHIFT 101051/* S2.8 contribution of Cb to Blue */1052#define SCALER_CSC2_COEF_CB_BLU_MASK VC4_MASK(19, 10)1053#define SCALER_CSC2_COEF_CB_BLU_SHIFT 101054#define SCALER_CSC2_ITR_R_601_5 0x000666041055#define SCALER_CSC2_ITR_R_709_3 0x00072e1d1056#define SCALER_CSC2_ITR_R_2020 0x0006b6241057#define SCALER_CSC2_JPEG_JFIF 0x00059dc61058#define SCALER_CSC2_ITR_R_709_3_FR 0x00064ddb1059#define SCALER_CSC2_ITR_R_2020_FR 0x0005e5e21060 1061#define SCALER_TPZ0_VERT_RECALC BIT(31)1062#define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8)1063#define SCALER_TPZ0_SCALE_SHIFT 81064#define SCALER_TPZ0_IPHASE_MASK VC4_MASK(7, 0)1065#define SCALER_TPZ0_IPHASE_SHIFT 01066#define SCALER_TPZ1_RECIP_MASK VC4_MASK(15, 0)1067#define SCALER_TPZ1_RECIP_SHIFT 01068 1069/* Skips interpolating coefficients to 64 phases, so just 8 are used.1070 * Required for nearest neighbor.1071 */1072#define SCALER_PPF_NOINTERP BIT(31)1073/* Replaes the highest valued coefficient with one that makes all 41074 * sum to unity.1075 */1076#define SCALER_PPF_AGC BIT(30)1077#define SCALER_PPF_SCALE_MASK VC4_MASK(24, 8)1078#define SCALER_PPF_SCALE_SHIFT 81079#define SCALER_PPF_IPHASE_MASK VC4_MASK(6, 0)1080#define SCALER_PPF_IPHASE_SHIFT 01081 1082#define SCALER_PPF_KERNEL_OFFSET_MASK VC4_MASK(13, 0)1083#define SCALER_PPF_KERNEL_OFFSET_SHIFT 01084#define SCALER_PPF_KERNEL_UNCACHED BIT(31)1085 1086/* PITCH0/1/2 fields for raster. */1087#define SCALER_SRC_PITCH_MASK VC4_MASK(15, 0)1088#define SCALER_SRC_PITCH_SHIFT 01089 1090/* PITCH0/1/2 fields for tiled (SAND). */1091#define SCALER_TILE_SKIP_0_MASK VC4_MASK(18, 16)1092#define SCALER_TILE_SKIP_0_SHIFT 161093#define SCALER_TILE_HEIGHT_MASK VC4_MASK(15, 0)1094#define SCALER_TILE_HEIGHT_SHIFT 01095 1096/* Common PITCH0 fields */1097#define SCALER_PITCH0_SINK_PIX_MASK VC4_MASK(31, 26)1098#define SCALER_PITCH0_SINK_PIX_SHIFT 261099 1100/* PITCH0 fields for T-tiled. */1101#define SCALER_PITCH0_TILE_WIDTH_L_MASK VC4_MASK(22, 16)1102#define SCALER_PITCH0_TILE_WIDTH_L_SHIFT 161103#define SCALER_PITCH0_TILE_LINE_DIR BIT(15)1104#define SCALER_PITCH0_TILE_INITIAL_LINE_DIR BIT(14)1105/* Y offset within a tile. */1106#define SCALER_PITCH0_TILE_Y_OFFSET_MASK VC4_MASK(13, 8)1107#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT 81108#define SCALER_PITCH0_TILE_WIDTH_R_MASK VC4_MASK(6, 0)1109#define SCALER_PITCH0_TILE_WIDTH_R_SHIFT 01110 1111#endif /* VC4_REGS_H */1112