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1// SPDX-License-Identifier: GPL-2.0-only2/*3 * Copyright (C) 2016 Broadcom4 */5 6/**7 * DOC: VC4 SDTV module8 *9 * The VEC encoder generates PAL or NTSC composite video output.10 *11 * TV mode selection is done by an atomic property on the encoder,12 * because a drm_mode_modeinfo is insufficient to distinguish between13 * PAL and PAL-M or NTSC and NTSC-J.14 */15 16#include <drm/drm_atomic_helper.h>17#include <drm/drm_drv.h>18#include <drm/drm_edid.h>19#include <drm/drm_panel.h>20#include <drm/drm_probe_helper.h>21#include <drm/drm_simple_kms_helper.h>22#include <linux/clk.h>23#include <linux/component.h>24#include <linux/of.h>25#include <linux/platform_device.h>26#include <linux/pm_runtime.h>27 28#include "vc4_drv.h"29#include "vc4_regs.h"30 31/* WSE Registers */32#define VEC_WSE_RESET 0xc033 34#define VEC_WSE_CONTROL 0xc435#define VEC_WSE_WSS_ENABLE BIT(7)36 37#define VEC_WSE_WSS_DATA 0xc838#define VEC_WSE_VPS_DATA1 0xcc39#define VEC_WSE_VPS_CONTROL 0xd040 41/* VEC Registers */42#define VEC_REVID 0x10043 44#define VEC_CONFIG0 0x10445#define VEC_CONFIG0_YDEL_MASK GENMASK(28, 26)46#define VEC_CONFIG0_YDEL(x) ((x) << 26)47#define VEC_CONFIG0_CDEL_MASK GENMASK(25, 24)48#define VEC_CONFIG0_CDEL(x) ((x) << 24)49#define VEC_CONFIG0_SECAM_STD BIT(21)50#define VEC_CONFIG0_PBPR_FIL BIT(18)51#define VEC_CONFIG0_CHROMA_GAIN_MASK GENMASK(17, 16)52#define VEC_CONFIG0_CHROMA_GAIN_UNITY (0 << 16)53#define VEC_CONFIG0_CHROMA_GAIN_1_32 (1 << 16)54#define VEC_CONFIG0_CHROMA_GAIN_1_16 (2 << 16)55#define VEC_CONFIG0_CHROMA_GAIN_1_8 (3 << 16)56#define VEC_CONFIG0_CBURST_GAIN_MASK GENMASK(14, 13)57#define VEC_CONFIG0_CBURST_GAIN_UNITY (0 << 13)58#define VEC_CONFIG0_CBURST_GAIN_1_128 (1 << 13)59#define VEC_CONFIG0_CBURST_GAIN_1_64 (2 << 13)60#define VEC_CONFIG0_CBURST_GAIN_1_32 (3 << 13)61#define VEC_CONFIG0_CHRBW1 BIT(11)62#define VEC_CONFIG0_CHRBW0 BIT(10)63#define VEC_CONFIG0_SYNCDIS BIT(9)64#define VEC_CONFIG0_BURDIS BIT(8)65#define VEC_CONFIG0_CHRDIS BIT(7)66#define VEC_CONFIG0_PDEN BIT(6)67#define VEC_CONFIG0_YCDELAY BIT(4)68#define VEC_CONFIG0_RAMPEN BIT(2)69#define VEC_CONFIG0_YCDIS BIT(2)70#define VEC_CONFIG0_STD_MASK GENMASK(1, 0)71#define VEC_CONFIG0_NTSC_STD 072#define VEC_CONFIG0_PAL_BDGHI_STD 173#define VEC_CONFIG0_PAL_M_STD 274#define VEC_CONFIG0_PAL_N_STD 375 76#define VEC_SCHPH 0x10877#define VEC_SOFT_RESET 0x10c78#define VEC_CLMP0_START 0x14479#define VEC_CLMP0_END 0x14880 81/*82 * These set the color subcarrier frequency83 * if VEC_CONFIG1_CUSTOM_FREQ is enabled.84 *85 * VEC_FREQ1_0 contains the most significant 16-bit half-word,86 * VEC_FREQ3_2 contains the least significant 16-bit half-word.87 * 0x80000000 seems to be equivalent to the pixel clock88 * (which itself is the VEC clock divided by 8).89 *90 * Reference values (with the default pixel clock of 13.5 MHz):91 *92 * NTSC (3579545.[45] Hz) - 0x21F07C1F93 * PAL (4433618.75 Hz) - 0x2A098ACB94 * PAL-M (3575611.[888111] Hz) - 0x21E6EFE395 * PAL-N (3582056.25 Hz) - 0x21F6944696 *97 * NOTE: For SECAM, it is used as the Dr center frequency,98 * regardless of whether VEC_CONFIG1_CUSTOM_FREQ is enabled or not;99 * that is specified as 4406250 Hz, which corresponds to 0x29C71C72.100 */101#define VEC_FREQ3_2 0x180102#define VEC_FREQ1_0 0x184103 104#define VEC_CONFIG1 0x188105#define VEC_CONFIG_VEC_RESYNC_OFF BIT(18)106#define VEC_CONFIG_RGB219 BIT(17)107#define VEC_CONFIG_CBAR_EN BIT(16)108#define VEC_CONFIG_TC_OBB BIT(15)109#define VEC_CONFIG1_OUTPUT_MODE_MASK GENMASK(12, 10)110#define VEC_CONFIG1_C_Y_CVBS (0 << 10)111#define VEC_CONFIG1_CVBS_Y_C (1 << 10)112#define VEC_CONFIG1_PR_Y_PB (2 << 10)113#define VEC_CONFIG1_RGB (4 << 10)114#define VEC_CONFIG1_Y_C_CVBS (5 << 10)115#define VEC_CONFIG1_C_CVBS_Y (6 << 10)116#define VEC_CONFIG1_C_CVBS_CVBS (7 << 10)117#define VEC_CONFIG1_DIS_CHR BIT(9)118#define VEC_CONFIG1_DIS_LUMA BIT(8)119#define VEC_CONFIG1_YCBCR_IN BIT(6)120#define VEC_CONFIG1_DITHER_TYPE_LFSR 0121#define VEC_CONFIG1_DITHER_TYPE_COUNTER BIT(5)122#define VEC_CONFIG1_DITHER_EN BIT(4)123#define VEC_CONFIG1_CYDELAY BIT(3)124#define VEC_CONFIG1_LUMADIS BIT(2)125#define VEC_CONFIG1_COMPDIS BIT(1)126#define VEC_CONFIG1_CUSTOM_FREQ BIT(0)127 128#define VEC_CONFIG2 0x18c129#define VEC_CONFIG2_PROG_SCAN BIT(15)130#define VEC_CONFIG2_SYNC_ADJ_MASK GENMASK(14, 12)131#define VEC_CONFIG2_SYNC_ADJ(x) (((x) / 2) << 12)132#define VEC_CONFIG2_PBPR_EN BIT(10)133#define VEC_CONFIG2_UV_DIG_DIS BIT(6)134#define VEC_CONFIG2_RGB_DIG_DIS BIT(5)135#define VEC_CONFIG2_TMUX_MASK GENMASK(3, 2)136#define VEC_CONFIG2_TMUX_DRIVE0 (0 << 2)137#define VEC_CONFIG2_TMUX_RG_COMP (1 << 2)138#define VEC_CONFIG2_TMUX_UV_YC (2 << 2)139#define VEC_CONFIG2_TMUX_SYNC_YC (3 << 2)140 141#define VEC_INTERRUPT_CONTROL 0x190142#define VEC_INTERRUPT_STATUS 0x194143 144/*145 * Db center frequency for SECAM; the clock for this is the same as for146 * VEC_FREQ3_2/VEC_FREQ1_0, which is used for Dr center frequency.147 *148 * This is specified as 4250000 Hz, which corresponds to 0x284BDA13.149 * That is also the default value, so no need to set it explicitly.150 */151#define VEC_FCW_SECAM_B 0x198152#define VEC_SECAM_GAIN_VAL 0x19c153 154#define VEC_CONFIG3 0x1a0155#define VEC_CONFIG3_HORIZ_LEN_STD (0 << 0)156#define VEC_CONFIG3_HORIZ_LEN_MPEG1_SIF (1 << 0)157#define VEC_CONFIG3_SHAPE_NON_LINEAR BIT(1)158 159#define VEC_STATUS0 0x200160#define VEC_MASK0 0x204161 162#define VEC_CFG 0x208163#define VEC_CFG_SG_MODE_MASK GENMASK(6, 5)164#define VEC_CFG_SG_MODE(x) ((x) << 5)165#define VEC_CFG_SG_EN BIT(4)166#define VEC_CFG_VEC_EN BIT(3)167#define VEC_CFG_MB_EN BIT(2)168#define VEC_CFG_ENABLE BIT(1)169#define VEC_CFG_TB_EN BIT(0)170 171#define VEC_DAC_TEST 0x20c172 173#define VEC_DAC_CONFIG 0x210174#define VEC_DAC_CONFIG_LDO_BIAS_CTRL(x) ((x) << 24)175#define VEC_DAC_CONFIG_DRIVER_CTRL(x) ((x) << 16)176#define VEC_DAC_CONFIG_DAC_CTRL(x) (x)177 178#define VEC_DAC_MISC 0x214179#define VEC_DAC_MISC_VCD_CTRL_MASK GENMASK(31, 16)180#define VEC_DAC_MISC_VCD_CTRL(x) ((x) << 16)181#define VEC_DAC_MISC_VID_ACT BIT(8)182#define VEC_DAC_MISC_VCD_PWRDN BIT(6)183#define VEC_DAC_MISC_BIAS_PWRDN BIT(5)184#define VEC_DAC_MISC_DAC_PWRDN BIT(2)185#define VEC_DAC_MISC_LDO_PWRDN BIT(1)186#define VEC_DAC_MISC_DAC_RST_N BIT(0)187 188 189struct vc4_vec_variant {190 u32 dac_config;191};192 193/* General VEC hardware state. */194struct vc4_vec {195 struct vc4_encoder encoder;196 struct drm_connector connector;197 198 struct platform_device *pdev;199 const struct vc4_vec_variant *variant;200 201 void __iomem *regs;202 203 struct clk *clock;204 205 struct drm_property *legacy_tv_mode_property;206 207 struct debugfs_regset32 regset;208};209 210#define VEC_READ(offset) \211 ({ \212 kunit_fail_current_test("Accessing a register in a unit test!\n"); \213 readl(vec->regs + (offset)); \214 })215 216#define VEC_WRITE(offset, val) \217 do { \218 kunit_fail_current_test("Accessing a register in a unit test!\n"); \219 writel(val, vec->regs + (offset)); \220 } while (0)221 222#define encoder_to_vc4_vec(_encoder) \223 container_of_const(_encoder, struct vc4_vec, encoder.base)224 225#define connector_to_vc4_vec(_connector) \226 container_of_const(_connector, struct vc4_vec, connector)227 228enum vc4_vec_tv_mode_id {229 VC4_VEC_TV_MODE_NTSC,230 VC4_VEC_TV_MODE_NTSC_J,231 VC4_VEC_TV_MODE_PAL,232 VC4_VEC_TV_MODE_PAL_M,233 VC4_VEC_TV_MODE_NTSC_443,234 VC4_VEC_TV_MODE_PAL_60,235 VC4_VEC_TV_MODE_PAL_N,236 VC4_VEC_TV_MODE_SECAM,237 VC4_VEC_TV_MODE_MONOCHROME,238};239 240struct vc4_vec_tv_mode {241 unsigned int mode;242 u16 expected_htotal;243 u32 config0;244 u32 config1;245 u32 custom_freq;246};247 248static const struct debugfs_reg32 vec_regs[] = {249 VC4_REG32(VEC_WSE_CONTROL),250 VC4_REG32(VEC_WSE_WSS_DATA),251 VC4_REG32(VEC_WSE_VPS_DATA1),252 VC4_REG32(VEC_WSE_VPS_CONTROL),253 VC4_REG32(VEC_REVID),254 VC4_REG32(VEC_CONFIG0),255 VC4_REG32(VEC_SCHPH),256 VC4_REG32(VEC_CLMP0_START),257 VC4_REG32(VEC_CLMP0_END),258 VC4_REG32(VEC_FREQ3_2),259 VC4_REG32(VEC_FREQ1_0),260 VC4_REG32(VEC_CONFIG1),261 VC4_REG32(VEC_CONFIG2),262 VC4_REG32(VEC_INTERRUPT_CONTROL),263 VC4_REG32(VEC_INTERRUPT_STATUS),264 VC4_REG32(VEC_FCW_SECAM_B),265 VC4_REG32(VEC_SECAM_GAIN_VAL),266 VC4_REG32(VEC_CONFIG3),267 VC4_REG32(VEC_STATUS0),268 VC4_REG32(VEC_MASK0),269 VC4_REG32(VEC_CFG),270 VC4_REG32(VEC_DAC_TEST),271 VC4_REG32(VEC_DAC_CONFIG),272 VC4_REG32(VEC_DAC_MISC),273};274 275static const struct vc4_vec_tv_mode vc4_vec_tv_modes[] = {276 {277 .mode = DRM_MODE_TV_MODE_NTSC,278 .expected_htotal = 858,279 .config0 = VEC_CONFIG0_NTSC_STD | VEC_CONFIG0_PDEN,280 .config1 = VEC_CONFIG1_C_CVBS_CVBS,281 },282 {283 .mode = DRM_MODE_TV_MODE_NTSC_443,284 .expected_htotal = 858,285 .config0 = VEC_CONFIG0_NTSC_STD,286 .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ,287 .custom_freq = 0x2a098acb,288 },289 {290 .mode = DRM_MODE_TV_MODE_NTSC_J,291 .expected_htotal = 858,292 .config0 = VEC_CONFIG0_NTSC_STD,293 .config1 = VEC_CONFIG1_C_CVBS_CVBS,294 },295 {296 .mode = DRM_MODE_TV_MODE_PAL,297 .expected_htotal = 864,298 .config0 = VEC_CONFIG0_PAL_BDGHI_STD,299 .config1 = VEC_CONFIG1_C_CVBS_CVBS,300 },301 {302 /* PAL-60 */303 .mode = DRM_MODE_TV_MODE_PAL,304 .expected_htotal = 858,305 .config0 = VEC_CONFIG0_PAL_M_STD,306 .config1 = VEC_CONFIG1_C_CVBS_CVBS | VEC_CONFIG1_CUSTOM_FREQ,307 .custom_freq = 0x2a098acb,308 },309 {310 .mode = DRM_MODE_TV_MODE_PAL_M,311 .expected_htotal = 858,312 .config0 = VEC_CONFIG0_PAL_M_STD,313 .config1 = VEC_CONFIG1_C_CVBS_CVBS,314 },315 {316 .mode = DRM_MODE_TV_MODE_PAL_N,317 .expected_htotal = 864,318 .config0 = VEC_CONFIG0_PAL_N_STD,319 .config1 = VEC_CONFIG1_C_CVBS_CVBS,320 },321 {322 .mode = DRM_MODE_TV_MODE_SECAM,323 .expected_htotal = 864,324 .config0 = VEC_CONFIG0_SECAM_STD,325 .config1 = VEC_CONFIG1_C_CVBS_CVBS,326 .custom_freq = 0x29c71c72,327 },328 {329 /* 50Hz mono */330 .mode = DRM_MODE_TV_MODE_MONOCHROME,331 .expected_htotal = 864,332 .config0 = VEC_CONFIG0_PAL_BDGHI_STD | VEC_CONFIG0_BURDIS |333 VEC_CONFIG0_CHRDIS,334 .config1 = VEC_CONFIG1_C_CVBS_CVBS,335 },336 {337 /* 60Hz mono */338 .mode = DRM_MODE_TV_MODE_MONOCHROME,339 .expected_htotal = 858,340 .config0 = VEC_CONFIG0_PAL_M_STD | VEC_CONFIG0_BURDIS |341 VEC_CONFIG0_CHRDIS,342 .config1 = VEC_CONFIG1_C_CVBS_CVBS,343 },344};345 346static inline const struct vc4_vec_tv_mode *347vc4_vec_tv_mode_lookup(unsigned int mode, u16 htotal)348{349 unsigned int i;350 351 for (i = 0; i < ARRAY_SIZE(vc4_vec_tv_modes); i++) {352 const struct vc4_vec_tv_mode *tv_mode = &vc4_vec_tv_modes[i];353 354 if (tv_mode->mode == mode &&355 tv_mode->expected_htotal == htotal)356 return tv_mode;357 }358 359 return NULL;360}361 362static const struct drm_prop_enum_list legacy_tv_mode_names[] = {363 { VC4_VEC_TV_MODE_NTSC, "NTSC", },364 { VC4_VEC_TV_MODE_NTSC_443, "NTSC-443", },365 { VC4_VEC_TV_MODE_NTSC_J, "NTSC-J", },366 { VC4_VEC_TV_MODE_PAL, "PAL", },367 { VC4_VEC_TV_MODE_PAL_60, "PAL-60", },368 { VC4_VEC_TV_MODE_PAL_M, "PAL-M", },369 { VC4_VEC_TV_MODE_PAL_N, "PAL-N", },370 { VC4_VEC_TV_MODE_SECAM, "SECAM", },371 { VC4_VEC_TV_MODE_MONOCHROME, "Mono", },372};373 374static enum drm_connector_status375vc4_vec_connector_detect(struct drm_connector *connector, bool force)376{377 return connector_status_unknown;378}379 380static void vc4_vec_connector_reset(struct drm_connector *connector)381{382 drm_atomic_helper_connector_reset(connector);383 drm_atomic_helper_connector_tv_reset(connector);384}385 386static int387vc4_vec_connector_set_property(struct drm_connector *connector,388 struct drm_connector_state *state,389 struct drm_property *property,390 uint64_t val)391{392 struct vc4_vec *vec = connector_to_vc4_vec(connector);393 394 if (property != vec->legacy_tv_mode_property)395 return -EINVAL;396 397 switch (val) {398 case VC4_VEC_TV_MODE_NTSC:399 state->tv.mode = DRM_MODE_TV_MODE_NTSC;400 break;401 402 case VC4_VEC_TV_MODE_NTSC_443:403 state->tv.mode = DRM_MODE_TV_MODE_NTSC_443;404 break;405 406 case VC4_VEC_TV_MODE_NTSC_J:407 state->tv.mode = DRM_MODE_TV_MODE_NTSC_J;408 break;409 410 case VC4_VEC_TV_MODE_PAL:411 case VC4_VEC_TV_MODE_PAL_60:412 state->tv.mode = DRM_MODE_TV_MODE_PAL;413 break;414 415 case VC4_VEC_TV_MODE_PAL_M:416 state->tv.mode = DRM_MODE_TV_MODE_PAL_M;417 break;418 419 case VC4_VEC_TV_MODE_PAL_N:420 state->tv.mode = DRM_MODE_TV_MODE_PAL_N;421 break;422 423 case VC4_VEC_TV_MODE_SECAM:424 state->tv.mode = DRM_MODE_TV_MODE_SECAM;425 break;426 427 case VC4_VEC_TV_MODE_MONOCHROME:428 state->tv.mode = DRM_MODE_TV_MODE_MONOCHROME;429 break;430 431 default:432 return -EINVAL;433 }434 435 return 0;436}437 438static int439vc4_vec_connector_get_property(struct drm_connector *connector,440 const struct drm_connector_state *state,441 struct drm_property *property,442 uint64_t *val)443{444 struct vc4_vec *vec = connector_to_vc4_vec(connector);445 446 if (property != vec->legacy_tv_mode_property)447 return -EINVAL;448 449 switch (state->tv.mode) {450 case DRM_MODE_TV_MODE_NTSC:451 *val = VC4_VEC_TV_MODE_NTSC;452 break;453 454 case DRM_MODE_TV_MODE_NTSC_443:455 *val = VC4_VEC_TV_MODE_NTSC_443;456 break;457 458 case DRM_MODE_TV_MODE_NTSC_J:459 *val = VC4_VEC_TV_MODE_NTSC_J;460 break;461 462 case DRM_MODE_TV_MODE_PAL:463 *val = VC4_VEC_TV_MODE_PAL;464 break;465 466 case DRM_MODE_TV_MODE_PAL_M:467 *val = VC4_VEC_TV_MODE_PAL_M;468 break;469 470 case DRM_MODE_TV_MODE_PAL_N:471 *val = VC4_VEC_TV_MODE_PAL_N;472 break;473 474 case DRM_MODE_TV_MODE_SECAM:475 *val = VC4_VEC_TV_MODE_SECAM;476 break;477 478 case DRM_MODE_TV_MODE_MONOCHROME:479 *val = VC4_VEC_TV_MODE_MONOCHROME;480 break;481 482 default:483 return -EINVAL;484 }485 486 return 0;487}488 489static const struct drm_connector_funcs vc4_vec_connector_funcs = {490 .detect = vc4_vec_connector_detect,491 .fill_modes = drm_helper_probe_single_connector_modes,492 .reset = vc4_vec_connector_reset,493 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,494 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,495 .atomic_get_property = vc4_vec_connector_get_property,496 .atomic_set_property = vc4_vec_connector_set_property,497};498 499static const struct drm_connector_helper_funcs vc4_vec_connector_helper_funcs = {500 .atomic_check = drm_atomic_helper_connector_tv_check,501 .get_modes = drm_connector_helper_tv_get_modes,502};503 504static int vc4_vec_connector_init(struct drm_device *dev, struct vc4_vec *vec)505{506 struct drm_connector *connector = &vec->connector;507 struct drm_property *prop;508 int ret;509 510 connector->interlace_allowed = true;511 512 ret = drmm_connector_init(dev, connector, &vc4_vec_connector_funcs,513 DRM_MODE_CONNECTOR_Composite, NULL);514 if (ret)515 return ret;516 517 drm_connector_helper_add(connector, &vc4_vec_connector_helper_funcs);518 519 drm_object_attach_property(&connector->base,520 dev->mode_config.tv_mode_property,521 DRM_MODE_TV_MODE_NTSC);522 523 prop = drm_property_create_enum(dev, 0, "mode",524 legacy_tv_mode_names,525 ARRAY_SIZE(legacy_tv_mode_names));526 if (!prop)527 return -ENOMEM;528 vec->legacy_tv_mode_property = prop;529 530 drm_object_attach_property(&connector->base, prop, VC4_VEC_TV_MODE_NTSC);531 532 drm_connector_attach_tv_margin_properties(connector);533 534 drm_connector_attach_encoder(connector, &vec->encoder.base);535 536 return 0;537}538 539static void vc4_vec_encoder_disable(struct drm_encoder *encoder,540 struct drm_atomic_state *state)541{542 struct drm_device *drm = encoder->dev;543 struct vc4_vec *vec = encoder_to_vc4_vec(encoder);544 int idx, ret;545 546 if (!drm_dev_enter(drm, &idx))547 return;548 549 VEC_WRITE(VEC_CFG, 0);550 VEC_WRITE(VEC_DAC_MISC,551 VEC_DAC_MISC_VCD_PWRDN |552 VEC_DAC_MISC_BIAS_PWRDN |553 VEC_DAC_MISC_DAC_PWRDN |554 VEC_DAC_MISC_LDO_PWRDN);555 556 clk_disable_unprepare(vec->clock);557 558 ret = pm_runtime_put(&vec->pdev->dev);559 if (ret < 0) {560 drm_err(drm, "Failed to release power domain: %d\n", ret);561 goto err_dev_exit;562 }563 564 drm_dev_exit(idx);565 return;566 567err_dev_exit:568 drm_dev_exit(idx);569}570 571static void vc4_vec_encoder_enable(struct drm_encoder *encoder,572 struct drm_atomic_state *state)573{574 struct drm_device *drm = encoder->dev;575 struct vc4_vec *vec = encoder_to_vc4_vec(encoder);576 struct drm_connector *connector = &vec->connector;577 struct drm_connector_state *conn_state =578 drm_atomic_get_new_connector_state(state, connector);579 struct drm_display_mode *adjusted_mode =580 &encoder->crtc->state->adjusted_mode;581 const struct vc4_vec_tv_mode *tv_mode;582 int idx, ret;583 584 if (!drm_dev_enter(drm, &idx))585 return;586 587 tv_mode = vc4_vec_tv_mode_lookup(conn_state->tv.mode,588 adjusted_mode->htotal);589 if (!tv_mode)590 goto err_dev_exit;591 592 ret = pm_runtime_resume_and_get(&vec->pdev->dev);593 if (ret < 0) {594 drm_err(drm, "Failed to retain power domain: %d\n", ret);595 goto err_dev_exit;596 }597 598 /*599 * We need to set the clock rate each time we enable the encoder600 * because there's a chance we share the same parent with the HDMI601 * clock, and both drivers are requesting different rates.602 * The good news is, these 2 encoders cannot be enabled at the same603 * time, thus preventing incompatible rate requests.604 */605 ret = clk_set_rate(vec->clock, 108000000);606 if (ret) {607 drm_err(drm, "Failed to set clock rate: %d\n", ret);608 goto err_put_runtime_pm;609 }610 611 ret = clk_prepare_enable(vec->clock);612 if (ret) {613 drm_err(drm, "Failed to turn on core clock: %d\n", ret);614 goto err_put_runtime_pm;615 }616 617 /* Reset the different blocks */618 VEC_WRITE(VEC_WSE_RESET, 1);619 VEC_WRITE(VEC_SOFT_RESET, 1);620 621 /* Disable the CGSM-A and WSE blocks */622 VEC_WRITE(VEC_WSE_CONTROL, 0);623 624 /* Write config common to all modes. */625 626 /*627 * Color subcarrier phase: phase = 360 * SCHPH / 256.628 * 0x28 <=> 39.375 deg.629 */630 VEC_WRITE(VEC_SCHPH, 0x28);631 632 /*633 * Reset to default values.634 */635 VEC_WRITE(VEC_CLMP0_START, 0xac);636 VEC_WRITE(VEC_CLMP0_END, 0xec);637 VEC_WRITE(VEC_CONFIG2,638 VEC_CONFIG2_UV_DIG_DIS |639 VEC_CONFIG2_RGB_DIG_DIS |640 ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ? 0 : VEC_CONFIG2_PROG_SCAN));641 VEC_WRITE(VEC_CONFIG3, VEC_CONFIG3_HORIZ_LEN_STD);642 VEC_WRITE(VEC_DAC_CONFIG, vec->variant->dac_config);643 644 /* Mask all interrupts. */645 VEC_WRITE(VEC_MASK0, 0);646 647 VEC_WRITE(VEC_CONFIG0, tv_mode->config0);648 VEC_WRITE(VEC_CONFIG1, tv_mode->config1);649 650 if (tv_mode->custom_freq) {651 VEC_WRITE(VEC_FREQ3_2,652 (tv_mode->custom_freq >> 16) & 0xffff);653 VEC_WRITE(VEC_FREQ1_0,654 tv_mode->custom_freq & 0xffff);655 }656 657 VEC_WRITE(VEC_DAC_MISC,658 VEC_DAC_MISC_VID_ACT | VEC_DAC_MISC_DAC_RST_N);659 VEC_WRITE(VEC_CFG, VEC_CFG_VEC_EN);660 661 drm_dev_exit(idx);662 return;663 664err_put_runtime_pm:665 pm_runtime_put(&vec->pdev->dev);666err_dev_exit:667 drm_dev_exit(idx);668}669 670static int vc4_vec_encoder_atomic_check(struct drm_encoder *encoder,671 struct drm_crtc_state *crtc_state,672 struct drm_connector_state *conn_state)673{674 const struct drm_display_mode *mode = &crtc_state->adjusted_mode;675 const struct vc4_vec_tv_mode *tv_mode;676 677 tv_mode = vc4_vec_tv_mode_lookup(conn_state->tv.mode, mode->htotal);678 if (!tv_mode)679 return -EINVAL;680 681 if (mode->crtc_hdisplay % 4)682 return -EINVAL;683 684 if (!(mode->crtc_hsync_end - mode->crtc_hsync_start))685 return -EINVAL;686 687 switch (mode->htotal) {688 /* NTSC */689 case 858:690 if (mode->crtc_vtotal > 262)691 return -EINVAL;692 693 if (mode->crtc_vdisplay < 1 || mode->crtc_vdisplay > 253)694 return -EINVAL;695 696 if (!(mode->crtc_vsync_start - mode->crtc_vdisplay))697 return -EINVAL;698 699 if ((mode->crtc_vsync_end - mode->crtc_vsync_start) != 3)700 return -EINVAL;701 702 if ((mode->crtc_vtotal - mode->crtc_vsync_end) < 4)703 return -EINVAL;704 705 break;706 707 /* PAL/SECAM */708 case 864:709 if (mode->crtc_vtotal > 312)710 return -EINVAL;711 712 if (mode->crtc_vdisplay < 1 || mode->crtc_vdisplay > 305)713 return -EINVAL;714 715 if (!(mode->crtc_vsync_start - mode->crtc_vdisplay))716 return -EINVAL;717 718 if ((mode->crtc_vsync_end - mode->crtc_vsync_start) != 3)719 return -EINVAL;720 721 if ((mode->crtc_vtotal - mode->crtc_vsync_end) < 2)722 return -EINVAL;723 724 break;725 726 default:727 return -EINVAL;728 }729 730 return 0;731}732 733static const struct drm_encoder_helper_funcs vc4_vec_encoder_helper_funcs = {734 .atomic_check = vc4_vec_encoder_atomic_check,735 .atomic_disable = vc4_vec_encoder_disable,736 .atomic_enable = vc4_vec_encoder_enable,737};738 739static int vc4_vec_late_register(struct drm_encoder *encoder)740{741 struct drm_device *drm = encoder->dev;742 struct vc4_vec *vec = encoder_to_vc4_vec(encoder);743 744 vc4_debugfs_add_regset32(drm, "vec_regs", &vec->regset);745 746 return 0;747}748 749static const struct drm_encoder_funcs vc4_vec_encoder_funcs = {750 .late_register = vc4_vec_late_register,751};752 753static const struct vc4_vec_variant bcm2835_vec_variant = {754 .dac_config = VEC_DAC_CONFIG_DAC_CTRL(0xc) |755 VEC_DAC_CONFIG_DRIVER_CTRL(0xc) |756 VEC_DAC_CONFIG_LDO_BIAS_CTRL(0x46)757};758 759static const struct vc4_vec_variant bcm2711_vec_variant = {760 .dac_config = VEC_DAC_CONFIG_DAC_CTRL(0x0) |761 VEC_DAC_CONFIG_DRIVER_CTRL(0x80) |762 VEC_DAC_CONFIG_LDO_BIAS_CTRL(0x61)763};764 765static const struct of_device_id vc4_vec_dt_match[] = {766 { .compatible = "brcm,bcm2835-vec", .data = &bcm2835_vec_variant },767 { .compatible = "brcm,bcm2711-vec", .data = &bcm2711_vec_variant },768 { /* sentinel */ },769};770 771static int vc4_vec_bind(struct device *dev, struct device *master, void *data)772{773 struct platform_device *pdev = to_platform_device(dev);774 struct drm_device *drm = dev_get_drvdata(master);775 struct vc4_vec *vec;776 int ret;777 778 ret = drm_mode_create_tv_properties(drm,779 BIT(DRM_MODE_TV_MODE_NTSC) |780 BIT(DRM_MODE_TV_MODE_NTSC_443) |781 BIT(DRM_MODE_TV_MODE_NTSC_J) |782 BIT(DRM_MODE_TV_MODE_PAL) |783 BIT(DRM_MODE_TV_MODE_PAL_M) |784 BIT(DRM_MODE_TV_MODE_PAL_N) |785 BIT(DRM_MODE_TV_MODE_SECAM) |786 BIT(DRM_MODE_TV_MODE_MONOCHROME));787 if (ret)788 return ret;789 790 vec = drmm_kzalloc(drm, sizeof(*vec), GFP_KERNEL);791 if (!vec)792 return -ENOMEM;793 794 vec->encoder.type = VC4_ENCODER_TYPE_VEC;795 vec->pdev = pdev;796 vec->variant = (const struct vc4_vec_variant *)797 of_device_get_match_data(dev);798 vec->regs = vc4_ioremap_regs(pdev, 0);799 if (IS_ERR(vec->regs))800 return PTR_ERR(vec->regs);801 vec->regset.base = vec->regs;802 vec->regset.regs = vec_regs;803 vec->regset.nregs = ARRAY_SIZE(vec_regs);804 805 vec->clock = devm_clk_get(dev, NULL);806 if (IS_ERR(vec->clock)) {807 ret = PTR_ERR(vec->clock);808 if (ret != -EPROBE_DEFER)809 drm_err(drm, "Failed to get clock: %d\n", ret);810 return ret;811 }812 813 ret = devm_pm_runtime_enable(dev);814 if (ret)815 return ret;816 817 ret = drmm_encoder_init(drm, &vec->encoder.base,818 &vc4_vec_encoder_funcs,819 DRM_MODE_ENCODER_TVDAC,820 NULL);821 if (ret)822 return ret;823 824 drm_encoder_helper_add(&vec->encoder.base, &vc4_vec_encoder_helper_funcs);825 826 ret = vc4_vec_connector_init(drm, vec);827 if (ret)828 return ret;829 830 dev_set_drvdata(dev, vec);831 832 return 0;833}834 835static const struct component_ops vc4_vec_ops = {836 .bind = vc4_vec_bind,837};838 839static int vc4_vec_dev_probe(struct platform_device *pdev)840{841 return component_add(&pdev->dev, &vc4_vec_ops);842}843 844static void vc4_vec_dev_remove(struct platform_device *pdev)845{846 component_del(&pdev->dev, &vc4_vec_ops);847}848 849struct platform_driver vc4_vec_driver = {850 .probe = vc4_vec_dev_probe,851 .remove_new = vc4_vec_dev_remove,852 .driver = {853 .name = "vc4_vec",854 .of_match_table = vc4_vec_dt_match,855 },856};857