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1/*2 * Copyright (C) 2015 Red Hat, Inc.3 * All Rights Reserved.4 *5 * Permission is hereby granted, free of charge, to any person obtaining6 * a copy of this software and associated documentation files (the7 * "Software"), to deal in the Software without restriction, including8 * without limitation the rights to use, copy, modify, merge, publish,9 * distribute, sublicense, and/or sell copies of the Software, and to10 * permit persons to whom the Software is furnished to do so, subject to11 * the following conditions:12 *13 * The above copyright notice and this permission notice (including the14 * next paragraph) shall be included in all copies or substantial15 * portions of the Software.16 *17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.24 */25 26#ifndef VIRTIO_DRV_H27#define VIRTIO_DRV_H28 29#include <linux/dma-direction.h>30#include <linux/virtio.h>31#include <linux/virtio_ids.h>32#include <linux/virtio_config.h>33#include <linux/virtio_gpu.h>34 35#include <drm/drm_atomic.h>36#include <drm/drm_drv.h>37#include <drm/drm_encoder.h>38#include <drm/drm_fourcc.h>39#include <drm/drm_framebuffer.h>40#include <drm/drm_gem.h>41#include <drm/drm_gem_shmem_helper.h>42#include <drm/drm_ioctl.h>43#include <drm/drm_probe_helper.h>44#include <drm/virtgpu_drm.h>45 46#define DRIVER_NAME "virtio_gpu"47#define DRIVER_DESC "virtio GPU"48#define DRIVER_DATE "0"49 50#define DRIVER_MAJOR 051#define DRIVER_MINOR 152#define DRIVER_PATCHLEVEL 053 54#define STATE_INITIALIZING 055#define STATE_OK 156#define STATE_ERR 257 58#define MAX_CAPSET_ID 6359#define MAX_RINGS 6460 61/* See virtio_gpu_ctx_create. One additional character for NULL terminator. */62#define DEBUG_NAME_MAX_LEN 6563 64struct virtio_gpu_object_params {65 unsigned long size;66 bool dumb;67 /* 3d */68 bool virgl;69 bool blob;70 71 /* classic resources only */72 uint32_t format;73 uint32_t width;74 uint32_t height;75 uint32_t target;76 uint32_t bind;77 uint32_t depth;78 uint32_t array_size;79 uint32_t last_level;80 uint32_t nr_samples;81 uint32_t flags;82 83 /* blob resources only */84 uint32_t ctx_id;85 uint32_t blob_mem;86 uint32_t blob_flags;87 uint64_t blob_id;88};89 90struct virtio_gpu_object {91 struct drm_gem_shmem_object base;92 uint32_t hw_res_handle;93 bool dumb;94 bool created;95 bool host3d_blob, guest_blob;96 uint32_t blob_mem, blob_flags;97 98 int uuid_state;99 uuid_t uuid;100};101#define gem_to_virtio_gpu_obj(gobj) \102 container_of((gobj), struct virtio_gpu_object, base.base)103 104struct virtio_gpu_object_shmem {105 struct virtio_gpu_object base;106};107 108struct virtio_gpu_object_vram {109 struct virtio_gpu_object base;110 uint32_t map_state;111 uint32_t map_info;112 struct drm_mm_node vram_node;113};114 115#define to_virtio_gpu_shmem(virtio_gpu_object) \116 container_of((virtio_gpu_object), struct virtio_gpu_object_shmem, base)117 118#define to_virtio_gpu_vram(virtio_gpu_object) \119 container_of((virtio_gpu_object), struct virtio_gpu_object_vram, base)120 121struct virtio_gpu_object_array {122 struct ww_acquire_ctx ticket;123 struct list_head next;124 u32 nents, total;125 struct drm_gem_object *objs[] __counted_by(total);126};127 128struct virtio_gpu_vbuffer;129struct virtio_gpu_device;130 131typedef void (*virtio_gpu_resp_cb)(struct virtio_gpu_device *vgdev,132 struct virtio_gpu_vbuffer *vbuf);133 134struct virtio_gpu_fence_driver {135 atomic64_t last_fence_id;136 uint64_t current_fence_id;137 uint64_t context;138 struct list_head fences;139 spinlock_t lock;140};141 142struct virtio_gpu_fence_event {143 struct drm_pending_event base;144 struct drm_event event;145};146 147struct virtio_gpu_fence {148 struct dma_fence f;149 uint32_t ring_idx;150 uint64_t fence_id;151 bool emit_fence_info;152 struct virtio_gpu_fence_event *e;153 struct virtio_gpu_fence_driver *drv;154 struct list_head node;155};156 157struct virtio_gpu_vbuffer {158 char *buf;159 int size;160 161 void *data_buf;162 uint32_t data_size;163 164 char *resp_buf;165 int resp_size;166 virtio_gpu_resp_cb resp_cb;167 void *resp_cb_data;168 169 struct virtio_gpu_object_array *objs;170 struct list_head list;171 172 uint32_t seqno;173};174 175struct virtio_gpu_output {176 int index;177 struct drm_crtc crtc;178 struct drm_connector conn;179 struct drm_encoder enc;180 struct virtio_gpu_display_one info;181 struct virtio_gpu_update_cursor cursor;182 const struct drm_edid *drm_edid;183 int cur_x;184 int cur_y;185 bool needs_modeset;186};187#define drm_crtc_to_virtio_gpu_output(x) \188 container_of(x, struct virtio_gpu_output, crtc)189 190struct virtio_gpu_framebuffer {191 struct drm_framebuffer base;192 struct virtio_gpu_fence *fence;193};194#define to_virtio_gpu_framebuffer(x) \195 container_of(x, struct virtio_gpu_framebuffer, base)196 197struct virtio_gpu_queue {198 struct virtqueue *vq;199 spinlock_t qlock;200 wait_queue_head_t ack_queue;201 struct work_struct dequeue_work;202 uint32_t seqno;203};204 205struct virtio_gpu_drv_capset {206 uint32_t id;207 uint32_t max_version;208 uint32_t max_size;209};210 211struct virtio_gpu_drv_cap_cache {212 struct list_head head;213 void *caps_cache;214 uint32_t id;215 uint32_t version;216 uint32_t size;217 atomic_t is_valid;218};219 220struct virtio_gpu_device {221 struct drm_device *ddev;222 223 struct virtio_device *vdev;224 225 struct virtio_gpu_output outputs[VIRTIO_GPU_MAX_SCANOUTS];226 uint32_t num_scanouts;227 228 struct virtio_gpu_queue ctrlq;229 struct virtio_gpu_queue cursorq;230 struct kmem_cache *vbufs;231 232 atomic_t pending_commands;233 234 struct ida resource_ida;235 236 wait_queue_head_t resp_wq;237 /* current display info */238 spinlock_t display_info_lock;239 bool display_info_pending;240 241 struct virtio_gpu_fence_driver fence_drv;242 243 struct ida ctx_id_ida;244 245 bool has_virgl_3d;246 bool has_edid;247 bool has_indirect;248 bool has_resource_assign_uuid;249 bool has_resource_blob;250 bool has_host_visible;251 bool has_context_init;252 struct virtio_shm_region host_visible_region;253 struct drm_mm host_visible_mm;254 255 struct work_struct config_changed_work;256 257 struct work_struct obj_free_work;258 spinlock_t obj_free_lock;259 struct list_head obj_free_list;260 261 struct virtio_gpu_drv_capset *capsets;262 uint32_t num_capsets;263 uint64_t capset_id_mask;264 struct list_head cap_cache;265 266 /* protects uuid state when exporting */267 spinlock_t resource_export_lock;268 /* protects map state and host_visible_mm */269 spinlock_t host_visible_lock;270};271 272struct virtio_gpu_fpriv {273 uint32_t ctx_id;274 uint32_t context_init;275 bool context_created;276 uint32_t num_rings;277 uint64_t base_fence_ctx;278 uint64_t ring_idx_mask;279 struct mutex context_lock;280 char debug_name[DEBUG_NAME_MAX_LEN];281 bool explicit_debug_name;282};283 284/* virtgpu_ioctl.c */285#define DRM_VIRTIO_NUM_IOCTLS 12286extern struct drm_ioctl_desc virtio_gpu_ioctls[DRM_VIRTIO_NUM_IOCTLS];287void virtio_gpu_create_context(struct drm_device *dev, struct drm_file *file);288 289/* virtgpu_kms.c */290int virtio_gpu_init(struct virtio_device *vdev, struct drm_device *dev);291void virtio_gpu_deinit(struct drm_device *dev);292void virtio_gpu_release(struct drm_device *dev);293int virtio_gpu_driver_open(struct drm_device *dev, struct drm_file *file);294void virtio_gpu_driver_postclose(struct drm_device *dev, struct drm_file *file);295 296/* virtgpu_gem.c */297int virtio_gpu_gem_object_open(struct drm_gem_object *obj,298 struct drm_file *file);299void virtio_gpu_gem_object_close(struct drm_gem_object *obj,300 struct drm_file *file);301int virtio_gpu_mode_dumb_create(struct drm_file *file_priv,302 struct drm_device *dev,303 struct drm_mode_create_dumb *args);304int virtio_gpu_mode_dumb_mmap(struct drm_file *file_priv,305 struct drm_device *dev,306 uint32_t handle, uint64_t *offset_p);307 308struct virtio_gpu_object_array *virtio_gpu_array_alloc(u32 nents);309struct virtio_gpu_object_array*310virtio_gpu_array_from_handles(struct drm_file *drm_file, u32 *handles, u32 nents);311void virtio_gpu_array_add_obj(struct virtio_gpu_object_array *objs,312 struct drm_gem_object *obj);313int virtio_gpu_array_lock_resv(struct virtio_gpu_object_array *objs);314void virtio_gpu_array_unlock_resv(struct virtio_gpu_object_array *objs);315void virtio_gpu_array_add_fence(struct virtio_gpu_object_array *objs,316 struct dma_fence *fence);317void virtio_gpu_array_put_free(struct virtio_gpu_object_array *objs);318void virtio_gpu_array_put_free_delayed(struct virtio_gpu_device *vgdev,319 struct virtio_gpu_object_array *objs);320void virtio_gpu_array_put_free_work(struct work_struct *work);321 322/* virtgpu_vq.c */323int virtio_gpu_alloc_vbufs(struct virtio_gpu_device *vgdev);324void virtio_gpu_free_vbufs(struct virtio_gpu_device *vgdev);325void virtio_gpu_cmd_create_resource(struct virtio_gpu_device *vgdev,326 struct virtio_gpu_object *bo,327 struct virtio_gpu_object_params *params,328 struct virtio_gpu_object_array *objs,329 struct virtio_gpu_fence *fence);330void virtio_gpu_cmd_unref_resource(struct virtio_gpu_device *vgdev,331 struct virtio_gpu_object *bo);332void virtio_gpu_cmd_transfer_to_host_2d(struct virtio_gpu_device *vgdev,333 uint64_t offset,334 uint32_t width, uint32_t height,335 uint32_t x, uint32_t y,336 struct virtio_gpu_object_array *objs,337 struct virtio_gpu_fence *fence);338void virtio_gpu_cmd_resource_flush(struct virtio_gpu_device *vgdev,339 uint32_t resource_id,340 uint32_t x, uint32_t y,341 uint32_t width, uint32_t height,342 struct virtio_gpu_object_array *objs,343 struct virtio_gpu_fence *fence);344void virtio_gpu_cmd_set_scanout(struct virtio_gpu_device *vgdev,345 uint32_t scanout_id, uint32_t resource_id,346 uint32_t width, uint32_t height,347 uint32_t x, uint32_t y);348void virtio_gpu_object_attach(struct virtio_gpu_device *vgdev,349 struct virtio_gpu_object *obj,350 struct virtio_gpu_mem_entry *ents,351 unsigned int nents);352void virtio_gpu_cursor_ping(struct virtio_gpu_device *vgdev,353 struct virtio_gpu_output *output);354int virtio_gpu_cmd_get_display_info(struct virtio_gpu_device *vgdev);355int virtio_gpu_cmd_get_capset_info(struct virtio_gpu_device *vgdev, int idx);356int virtio_gpu_cmd_get_capset(struct virtio_gpu_device *vgdev,357 int idx, int version,358 struct virtio_gpu_drv_cap_cache **cache_p);359int virtio_gpu_cmd_get_edids(struct virtio_gpu_device *vgdev);360void virtio_gpu_cmd_context_create(struct virtio_gpu_device *vgdev, uint32_t id,361 uint32_t context_init, uint32_t nlen,362 const char *name);363void virtio_gpu_cmd_context_destroy(struct virtio_gpu_device *vgdev,364 uint32_t id);365void virtio_gpu_cmd_context_attach_resource(struct virtio_gpu_device *vgdev,366 uint32_t ctx_id,367 struct virtio_gpu_object_array *objs);368void virtio_gpu_cmd_context_detach_resource(struct virtio_gpu_device *vgdev,369 uint32_t ctx_id,370 struct virtio_gpu_object_array *objs);371void virtio_gpu_cmd_submit(struct virtio_gpu_device *vgdev,372 void *data, uint32_t data_size,373 uint32_t ctx_id,374 struct virtio_gpu_object_array *objs,375 struct virtio_gpu_fence *fence);376void virtio_gpu_cmd_transfer_from_host_3d(struct virtio_gpu_device *vgdev,377 uint32_t ctx_id,378 uint64_t offset, uint32_t level,379 uint32_t stride,380 uint32_t layer_stride,381 struct drm_virtgpu_3d_box *box,382 struct virtio_gpu_object_array *objs,383 struct virtio_gpu_fence *fence);384void virtio_gpu_cmd_transfer_to_host_3d(struct virtio_gpu_device *vgdev,385 uint32_t ctx_id,386 uint64_t offset, uint32_t level,387 uint32_t stride,388 uint32_t layer_stride,389 struct drm_virtgpu_3d_box *box,390 struct virtio_gpu_object_array *objs,391 struct virtio_gpu_fence *fence);392void393virtio_gpu_cmd_resource_create_3d(struct virtio_gpu_device *vgdev,394 struct virtio_gpu_object *bo,395 struct virtio_gpu_object_params *params,396 struct virtio_gpu_object_array *objs,397 struct virtio_gpu_fence *fence);398void virtio_gpu_ctrl_ack(struct virtqueue *vq);399void virtio_gpu_cursor_ack(struct virtqueue *vq);400void virtio_gpu_dequeue_ctrl_func(struct work_struct *work);401void virtio_gpu_dequeue_cursor_func(struct work_struct *work);402void virtio_gpu_notify(struct virtio_gpu_device *vgdev);403 404int405virtio_gpu_cmd_resource_assign_uuid(struct virtio_gpu_device *vgdev,406 struct virtio_gpu_object_array *objs);407 408int virtio_gpu_cmd_map(struct virtio_gpu_device *vgdev,409 struct virtio_gpu_object_array *objs, uint64_t offset);410 411void virtio_gpu_cmd_unmap(struct virtio_gpu_device *vgdev,412 struct virtio_gpu_object *bo);413 414void415virtio_gpu_cmd_resource_create_blob(struct virtio_gpu_device *vgdev,416 struct virtio_gpu_object *bo,417 struct virtio_gpu_object_params *params,418 struct virtio_gpu_mem_entry *ents,419 uint32_t nents);420void421virtio_gpu_cmd_set_scanout_blob(struct virtio_gpu_device *vgdev,422 uint32_t scanout_id,423 struct virtio_gpu_object *bo,424 struct drm_framebuffer *fb,425 uint32_t width, uint32_t height,426 uint32_t x, uint32_t y);427 428/* virtgpu_display.c */429int virtio_gpu_modeset_init(struct virtio_gpu_device *vgdev);430void virtio_gpu_modeset_fini(struct virtio_gpu_device *vgdev);431 432/* virtgpu_plane.c */433uint32_t virtio_gpu_translate_format(uint32_t drm_fourcc);434struct drm_plane *virtio_gpu_plane_init(struct virtio_gpu_device *vgdev,435 enum drm_plane_type type,436 int index);437 438/* virtgpu_fence.c */439struct virtio_gpu_fence *virtio_gpu_fence_alloc(struct virtio_gpu_device *vgdev,440 uint64_t base_fence_ctx,441 uint32_t ring_idx);442void virtio_gpu_fence_emit(struct virtio_gpu_device *vgdev,443 struct virtio_gpu_ctrl_hdr *cmd_hdr,444 struct virtio_gpu_fence *fence);445void virtio_gpu_fence_event_process(struct virtio_gpu_device *vdev,446 u64 fence_id);447 448/* virtgpu_object.c */449void virtio_gpu_cleanup_object(struct virtio_gpu_object *bo);450struct drm_gem_object *virtio_gpu_create_object(struct drm_device *dev,451 size_t size);452int virtio_gpu_object_create(struct virtio_gpu_device *vgdev,453 struct virtio_gpu_object_params *params,454 struct virtio_gpu_object **bo_ptr,455 struct virtio_gpu_fence *fence);456 457bool virtio_gpu_is_shmem(struct virtio_gpu_object *bo);458 459int virtio_gpu_resource_id_get(struct virtio_gpu_device *vgdev,460 uint32_t *resid);461/* virtgpu_prime.c */462int virtio_gpu_resource_assign_uuid(struct virtio_gpu_device *vgdev,463 struct virtio_gpu_object *bo);464struct dma_buf *virtgpu_gem_prime_export(struct drm_gem_object *obj,465 int flags);466struct drm_gem_object *virtgpu_gem_prime_import(struct drm_device *dev,467 struct dma_buf *buf);468struct drm_gem_object *virtgpu_gem_prime_import_sg_table(469 struct drm_device *dev, struct dma_buf_attachment *attach,470 struct sg_table *sgt);471 472/* virtgpu_debugfs.c */473void virtio_gpu_debugfs_init(struct drm_minor *minor);474 475/* virtgpu_vram.c */476bool virtio_gpu_is_vram(struct virtio_gpu_object *bo);477int virtio_gpu_vram_create(struct virtio_gpu_device *vgdev,478 struct virtio_gpu_object_params *params,479 struct virtio_gpu_object **bo_ptr);480struct sg_table *virtio_gpu_vram_map_dma_buf(struct virtio_gpu_object *bo,481 struct device *dev,482 enum dma_data_direction dir);483void virtio_gpu_vram_unmap_dma_buf(struct device *dev,484 struct sg_table *sgt,485 enum dma_data_direction dir);486 487/* virtgpu_submit.c */488int virtio_gpu_execbuffer_ioctl(struct drm_device *dev, void *data,489 struct drm_file *file);490 491#endif492