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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright © 2023 Intel Corporation4 */5 6#ifndef _XE_GPU_COMMANDS_H_7#define _XE_GPU_COMMANDS_H_8 9#include "regs/xe_reg_defs.h"10 11#define XY_CTRL_SURF_COPY_BLT ((2 << 29) | (0x48 << 22) | 3)12#define SRC_ACCESS_TYPE_SHIFT 2113#define DST_ACCESS_TYPE_SHIFT 2014#define CCS_SIZE_MASK GENMASK(17, 8)15#define XE2_CCS_SIZE_MASK GENMASK(18, 9)16#define XY_CTRL_SURF_MOCS_MASK GENMASK(31, 26)17#define XE2_XY_CTRL_SURF_MOCS_INDEX_MASK GENMASK(31, 28)18#define NUM_CCS_BYTES_PER_BLOCK 25619#define NUM_BYTES_PER_CCS_BYTE(_xe) (GRAPHICS_VER(_xe) >= 20 ? 512 : 256)20 21#define XY_FAST_COLOR_BLT_CMD (2 << 29 | 0x44 << 22)22#define XY_FAST_COLOR_BLT_DEPTH_32 (2 << 19)23#define XY_FAST_COLOR_BLT_DW 1624#define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 22)25#define XE2_XY_FAST_COLOR_BLT_MOCS_INDEX_MASK GENMASK(27, 24)26#define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 3127 28#define XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22)29#define XY_FAST_COPY_BLT_DEPTH_32 (3<<24)30#define XY_FAST_COPY_BLT_D1_SRC_TILE4 REG_BIT(31)31#define XY_FAST_COPY_BLT_D1_DST_TILE4 REG_BIT(30)32#define XE2_XY_FAST_COPY_BLT_MOCS_INDEX_MASK GENMASK(23, 20)33 34#define PVC_MEM_SET_CMD (2 << 29 | 0x5b << 22)35#define PVC_MEM_SET_CMD_LEN_DW 736#define PVC_MEM_SET_MATRIX REG_BIT(17)37#define PVC_MEM_SET_DATA_FIELD GENMASK(31, 24)38/* Bspec lists field as [6:0], but index alone is from [6:1] */39#define PVC_MEM_SET_MOCS_INDEX_MASK GENMASK(6, 1)40#define XE2_MEM_SET_MOCS_INDEX_MASK GENMASK(6, 3)41 42#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))43 44#define PIPE_CONTROL0_HDC_PIPELINE_FLUSH BIT(9) /* gen12 */45 46#define PIPE_CONTROL_COMMAND_CACHE_INVALIDATE (1<<29)47#define PIPE_CONTROL_TILE_CACHE_FLUSH (1<<28)48#define PIPE_CONTROL_AMFS_FLUSH (1<<25)49#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24)50#define PIPE_CONTROL_LRI_POST_SYNC BIT(23)51#define PIPE_CONTROL_STORE_DATA_INDEX (1<<21)52#define PIPE_CONTROL_CS_STALL (1<<20)53#define PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET (1<<19)54#define PIPE_CONTROL_TLB_INVALIDATE BIT(18)55#define PIPE_CONTROL_PSD_SYNC (1<<17)56#define PIPE_CONTROL_QW_WRITE (1<<14)57#define PIPE_CONTROL_DEPTH_STALL (1<<13)58#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12)59#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11)60#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10)61#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)62#define PIPE_CONTROL_FLUSH_ENABLE (1<<7)63#define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5)64#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)65#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)66#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)67#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)68#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)69 70#endif71