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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright © 2023 Intel Corporation4 */5 6#ifndef _XE_GSC_COMMANDS_H_7#define _XE_GSC_COMMANDS_H_8 9#include "instructions/xe_instr_defs.h"10 11/*12 * All GSCCS-specific commands have fixed length, so we can include it in the13 * defines. Note that the generic GSC command header structure includes an14 * optional data field in bits 9-21, but there are no commands that actually use15 * it; some of the commands are instead defined as having an extended length16 * field spanning bits 0-15, even if the extra bits are not required because the17 * longest GSCCS command is only 8 dwords. To handle this, the defines below use18 * a single field for both data and len. If we ever get a commands that does19 * actually have data and this approach doesn't work for it we can re-work it20 * at that point.21 */22 23#define GSC_OPCODE REG_GENMASK(28, 22)24#define GSC_CMD_DATA_AND_LEN REG_GENMASK(21, 0)25 26#define __GSC_INSTR(op, dl) \27 (XE_INSTR_GSC | \28 REG_FIELD_PREP(GSC_OPCODE, op) | \29 REG_FIELD_PREP(GSC_CMD_DATA_AND_LEN, dl))30 31#define GSC_HECI_CMD_PKT __GSC_INSTR(0, 6)32 33#define GSC_FW_LOAD __GSC_INSTR(1, 2)34#define GSC_FW_LOAD_LIMIT_VALID REG_BIT(31)35 36#endif37