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1/* SPDX-License-Identifier: MIT */2/*3 * Copyright © 2023 Intel Corporation4 */5 6#ifndef _XE_GSC_REGS_H_7#define _XE_GSC_REGS_H_8 9#include <linux/compiler.h>10#include <linux/types.h>11 12#include "regs/xe_reg_defs.h"13 14/* Definitions of GSC H/W registers, bits, etc */15 16#define MTL_GSC_HECI1_BASE 0x0011600017#define MTL_GSC_HECI2_BASE 0x0011700018 19#define HECI_H_CSR(base) XE_REG((base) + 0x4)20#define HECI_H_CSR_IE REG_BIT(0)21#define HECI_H_CSR_IS REG_BIT(1)22#define HECI_H_CSR_IG REG_BIT(2)23#define HECI_H_CSR_RDY REG_BIT(3)24#define HECI_H_CSR_RST REG_BIT(4)25 26/*27 * The FWSTS register values are FW defined and can be different between28 * HECI1 and HECI229 */30#define HECI_FWSTS1(base) XE_REG((base) + 0xc40)31#define HECI1_FWSTS1_CURRENT_STATE REG_GENMASK(3, 0)32#define HECI1_FWSTS1_CURRENT_STATE_RESET 033#define HECI1_FWSTS1_PROXY_STATE_NORMAL 534#define HECI1_FWSTS1_INIT_COMPLETE REG_BIT(9)35#define HECI_FWSTS2(base) XE_REG((base) + 0xc48)36#define HECI_FWSTS3(base) XE_REG((base) + 0xc60)37#define HECI_FWSTS4(base) XE_REG((base) + 0xc64)38#define HECI_FWSTS5(base) XE_REG((base) + 0xc68)39#define HECI1_FWSTS5_HUC_AUTH_DONE REG_BIT(19)40#define HECI_FWSTS6(base) XE_REG((base) + 0xc6c)41 42#define HECI_H_GS1(base) XE_REG((base) + 0xc4c)43#define HECI_H_GS1_ER_PREP REG_BIT(0)44 45#define GSCI_TIMER_STATUS XE_REG(0x11ca28)46#define GSCI_TIMER_STATUS_VALUE REG_GENMASK(1, 0)47#define GSCI_TIMER_STATUS_RESET_IN_PROGRESS 048#define GSCI_TIMER_STATUS_TIMER_EXPIRED 149#define GSCI_TIMER_STATUS_RESET_COMPLETE 250#define GSCI_TIMER_STATUS_OUT_OF_RESET 351 52#endif53